JP2004200707A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide corrosion-proofing technology for a metal interconnect line formed by chemical mechanical polishing (CMP) method. <P>SOLUTION: The method comprises a process that forms a metal layer containing copper as a main component on primary major face of a wafer having a primary insulating film in which concave groove pattern is formed, a process that eliminates the metal layer on the front surface of the primary insulating film and outside of the concave groove by the CMP, a process that transports the wafer from which the metal layer is removed to a post-cleaning section being made a shielding structure, a process that post-cleans the primary major face of the wafer with alkaline or alkalescent chemicals by scrub or brush cleaning in the post-cleaning section, and a process that carries out spin drying for the primary major face of the wafer to which the post-cleaning is performed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to corrosion prevention of metal wiring formed by a chemical mechanical polishing (CMP) method.

  JP-A-7-135192 (Patent Document 1) discloses that a series of steps from chemical mechanical polishing, wafer reversal standby, physical cleaning, chemical cleaning (spin cleaning), and rinsing are performed without drying the wafer. Discloses a post-polishing treatment method for reducing the particle level after the polishing treatment. The polishing apparatus used in this method has a configuration in which the wafer mount section in the polishing unit is capable of holding the wafer wet, and a unit-to-unit wet transfer mechanism is used for transfer between the polishing unit, the cleaning unit, and the rinsing / drying unit. For transport between the cleaning chambers in the cleaning unit, an in-unit wet transport mechanism is used.

  "Electronic Materials", published by the Industrial Research Council, May 1996, p53 (Non-Patent Document 1) discloses a CMP apparatus for an oxide film composed of a wafer supply unit, a polishing unit, a wafer removal unit, and a dress unit. ing. The wafer is transferred from the load cassette to the polishing section by the transfer robot and subjected to polishing processing. The polished wafer is scrub-cleaned on its front and back surfaces with pure water, stored in an unload cassette, and stored in water.

  Similarly, "Electronic Materials", May 1996, p62 (Non-Patent Document 2) is an object of post-cleaning from a polishing process (to remove undesired particles such as abrasive grains during polishing from a wafer surface). The cleaning is generally performed before the surface of the wafer is naturally dried.

Similarly, “Electronic Materials”, May 1996, p33 (Non-patent Document 3), a polishing plate (platen) for primary polishing, a polishing plate for secondary polishing (or buffing), and a wafer after polishing Discloses a CMP apparatus provided with a clean station for cleaning the wafer with water and a brush and an unloader for holding the wafer in a submerged state.
JP-A-7-135192 "Electronic Materials" issued by the Industrial Research Council, May 1996, p53 "Electronic Materials" issued by the Industrial Research Council, May 1996, p. 62 "Electronic Materials" issued by the Industrial Research Council, May 1996, p33

  Conventionally, a metal wiring of an LSI is formed by depositing a metal film such as an aluminum (Al) alloy film or a tungsten (W) film on a silicon substrate (wafer) by a sputtering method, and then performing dry etching using a photoresist film as a mask. This metal film is formed by a method of patterning.

  However, with the recent increase in the degree of integration of LSIs, in the above-described method, the increase in wiring resistance due to the miniaturization of the wiring width has become remarkable, and this is becoming a major factor impeding the performance of high-performance logic LSIs. Therefore, recently, wiring using copper (Cu), which has an electric resistance of about half that of an Al alloy and has an electromigration resistance that is about one digit higher than that of an Al alloy, has attracted attention.

  Cu has a low vapor pressure of its halogen compound, and it is difficult to form wiring by conventional dry etching. Therefore, a groove is previously formed in an insulating film on a silicon substrate, and the insulating film including the inside of the groove is formed on the insulating film. After the Cu film is deposited on the substrate, an unnecessary Cu film outside the groove is polished back by a chemical mechanical polishing (CMP) method to leave the inside of the groove in a wiring forming process (so-called damascene process). .

  However, when the Cu film is polished by the CMP method, a part of Cu is eluted due to the action of the oxidizing agent added to the polishing slurry, and a part of the Cu wiring is corroded, which may cause an open defect or a short defect. .

  Such corrosion of the Cu wiring is caused by the Cu connected to the p-type diffusion layer of a pn junction (for example, a diffusion resistance element, a source and a drain of a MOS transistor, a collector, a base and an emitter of a bipolar transistor) formed on the silicon substrate. It occurs characteristically in wiring. Although not as remarkable as the Cu wiring, another metal material (for example, W or Al alloy) is polished by the CMP method to form the metal wiring, and the metal material ( Even when plugs are embedded, if these metal wirings and plugs are connected to the pn junction, corrosion may occur due to the above-described reasons.

  FIG. 14A is a model diagram showing a mechanism of generating an electromotive force of a pn junction, FIG. 14B is a graph showing IV characteristics of the pn junction at the time of light irradiation and at the time of darkness, and FIG. FIG. 4 is a model diagram showing a mechanism of occurrence of corrosion.

As shown in FIG. 14A, when light enters a pn junction formed on a silicon substrate, an external voltage (up to 0.6 V) of + on the p-side and-on the n-side is generated due to the photovoltaic effect of silicon. As shown in FIG. 15B, as a result of the shift of the IV characteristic of the pn junction, as shown in FIG. 15, the Cu wiring connected to the p-side (+ side) of the pn junction-pn junction-pn A short circuit current flows through a closed circuit formed by the polishing slurry attached to the n-side (-side) of the junction-polishing slurry attached to the wafer surface, and the Cu wiring connected to the p-side (+ side) of the pn junction. Cu ²⁺ ions dissociate from the surface causing electrochemical corrosion (electrolytic corrosion).

  FIG. 16 is a graph showing the relationship between the slurry concentration (%) and the etching (elution) rate of Cu when a voltage is applied. As shown in the figure, when the slurry concentration is 100%, the elution rate of Cu is relatively small, but it can be seen that the elution rate sharply increases when the polishing slurry is diluted with water to some extent.

  From the above, when light is incident on the pn junction in a state where the polishing slurry or the polishing slurry liquid diluted with water is attached to the surface of the silicon wafer, the elution of Cu becomes remarkable and electrolytic corrosion is caused. I can say. Specifically, when light is incident on the surface of the wafer during the transfer from the polishing step to the post-cleaning step or during standby, electrolytic corrosion occurs in the Cu wiring connected to the pn junction p-type diffusion layer. .

  An object of the present invention is to provide a technique capable of preventing corrosion of a metal wiring formed by using a CMP method.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

The method for manufacturing a semiconductor integrated circuit device according to the present invention comprises:
(A) forming a metal layer containing copper as a main component on a first main surface of a wafer having a first insulating film on which a groove pattern is formed;
(B) removing the metal layer on the surface of the first insulating film and outside the groove by a chemical mechanical polishing method;
(C) transferring the wafer from which the metal layer has been removed to a cleaning processing unit after having a light-shielding structure;
(D) in the post-cleaning processing section, performing post-cleaning on the first main surface of the wafer by scrubbing or brush cleaning using an alkaline or weakly alkaline chemical solution;
(E) spin drying the first main surface of the wafer that has been subjected to the post-cleaning;
And the steps (b) to (e) are performed in a single-wafer method.

  According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after a metal layer (conductive layer) is formed on a main surface of a wafer, the metal layer is planarized by chemical mechanical polishing (CMP). The so-called CMP techniques for planarizing the layer include those using standard abrasive pads and floating abrasives, fixed abrasives, and intermediates between them. Not only the embedded wiring technology but also a metal CMP for embedding a metal plug), and a step of forming a metal wiring, and a step of pre-cleaning (polishing) the main surface of the wafer subjected to the planarization processing. Cleaning for the purpose of removing undesired chemicals such as oxidizing agents from the wafer surface at the time of polishing, which is performed immediately after polishing). The main purpose of the process is to form a hydrophobic protective film on the surface of the metal in the process itself or a lower process, and it is desirable to carry out anticorrosion treatment while washing immediately. Before corrosion or before the metal is corroded by the residual oxidizing agent, etc. This anticorrosion treatment can substantially prevent the electrochemical corrosion of metal wiring. Forming a hydrophobic protective film on the surface of the metal wiring by applying a metal, a pn junction, a metal, and a metal and a polishing liquid to form a closed circuit composed of a metal and a polishing solution. A step of immersing in a liquid or holding the wafer in a wet state so as not to dry the main surface of the anticorrosion-treated wafer (that is, wet storage. Generally, wet storage is performed in pure water or the like). Immersion, supply of a shower of pure water or holding or transferring in a state of preventing its drying in a saturated steam atmosphere) and a step of post-cleaning the main surface of the wafer held in the wet state (at the time of polishing). A cleaning process for the purpose of removing undesired particles such as abrasive particles from the wafer surface, which is generally performed before the surface is dried.Generally, mechanical cleaning such as scrub cleaning with a brush or the like and chemical cleaning or the like. (Often combined with weak etching).

The summary of the invention of the present application other than the above-mentioned invention will be described below in a simple manner divided into items. That is,
1. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) a step of immersing the wafer in the liquid or holding it in a wet state so as not to dry the first main surface of the wafer subjected to the anticorrosion treatment;
(E) post-cleaning the first main surface of the wafer held in the wet state.
2. In the first aspect, the anticorrosion treatment in the step (c) includes: a step of removing polishing slurry attached to the first main surface of the wafer by the mechanical cleaning in the step (b); and a step of removing the polishing slurry. Forming a protective film on a surface portion of the metal layer on the first main surface of the wafer thus formed.
3. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the protective film is a hydrophobic protective film.
4. In the first aspect, the post-cleaning step (e) includes a step of mechanically cleaning foreign particles adhered to the first main surface of the wafer in the step (b). A method for manufacturing a semiconductor integrated circuit device.
5. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer containing copper as a main component on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) a step of immersing the wafer in the liquid or holding it in a wet state so as not to dry the first main surface of the wafer subjected to the anticorrosion treatment;
(E) post-cleaning the first main surface of the wafer held in the wet state.
6. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) a step of immersing or holding the wafer in the liquid in a light-shielded wafer storage unit so as not to dry the first main surface of the corrosion-treated wafer.
7. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the wafer holding unit is shielded from light so that the illuminance is 500 lux or less.
8. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the wafer holding unit is shielded from light so that the illuminance is 300 lux or less.
9. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) a step of drying the first main surface of the flattened wafer immediately after the flattening process.
10. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) a step of post-cleaning the first main surface of the wafer that has been subjected to the flattening process, in a post-light-shielded cleaning section.
11. In the above paragraph 10, in the post-cleaning step (c), foreign particles are removed by applying mechanical friction to the first main surface of the wafer in the presence of an alkaline or weakly alkaline chemical solution. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
12. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) a step of post-cleaning the first main surface of the wafer having been subjected to the anticorrosion treatment.
13. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of copper on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) forming a hydrophobic protective film on the flattened surface of the metal layer by subjecting the first main surface of the wafer subjected to the flattening process to an anticorrosion process.
14． A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method using single wafer processing;
(C) a step of post-cleaning the first main surface of the wafer that has been subjected to the flattening process, in a post-light-shielded cleaning section.
15. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method using single wafer processing;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) a step of post-cleaning the first main surface of the wafer having been subjected to the anticorrosion treatment.
16. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) immersion in a liquid in a wafer holding unit held at such a low temperature that an electrochemical corrosion reaction does not substantially proceed so as not to dry the first main surface of the wafer subjected to the corrosion protection treatment. Or a step of maintaining the wet state.
17. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method;
(C) forming a protective film on the surface of the metal layer that has been subjected to the flattening process by performing an anticorrosion process on the first main surface of the wafer that has been subjected to the flattening process.
18. 17. The method according to claim 17, wherein the anticorrosion treatment in the step (c) is performed under a condition that the oxidizing agent attached to the first main surface of the wafer in the step (b) does not substantially act. Of manufacturing a semiconductor integrated circuit device.
19. 18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the protective film is a hydrophobic protective film.
20. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a metal layer mainly composed of metal on a first main surface of a wafer having a pattern of a semiconductor integrated circuit;
(B) flattening the first main surface of the wafer on which the metal layer is formed by a chemical mechanical polishing method using single wafer processing;
(C) performing an anticorrosion treatment on the first main surface of the wafer that has been subjected to the planarization treatment;
(D) a step of immersing the wafer in the liquid or holding it in a wet state so as not to dry the first main surface of the wafer subjected to the anticorrosion treatment;
(E) post-cleaning the first main surface of the wafer held in the wet state.

Further, the summary of other inventions is described as follows.
21. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a plurality of semiconductor elements on a main surface of a semiconductor substrate;
(B) forming a metal layer on the plurality of semiconductor elements via an insulating film;
(C) forming a plurality of metal wirings electrically connected to the plurality of semiconductor elements by flattening the metal layer by a chemical mechanical polishing method;
(D) performing a corrosion-resistant treatment on the surface of the metal wiring;
(E) a step of immersing in a liquid or maintaining a wet state so as not to dry the surface of the metal wiring subjected to the anticorrosion treatment;
(F) a step of post-cleaning the surface of the metal wiring held in the wet state.
22. In the above paragraph 20, the corrosion prevention treatment in the step (d) includes a step of removing polishing slurry attached to a surface of the metal wiring by mechanical cleaning, and a step of protecting the surface of the metal invention from which the polishing slurry has been removed. Forming a film.
23. 23. The method according to claim 22, wherein the protective film is a hydrophobic protective film.
24. 20. In the paragraph 20, the plurality of semiconductor elements include a pn junction, a part of the plurality of metal wirings is electrically connected to one of the pn junctions, and another part of the plurality of metal wirings is A method for manufacturing a semiconductor integrated circuit device, wherein the method is electrically connected to the other of the pn junctions.
25. 21. The method for manufacturing a semiconductor integrated circuit device according to claim 20, wherein the metal wiring includes a metal plug.
26. 21. The method for manufacturing a semiconductor integrated circuit device according to claim 20, wherein the metal layer contains at least copper.
27. 21. The semiconductor integrated circuit according to claim 20, wherein the metal wiring subjected to the anticorrosion treatment is immersed or wet in the liquid in a light-shielded wafer storage unit so as not to dry the surface. Device manufacturing method.
28. 28. The method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein the wafer holding unit is shielded from light so that the illuminance is 500 lux or less.
29. 28. The method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein the wafer holding unit is shielded from light so that the illuminance is 300 lux or less.
30. 28. The method for manufacturing a semiconductor integrated circuit device according to claim 27, wherein the wafer holding unit is shielded from light so that the illuminance is 100 lux or less.
31. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a plurality of semiconductor elements on a main surface of a semiconductor substrate;
(B) forming a metal layer on the plurality of semiconductor elements via an insulating film;
(C) forming a plurality of metal wirings electrically connected to the plurality of semiconductor elements by flattening the metal layer by a chemical mechanical polishing method;
(D) a step of post-cleaning the surface of the metal wiring subjected to the planarization process in a post-light-shielding cleaning section
32. 32. The method for manufacturing a semiconductor integrated circuit device according to claim 31, wherein the metal layer contains at least copper.
33. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a plurality of semiconductor elements on a main surface of a semiconductor substrate;
(B) forming a metal layer on the plurality of semiconductor elements via an insulating film;
(C) forming a plurality of metal wirings electrically connected to the plurality of semiconductor elements by flattening the metal layer by a chemical mechanical polishing method;
(D) a step of drying the surface of the metal wiring subjected to the planarization processing immediately after the planarization processing.
34. 34. The method for manufacturing a semiconductor integrated circuit device according to claim 33, wherein the metal layer contains at least copper.

  The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

  Corrosion of metal wirings and metal plugs formed by using the CMP method can be reliably prevented, so that the reliability and manufacturing yield of a high-speed LSI using Cu wiring in particular can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary.

  Furthermore, in the following embodiments, when it is necessary for convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not irrelevant to each other, unless otherwise specified. There is a relationship of some or all of the other modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), unless otherwise specified, and unless the number is clearly limited to a specific number in principle, The number is not limited to the specific number, and may be more than or less than the specific number. Furthermore, in the embodiments described below, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified and considered to be indispensable in principle. Not even.

  Similarly, in the following embodiments, when referring to the shape of components and the like, the positional relationship, etc., the shape and the like of the components and the like are substantially excluded, unless otherwise specified and when it is considered that it is not clearly apparent in principle. And those similar to or similar to This is the same for the above numerical values and ranges.

In the present application, the following terms are interpreted as having the following meanings.
Metal CMP: Flattening the surface mainly composed of metal etc. by the chemical action of a polishing liquid and mechanical polishing on the surface side of the wafer on which a pattern is formed (in addition to damascene, dual damascene, etc., which use floating abrasive grains, Including those using fixed abrasives).
Immediately after: In the metal CMP process, before the wafer surface naturally dries after polishing, or before the metal is corroded by the remaining oxidizing agent.
Pre-cleaning: Cleaning for one purpose of removing undesired chemicals such as an oxidizing agent from the wafer surface during polishing, which is performed immediately after polishing.
Anti-corrosion treatment: A treatment for forming a hydrophobic protective film on the surface of a metal in a lower step of the pre-cleaning.
Wetting treatment: Immersion in pure water or the like, supply of a pure water shower, or holding in a saturated atmosphere with drying prevented.
Post-cleaning: Cleaning for one purpose of removing undesired particles such as abrasive grains during polishing from the wafer surface, which is generally performed before the surface is naturally dried.
Electrochemical corrosion: Corrosion of the metal due to the battery action due to the formation of a closed circuit composed of the metal constituting the pattern of the wafer, the pn junction, the metal, and the polishing liquid component.
Mechanical cleaning: Cleaning performed by rubbing the surface with a scrub brush or the like.

  Further, the term "wafer" used in the present application includes not only a single crystal silicon wafer but also a silicon epitaxial wafer and a wafer having one or more epitaxial regions formed on an insulating substrate. In addition to those made on various kinds of wafers, those made on other substrates such as TFT liquid crystal are included unless otherwise specified.

(Embodiment 1)
A method for manufacturing a MOS-LSI according to an embodiment of the present invention will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, a semiconductor substrate (wafer) 1 made of, for example, p-type single crystal silicon is prepared, and an n-type well 2n is formed on its main surface by a well-known ion implantation and selective oxidation (LOCOS) method. After the formation of the p-type well 2p and the field oxide film 3, the respective surfaces of the n-type well 2n and the p-type well 2p are thermally oxidized to form the gate oxide film 4.

  Next, as shown in FIG. 2, after a gate electrode 5 is formed on each of the gate oxide films 4 of the n-type well 2n and the p-type well 2p, an n-type impurity (for example, phosphorus) is ionized into the p-type well 2p. The source and the drain (the n-type semiconductor region 6) are formed by implanting, and the source and the drain (the p-type semiconductor region 7) are formed by implanting a p-type impurity (for example, boron) into the n-type well 2n. An n-channel MISFET (Qn) and a p-channel MISFET (Qp) are formed.

  Next, as shown in FIG. 3, after depositing a silicon oxide film 8 on the semiconductor substrate 1 by a CVD method, the silicon oxide film 8 is dry-etched using a photoresist film as a mask, thereby forming an n-channel MISFET ( A contact hole 9 is formed above the source and drain (n-type semiconductor region 6) of Qn), and a contact hole 10 is formed above the source and drain (p-type semiconductor region 7) of the p-channel MISFET (Qp). .

  Next, as shown in FIG. 4, first-layer W wirings 11 to 16 are formed on the silicon oxide film 8, and then a silicon oxide film is deposited on these W wirings 11 to 16 by the CVD method. After the first interlayer insulating film 17 is formed, through holes 18 to 21 are formed in the interlayer insulating film 17 by dry etching using a photoresist film as a mask. The first-layer W wirings 11 to 16 are formed, for example, by depositing a W film on the silicon oxide film 8 including the inside of the contact holes 9 and 10 by a CVD method (or a sputtering method) and then using the photoresist film as a mask. This W film is formed by patterning by dry etching.

  Next, as shown in FIG. 5, a plug 22 is formed inside the through holes 18 to 21, and then a silicon oxide film 23 is deposited on the interlayer insulating film 17 by a CVD method, and the photoresist film is used as a mask. The grooves 24 to 26 are formed in the silicon oxide film 23 by the dry etching. The plug 22 is formed by depositing a W film on the interlayer insulating film 17 including the inside of the through holes 18 to 21 by the CVD method, and then etching back the W film (or polishing by a CMP method described later). .

  Next, as shown in FIG. 6, a Cu film (or a Cu alloy film containing Cu as a main component) is formed on the silicon oxide film 23 including the insides of the grooves 24 to 26 by using, for example, a low-pressure long-distance sputtering method. 27) is deposited. If it is difficult to sufficiently bury the Cu film 27 therein by the sputtering method due to the large aspect ratio of the grooves 24 to 26, the semiconductor substrate 1 is heat-treated after the Cu film 27 is deposited, The film 27 may be reflowed and poured into the concave grooves 24 to 26. Alternatively, the Cu film 27 may be formed by a CVD method or an electroplating method having better step coverage than the sputtering-reflow method.

  Next, as shown in FIG. 7, the Cu film 27 is polished by a CMP method described below to flatten the surface thereof, so that the Cu wiring 28 of the second layer is formed inside the concave grooves 24 to 26. To 30 are formed.

  FIG. 8 is a schematic diagram showing a single wafer type CMP apparatus 100 used for polishing the Cu film 27. As shown in FIG. The CMP apparatus 100 includes a loader 120 for accommodating a plurality of wafers 1 each having a Cu film 27 formed on the surface, a polishing processing unit 130 for polishing and flattening the Cu film 27, and a corrosion prevention treatment for the surface of the polished wafer 1. Anti-corrosion processing unit 140, immersion processing unit 150 that keeps the surface of the wafer 1 not to be dried until post-cleaning the wafer 1 after the anti-corrosion processing, and after post-cleaning the wafer 1 after the anti-corrosion processing A cleaning processing unit 160 and an unloader 170 for accommodating a plurality of wafers 1 after the post-cleaning are provided.

  As shown in FIG. 9, the polishing processing unit 130 of the CMP apparatus 100 has a casing 101 having an open top, and a motor 103 is attached to the upper end of a rotating shaft 102 attached to the casing 101. A polishing machine (platen) 104 that is driven to rotate by the motor is attached. A polishing pad 105 formed by uniformly attaching a synthetic resin having a large number of pores is attached to the surface of the polishing plate 104.

  The polishing processing unit 130 includes a wafer carrier 106 for holding the wafer 1. The drive shaft 107 to which the wafer carrier 106 is attached is rotated integrally with the wafer carrier 106 by a motor (not shown), and is vertically moved above the polishing plate 104.

  The wafer 1 is held by the wafer carrier 106 by a vacuum suction mechanism (not shown) provided on the wafer carrier 106 with its main surface, that is, the surface to be polished facing downward. A concave portion 106a for accommodating the wafer 1 is formed at a lower end portion of the wafer carrier 106. When the wafer 1 is accommodated in the concave portion 106a, a surface to be polished is substantially the same as or slightly lower than the lower end surface of the wafer carrier 106. It will be in the state protruding to.

  A slurry supply pipe 108 for supplying a polishing slurry (S) between the surface of the polishing pad 105 and the surface to be polished of the wafer 1 is provided above the polishing plate 104, and is supplied from a lower end thereof. The polished surface of the wafer 1 is chemically and mechanically polished by the polishing slurry (S). As the polishing slurry (S), for example, a slurry mainly containing abrasive grains such as alumina and an oxidizing agent such as aqueous hydrogen peroxide or an aqueous solution of ferric nitrate, and dispersing or dissolving them in water is used.

  The polishing processing unit 130 includes a dresser 109 which is a tool for shaping (dressing) the surface of the polishing pad 105. The dresser 109 is attached to the lower end of a drive shaft 110 that moves up and down above the polishing plate 104, and is driven to rotate by a motor (not shown).

  The dressing is performed after the polishing of some wafers 1 is completed (batch processing) or every time the polishing of one wafer 1 is completed (single wafer processing). Alternatively, dressing may be performed simultaneously with polishing. For example, when the wafer 1 is pressed against the polishing pad 105 by the wafer carrier 106 and polishing is performed for a predetermined time, the wafer carrier 106 is retracted upward. Next, the dresser 109 moves downward and is pressed against the polishing pad 105, and after its surface is dressed for a predetermined time, the dresser 109 is retracted upward. Subsequently, another wafer 1 is mounted on the wafer carrier 106, and the above-described polishing step is repeated. After the wafer 1 is polished in this manner, the polishing operation is terminated by stopping the rotation of the polishing plate 104.

  The surface of the polished wafer 1 is subjected to an anticorrosion process in an anticorrosion processing unit 140. The anti-corrosion processing section 140 has a configuration similar to that of the polishing processing section 130 described above. Here, first, the main surface of the wafer 1 is pressed against a polishing pad attached to the surface of a polishing board (platen) to perform polishing. After the slurry is mechanically removed, a chemical solution containing an anticorrosive agent, such as benzotriazole (BTA), is supplied to the main surface of the wafer 1 so that the Cu wiring 28 formed on the main surface of the wafer 1 is removed. A hydrophobic protective film is formed on the surface portion of the substrate.

  The pre-cleaning, which is performed for the purpose of mechanically removing undesired chemicals from the surface of the wafer 1, such as in a polishing slurry containing an oxidizing agent, is desirably performed immediately after the polishing operation is completed. That is, the surface of the wafer 1 after the polishing operation is dried naturally, or the electrochemical corrosion reaction of the Cu wirings 28 to 30 is substantially started by the oxidizing agent in the polishing slurry remaining on the surface of the wafer 1. It is desirable to do before doing.

  The mechanical cleaning (pre-cleaning) of the polishing slurry can also be performed by rubbing the surface of the wafer 1 with pure water using a scrub brush such as a nylon brush. In addition, in the anti-corrosion treatment after the pre-cleaning, if necessary, pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning or pure water spin cleaning or the like is performed before or in parallel with the corrosion protection treatment, so that polishing is performed. The oxidizing agent in the polishing slurry adhered to the main surface of the wafer 1 is sufficiently removed by the processing unit 130, and a hydrophobic protective film is formed under the condition that the oxidizing agent does not substantially act.

  The wafer 1 that has been subjected to the anti-corrosion treatment is temporarily stored in the immersion processing unit 150 in order to prevent the surface from drying. The immersion processing unit 150 is for maintaining the surface of the wafer 1 after the corrosion-resistant treatment is not dried until the wafer 1 is subjected to post-cleaning. For example, the immersion processing unit 150 is placed in an immersion tank (stocker) in which pure water overflows. The structure is such that a predetermined number of wafers 1 are immersed and stored. At this time, the corrosion of the Cu wirings 28 to 30 is more reliably prevented by supplying pure water cooled to such a low temperature that the electrochemical corrosion reaction of the Cu wirings 28 to 30 does not substantially proceed. can do.

  The prevention of drying of the wafer 1 may be performed by a method other than the storage in the immersion tank described above, as long as at least the surface of the wafer 1 can be kept in a wet state, for example, by supplying a pure water shower. . In the case where the above-described polishing treatment and anticorrosion treatment are performed in a single-wafer method, when these treatments and a post-cleaning treatment described later proceed at the same timing, storage in the immersion tank is not always necessary, Although the processed wafer 1 may be immediately transferred to the post-cleaning processing unit 160, even in this case, in order to prevent drying of the wafer 1 being transferred, for example, a method such as immersion in pure water or supply of a pure water shower may be used. It is desirable to transfer the wafer 1 while keeping the surface of the wafer 1 wet.

  The wafer 1 transported to the post-cleaning processing unit 160 is immediately subjected to post-cleaning while the surface of the wafer 1 is kept wet. Here, the surface of the wafer 1 is scrub-cleaned (or brush-cleaned) while supplying a weak alkaline chemical such as ammonia water to neutralize the oxidizing agent, and then a hydrofluoric acid aqueous solution is supplied to the surface of the wafer 1. The foreign particles are removed by etching. Prior to or in parallel with the scrub cleaning, the surface of the wafer 1 is subjected to pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning, or pure water spin cleaning, or the back surface of the wafer 1 is subjected to pure water scrub cleaning. Or you may.

  After the post-cleaning process is completed, the wafer 1 is stored in the unloader 170 in a dry state after rinsing with pure water and spin-drying, and is conveyed to the next step in units of a plurality of wafers.

  The process after the formation of the Cu wiring will be briefly described below. First, as shown in FIG. 10, a silicon oxide film is deposited on the second Cu wirings 28 to 30 by the CVD method, and After forming an interlayer insulating film 31 and then forming through holes 32 to 34 in the interlayer insulating film 31 by dry etching using a photoresist film as a mask, a plug 35 made of a W film is embedded in the through holes 32 to 34. . Subsequently, after a silicon oxide film 36 is deposited on the interlayer insulating film 31 by the CVD method, third-layer Cu wirings 40 to 42 are formed inside the concave grooves 37 to 39 formed in the silicon oxide film 36. . The plug 35 and the third-layer Cu wirings 40 to 42 are formed in the same manner as the plug 22 and the second-layer Cu wirings 28 to 30, respectively.

  Thereafter, as shown in FIG. 11, a silicon oxide film and silicon nitride are deposited on the Cu wirings 40 to 42 by a CVD method to form a passivation film 43, thereby completing a CMOS-logic LSI.

(Embodiment 2)
FIG. 12 is a schematic diagram of a single wafer type CMP apparatus 100 used for forming Cu wiring in the present embodiment. The CMP apparatus 100 includes a loader 120 for accommodating a plurality of wafers 1 each having a Cu film formed on the surface, a polishing processing unit 130 for polishing and flattening the Cu film to form wiring, and a polishing processing unit 130 for polishing the surface of the polished wafer 1. An anti-corrosion processing section 140 for performing anti-corrosion processing, an immersion processing section 150 for keeping the surface of the wafer 1 after the anti-corrosion processing is not dried until post-cleaning, and a post-cleaning for the wafer 1 after the anti-corrosion processing is completed A post-cleaning processing unit 160 and an unloader 170 for accommodating a plurality of post-washed wafers 1 are provided. In accordance with the same procedure as in the first embodiment, polishing, corrosion protection, immersion, and post-cleaning are performed on wafers. 1 is applied.

  In addition, in the CMP apparatus 100, the immersion processing unit 150 for preventing the surface of the wafer 1 after the anti-corrosion processing is dried has a light-shielding structure so that the surface of the wafer 1 during storage is not irradiated with illumination light or the like. In addition, the occurrence of short-circuit current due to the photovoltaic effect is prevented. In order to make the immersion treatment section 150 have a light-shielding structure, specifically, the illuminance inside the immersion tank (stocker) is at least 500 lux or less, preferably by covering the periphery of the immersion tank (stocker) with a light-shielding sheet or the like. 300 lux or less, more preferably 100 lux or less.

  In addition, at the same time as the first embodiment, pure water cooled to a low temperature such that the electrochemical corrosion reaction of the Cu wiring does not substantially proceed is supplied to the immersion tank, as in the first embodiment. Thus, corrosion of the Cu wiring can be effectively prevented more effectively.

  Further, in the case where the wafer 1 having been subjected to the anti-corrosion treatment is not temporarily stored in the immersion tank but is immediately transferred to the post-cleaning processing unit 160, the transfer path on the way from the anti-corrosion processing unit 140 to the post-cleaning processing unit 160 has a light shielding structure. Alternatively, both the transport path and the post-cleaning processing unit 160 may have a light shielding structure. Further, even when the wafer 1 after the anti-corrosion processing is temporarily stored in the immersion tank, the processing units after the polishing processing unit 130, that is, the entire anti-corrosion processing unit 140, the immersion processing unit 150, and the post-cleaning processing unit 160 have a light-shielding structure. You may.

(Embodiment 3)
FIG. 13 is a schematic diagram of a single wafer type CMP apparatus 200 used for forming Cu wiring in the present embodiment. The CMP apparatus 200 includes a loader 220 for accommodating a plurality of wafers 1 each having a Cu film formed on the surface, a polishing processing unit 230 for polishing and flattening the Cu film to form wiring, and a polishing processing unit 230 for polishing the surface of the polished wafer 1. A drying processing unit 240 for drying, a post-cleaning processing unit 250 for post-washing the wafer 1, and an unloader 260 for accommodating a plurality of wafers 1 after the post-cleaning are provided.

  In the Cu wiring forming process using the CMP apparatus 200, the wafer 1 subjected to the polishing processing in the polishing processing section 230 is subjected to electrochemical corrosion by the oxidizing agent in the polishing slurry immediately after the polishing processing, that is, the polishing slurry remaining on the surface. Immediately before the reaction is started, the slurry is conveyed to the drying processing unit 240, and the moisture in the polishing slurry is removed by forced drying. Thereafter, the wafer 1 is conveyed to the post-cleaning processing section 250 while maintaining the dry state, subjected to the post-cleaning processing, and then stored in the unloader 170 through pure water rinsing and spin drying. The processing in the polishing processing section 230 and the processing in the post-cleaning processing section 250 are performed in the same procedure as in the first embodiment.

  According to the present embodiment, the surface of the wafer 1 is kept in a dry state immediately after the polishing process until the post-cleaning is started, so that the start of the electrochemical corrosion reaction is suppressed. And corrosion of the Cu wiring can be effectively prevented.

  As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.

  In the above embodiment, a process using a single-wafer type CMP apparatus has been described. However, the present invention is not limited to this. Polishing, corrosion prevention, immersion, and post-cleaning are performed in a batch manner (a plurality of wafers are collectively processed). The present invention can also be applied to a single-wafer-batch mixed process in which a part of these processes is performed in a single-wafer system, and another part is performed in a batch system.

  In the above embodiment, the case where the Cu wiring is formed by polishing the Cu film (or the Cu alloy film containing Cu as a main component) by the CMP method has been described, but the present invention is not limited to this. For example, after simultaneously embedding a metal layer such as a Cu film, a W film or an Al alloy film in a concave groove and a through hole formed in an insulating film, the metal layer is polished and flattened by a CMP method to form a wiring and a plug. Generally, a metal layer composed mainly of metal by treating the surface side of a wafer on which a pattern is formed with a chemical action of a polishing liquid and mechanical polishing, such as a so-called dual damascene process formed at the same time. Can be widely applied to a metal CMP process for polishing and flattening the surface of a metal.

  INDUSTRIAL APPLICABILITY The present invention is useful when applied to the manufacture of a semiconductor integrated circuit device in which a metal wiring is formed by using a CMP method.

FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 1 is an overall configuration diagram of a CMP apparatus used in Embodiment 1 of the present invention. FIG. 2 is a schematic diagram illustrating a polishing processing unit of the CMP apparatus used in Embodiment 1 of the present invention. FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view of a main part of the wafer, illustrating the method for manufacturing the MOS-LSI according to the first embodiment of the present invention; FIG. 6 is an overall configuration diagram of a CMP apparatus used in Embodiment 2 of the present invention. FIG. 11 is an overall configuration diagram of a CMP apparatus used in Embodiment 3 of the present invention. (A) is a model diagram showing an electromotive force generation mechanism of a pn junction, and (b) is a graph showing IV characteristics of the pn junction at the time of light irradiation and at the time of darkness. It is a model figure which shows the corrosion generation mechanism of Cu wiring. 4 is a graph showing a relationship between a slurry concentration (%) at the time of applying a voltage and an etching (elution) rate of Cu.

Explanation of reference numerals

1 semiconductor substrate (wafer)
2n n-type well 2p p-type well 3 field oxide film 4 gate oxide film 5 gate electrode 6 n-type semiconductor region (source, drain)
7 p-type semiconductor region (source, drain)
Reference Signs List 8 silicon oxide film 9, 10 contact hole 11 to 16 W wiring 17 interlayer insulating film 18 to 21 through hole 22 plug 23 silicon oxide film 24 to 26 concave groove 27 Cu film 28 to 30 Cu wiring 31 interlayer insulating film 32 to 34 through Hole 35 Plug 36 Silicon oxide films 37-39 Grooves 40-42 Cu wiring 43 Passivation film 100 CMP device 101 Housing 102 Rotating shaft 103 Motor 104 Polishing machine (platen)
105 Polishing pad 106 Wafer carrier 106a Recess 107 Drive shaft 108 Slurry supply pipe 109 Dresser 110 Drive shaft 120 Loader 130 Polishing processing unit 140 Corrosion protection processing unit 150 Immersion processing unit 160 Post-cleaning processing unit 170 Unloader 200 CMP device 220 Loader 230 Polishing processing unit 240 Drying section 250 Post-cleaning section 260 Unloader S Polishing slurry Qn N-channel MISFET
Qp p-channel type MISFET

Claims (7)

(A) forming a metal layer containing copper as a main component on a first main surface of a wafer having a first insulating film on which a groove pattern is formed;
(B) removing the metal layer on the surface of the first insulating film and outside the groove by a chemical mechanical polishing method;
(C) transferring the wafer from which the metal layer has been removed to a cleaning processing unit after having a light-shielding structure;
(D) in the post-cleaning processing section, performing post-cleaning on the first main surface of the wafer by scrubbing or brush cleaning using an alkaline or weakly alkaline chemical solution;
(E) spin drying the first main surface of the wafer that has been subjected to the post-cleaning;
And a step of performing the steps (b) to (e) in a single-wafer method.   2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said scrub or brush cleaning is brush scrub cleaning. 3. The method according to claim 1, wherein the step (a) includes the following lower step (i):
(I) forming, by electroplating, the metal layer containing copper as a main component on the first main surface of the wafer having the first insulating film on which the concave groove pattern is formed.   4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the metal layer left in the concave groove forms a part of a wiring by a dual damascene process. (A) forming a metal layer on a first main surface of a wafer having a first insulating film on which a groove pattern is formed;
(B) removing the metal layer on the surface of the first insulating film and outside the groove by a chemical mechanical polishing method;
(C) transferring the wafer from which the metal layer has been removed to a cleaning processing unit after having a light-shielding structure;
(D) in the post-cleaning processing section, performing post-cleaning on the first main surface of the wafer by scrubbing or brush cleaning using an alkaline or weakly alkaline chemical solution;
(E) spin drying the first main surface of the wafer that has been subjected to the post-cleaning;
And a step of performing the steps (b) to (e) in a single-wafer method.   6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said scrub or brush cleaning is brush scrub cleaning.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the metal layer left in the concave groove forms a part of a wiring by a dual damascene process.

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