JP2004193770A - Semiconductor integrated circuit and semiconductor memory using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit including a signal level conversion circuit for converting a signal level at a high speed with small current consumption even when a low power supply voltage is applied, and to provide a semiconductor memory employing that circuit. <P>SOLUTION: A signal level conversion circuit comprises an inverter circuit 2a with a control switch supplied with a power supply voltage VDD where a control switch 3a is provided with a PMOS transistor QP3 and a delay circuit 4, an inverter circuit 5a supplied with a power supply voltage VDDH (VDDH>VDD), and a pull-up gate 6. The signal level conversion circuit is applied to a word driver or the like of a memory, for example. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for speeding up and reducing power consumption of a semiconductor integrated circuit including a signal level conversion circuit, and particularly to a logic circuit portion to which a low power supply voltage is supplied, such as a low power supply voltage system LSI including a memory core. And a technology effective when applied to a connection portion with a memory core portion that requires supply of a relatively high power supply voltage.
[0002]
[Prior art]
According to the studies made by the present inventors, the following techniques can be considered for a signal level conversion circuit that converts a low-voltage amplitude pulse signal into a high-voltage amplitude pulse signal.
[0003]
For example, as a word driver and a driving circuit thereof, an inverter circuit which receives a signal from a decoder or the like, an N-type MOS transistor having one of its source and drain terminals connected to its output, and a word driver connected to the other. And a circuit for feeding back the output signal of the word driver and pulling up the input voltage. The voltage amplitude of the inverter circuit is VDD, and the voltage amplitude of the word driver is VDH which is higher than VDD by the threshold voltage of the cell transistor. In addition, VDD or 0 V is input to the gate of the N-type MOS transistor according to the operation (for example, see Non-Patent Document 1).
[0004]
[Non-patent document 1]
Kiyoo Ito, "Super LSI Memory", Baifukan Publishing, November 5, 1994, p. 157
[0005]
[Problems to be solved by the invention]
By the way, the inventors of the present invention have studied the technology of the signal level conversion circuit as described above, and have found the following.
[0006]
For example, an example of a signal level conversion circuit studied by the present inventors as a premise of the present invention will be described with reference to FIG.
[0007]
The signal level conversion circuit of FIG. 4 includes inverter circuits 5d and 5a, a pull-up gate 6, and a transfer gate 10. The inverter circuit 5d is supplied with VDD from the VDD power supply terminal 11, has an input terminal N8, an output terminal N9, and has a P-type MOS transistor QP1 and an N-type MOS transistor QN1. The inverter circuit 5a is supplied with VDDH satisfying VDDH> VDD from the VDDH power supply terminal 12, has an input terminal N10, an output terminal N11, and has a P-type MOS transistor QP2 and an N-type MOS transistor QN2. The pull-up gate 6 is a P-type MOS transistor. The source is connected to the VDDH power supply terminal 12, the drain is connected to the terminal N10, and the gate is connected to the terminal N11. The transfer gate 10 is an N-type MOS transistor. One of the terminals N9 and N10 is a source, the other is a drain, and the gate is connected to the VDD power supply terminal 11.
[0008]
The operation of the signal level conversion circuit will be described below.
[0009]
In the initial state, QP1 is ON, QN1 is OFF, QP2 is OFF, QN2 is ON, pull-up gate 6 is ON, transfer gate 10 is OFF, terminal N8 is 0V, terminal N9 is VDD, terminal N10 is VDDH, terminal N11. Is 0V.
[0010]
When the VDD “H” signal is input to the terminal N8 from this initial state, QP1 goes off, QN1 turns on, and the electric charge at the terminal N9 is discharged via QN1. As a result, the transfer gate 10 is turned on, and the driving capability of the pull-up gate 6 is generally designed to be low, so that the charge at the terminal N10 also starts to be discharged, and the terminals N9 and N10 approach 0V. Then, QP2 turns ON, QN2 turns OFF, and the terminal N11 approaches VDDH, which is fed back and the pull-up gate 6 turns OFF. As a result, the terminals N9 and N10 further approach 0V, QN2 is completely turned off, and the terminal N11 becomes VDDH.
[0011]
As described above, in the stable state after switching, QP1 is OFF, QN1 is ON, QP2 is ON, QN2 is OFF, pull-up gate 6 is OFF, transfer gate 10 is ON, terminal N8 is VDD, and terminals N9 and N10 are 0V, and the terminal N11 becomes VDDH.
[0012]
Next, when a 0V 'L' signal is input to the terminal N8, QP1 is turned on and QN1 is turned off, and the terminal N9 is charged to VDD via QP1. The transfer gate 10 is kept ON because the terminal N10 is initially at 0 V, so that the terminal N10 is also charged, and the voltage of the terminal N10 drops by the threshold voltage of the transfer gate 10 (VDD-Vthn). ). Then, QP2 is turned off, QN2 is turned on, and the terminal N11 approaches 0V, which is fed back and the pull-up gate 6 is turned on. For this reason, the terminal N10 is boosted to VDDH and the QP2 is completely turned off, and the transfer gate 10 is also turned off, so that a leak current from the VDDH power supply terminal 12 to the VDD power supply terminal 11 can be prevented.
[0013]
As described above, in the stable state after the switching, the transistor is in the open / closed state and the terminal voltage in the initial state.
[0014]
A semiconductor integrated circuit including the above-described signal level conversion circuit is particularly required in, for example, a system LSI or the like including many functional blocks having different voltage specifications. In recent years, in system LSIs and the like, the power supply voltage has been reduced and the operation speed has been increased. However, the memory core still needs to supply a relatively high power supply voltage to secure an operation margin. Therefore, there is a need for a semiconductor integrated circuit including a high-speed and low power consumption signal level conversion circuit in connection with a logic block operating at a low power supply voltage such as a decoder.
[0015]
Under such circumstances, for example, in the signal level conversion circuit as shown in FIG. 4, particularly at a low power supply voltage, a decrease in operating speed and an increase in current consumption are remarkable. It is directed from VDDH to VDD between a circuit operating at a low power supply voltage VDD such as the inverter circuit 5d and a circuit operating at a high power supply voltage VDDH such as the inverter circuit 5a and the pull-up gate 6. In order to prevent leakage current, the main factor is to use an N-type MOS transistor such as the transfer gate 10 described above.
[0016]
The N-type MOS transistor causes a delay when transferring the “H” signal from the inverter circuit 5d to the inverter circuit 5a because the on-resistance increases as the transfer proceeds, and also causes a voltage drop corresponding to the threshold voltage. This voltage drop degrades the voltage margin of the 'H' signal input and lowers the switching speed of the 'L' output in the inverter circuit 5a. Then, the output thereof is fed back, and the ON of the pull-up gate 6 for boosting the input terminal N10 of the inverter circuit 5a to VDDH is also delayed, so that the time required for boosting to VDDH at the terminal N10 is shown in FIG. Slow as shown. As a result, the turning off of the QP2, which is a pull-up element of the inverter circuit 5a, is delayed, causing a further decrease in the switching speed at the "L" output, and an increase in the through current of the inverter circuit 5a.
[0017]
Therefore, an object of the present invention is to provide a semiconductor integrated circuit including a signal level conversion circuit capable of performing high-speed signal level conversion with low current consumption even at a low power supply voltage, and a semiconductor memory device using the circuit. Is to do.
[0018]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0020]
That is, a semiconductor integrated circuit according to the present invention includes a first inverter circuit, a second inverter circuit, and a pull-up transistor.
[0021]
The first inverter circuit is supplied with a first power supply voltage, includes a first transistor of a first type, a second transistor of a second type, and a control switch, and is provided between a power terminal and a signal output terminal. The semiconductor device includes the first transistor and the control switch. The control switch includes means for interrupting conduction after a lapse of a predetermined time from the start of electrical conduction between the power supply terminal and the signal output terminal.
[0022]
The second inverter circuit is supplied with a power supply voltage higher than the power supply voltage of the first inverter circuit, includes a first-type third transistor, and a second-type fourth transistor. The output is the input.
[0023]
The pull-up transistor is a transistor that receives an output of the second inverter circuit as a control input, and is provided between a power supply terminal of the second inverter circuit and an input terminal of the second inverter circuit. .
[0024]
Further, the control switch of the first inverter circuit has a fifth transistor of a first type and a delay circuit. The delay circuit has a function of delaying and outputting input binary information and using the output voltage as a power supply voltage of the second inverter circuit when delaying and outputting 'H' information. is there.
[0025]
In the first inverter circuit, the first transistor, the fifth transistor, and the second transistor are connected in series from a power supply terminal.
[0026]
Further, the delay circuit is inputted from a signal output terminal of the first inverter circuit or a signal output terminal of the second inverter circuit, and outputted to a control input terminal of the fifth transistor. When the signal output terminal of the second inverter circuit is used as an input, the delay circuit has a third inverter circuit to which a power supply voltage of the second inverter circuit is supplied.
[0027]
Further, a semiconductor memory device according to the present invention includes a word line drive circuit, and the word line drive circuit includes the semiconductor integrated circuit.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0029]
(Embodiment 1)
FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to the first embodiment of the present invention. First, an example of the configuration of the semiconductor integrated circuit according to the first embodiment will be described with reference to FIG.
[0030]
In the semiconductor integrated circuit of the first embodiment, for example, VDD (first power supply voltage) is supplied from a VDD power supply terminal (first power supply terminal) 11, an input terminal (first signal input terminal) is N1, and an output terminal is An inverter with a control switch including a P-type MOS transistor (first-type first transistor) QP1, an N-type MOS transistor (second-type second transistor) QN1, and a control switch 3a, where (first signal output terminal) is N2. A circuit (first inverter circuit) 2a and a VDDH power supply terminal (second power supply terminal) 12 are supplied with VDDH (second power supply voltage) satisfying VDDH> VDD, and an input terminal (second signal input terminal) is supplied with the output. A terminal N2, an output terminal (second signal output terminal) is N3, and a P-type MOS transistor (first-type third transistor) QP2 and an N-type MOS transistor (second A fourth transistor) having an inverter circuit (second inverter circuit) 5A having a QN2 and a P-type MOS transistor provided between a VDDH power supply terminal 12 and a terminal N2, the pull-up gate having a gate connected to a terminal N3. Pull-up transistor) 6 and the like. The control switch 3a is supplied with a P-type MOS transistor (first-type fifth transistor) QP3 and VDDH from a VDDH power supply terminal 12, and has an input terminal as the output terminal N2 and an output terminal as a gate of QP3. It comprises a delay circuit 4 and the like.
[0031]
Next, an example of the operation of the semiconductor integrated circuit according to the first embodiment will be described.
[0032]
Initial states are as follows: QP1 is ON, QN1 is OFF, QP2 is OFF, QN2 is ON, pull-up gate 6 is ON, QP3 is OFF, terminal N1 is 0V, terminal N2 is VDDH, terminal N3 is 0V, gate voltage of QP3 Is VDDH.
[0033]
First, a case where a VDD 'H' signal is input to the terminal N1 from the initial state will be described. By the "H" input, QP1 is turned off and QN1 is turned on, and the electric charge of the terminal N2 is discharged via QN1. Generally, since the driving capability of the pull-up gate 6 is designed to be low, the terminal N2 approaches 0V. Then, QP2 turns ON, QN2 turns OFF, and the terminal N3 approaches VDDH. This is fed back and the pull-up gate 6 also turns OFF, and the terminal N2 further approaches 0V. When QN2 is turned off, the terminal N3 is stabilized at VDDH, the pull-up gate 6 is turned off, and the terminal N2 is stabilized at 0V.
[0034]
During the switching from the "H" output to the "L" output of the inverter circuit 2a with the control switch, the gate voltage of the QP3 holds VDDH because the "L" signal of the terminal N2 is transmitted with a delay by the delay circuit 4. However, since QP3 remains OFF, a through current caused by switching of the inverter circuit 2a with the control switch can be reduced.
[0035]
Also, when the 'L' signal is transmitted to the gate of QP3, QP3 is turned on in the process of discharging the charge of VDD stored between QP1 and QP3 to the charge of the threshold voltage of QP3, Thereafter, it is turned off.
[0036]
As described above, in the stable state after switching, QP1 is OFF, QN1 is ON, QP2 is ON, QN2 is OFF, pull-up gate 6 is OFF, QP3 is OFF, terminal N1 is VDD, terminal N2 is 0V, terminal N3 Is VDDH, and the gate voltage of QP3 is 0V.
[0037]
In comparison with the circuit of FIG. 4 examined as a premise of the present invention at the "H" signal input, an N-type MOS transistor such as the transfer gate 10 is not required, so that the inverter circuit 2a with the control switch is connected to the inverter circuit 5a. The transfer speed is improved, and the through current in switching of the inverter circuit 2a with the control switch can be reduced.
[0038]
Next, a case where a 0V 'L' signal is input to the terminal N1 will be described. QP1 is turned on and QN1 is turned off by the "L" input, and the gate voltage of QP3 is 0 V. Therefore, VDD which is the drain voltage of QP1 turns on QP3 and charges terminal N2 to VDD. During this time, the ON-resistance is small because the gate-source voltage of QP3 becomes VDD. Then, VDD of the terminal N2 is input to the inverter circuit 5a, QP2 turns OFF, QN2 turns ON, and the terminal N3 approaches 0V, so that the pull-up gate 6 turns ON. Therefore, the voltage at the terminal N2 is boosted to VDDH, the QP2 is completely turned off, and the voltage at the terminal N3 also becomes 0V.
[0039]
Here, regarding the operation of the control switch 3a, at the stage of charging the terminal N2 to VDD described above, the gate voltage of QP3 becomes VDDH after the delay time determined by the delay circuit 4, and QP3 is turned off. Then, conduction between the VDD power supply terminal 11 and the terminal N2 is cut off, and the QP3 is kept OFF even when the voltage of the terminal N2 is boosted to VDDH. Therefore, leakage current from the VDDH power supply terminal 12 to the VDD power supply terminal 11 can be prevented. However, if the delay time is too short, the charging of the terminal N2 with VDD is insufficient, the driving of the pull-up gate 6 becomes insufficient, and the terminal N2 cannot be boosted to VDDH.
[0040]
Therefore, if the delay time of the delay circuit 4 is too short, the drive of the pull-up gate 6 becomes insufficient, and if the delay time is too long, a leak current from the VDDH power supply terminal 12 to the VDD power supply terminal 11 is generated. It is necessary to design so as to be the amount of delay.
[0041]
As described above, in the stable state after switching, QP1 is ON, QN1 is OFF, QP2 is OFF, QN2 is ON, pull-up gate 6 is ON, QP3 is OFF, terminal N1 is 0V, terminal N2 is VDDH, terminal N3. Is 0V, and the gate voltage of QP3 is VDDH, which is the same as the open / closed state of each transistor and the voltage state of the terminal in the initial state.
[0042]
Compared with the circuit of FIG. 4 examined as a premise of the present invention, the delay due to the large on-resistance of the transfer gate 10 and the voltage drop corresponding to the threshold voltage do not occur at the “L” signal input. The transfer speed between the inverter circuit with control switch 2a and the inverter circuit 5a and the switching speed in the inverter circuit 5a are improved. In addition, the through current can be reduced with the improvement of the switching speed, and the voltage margin of the 'H' signal input in the inverter circuit 5a is improved by the threshold voltage of the conventional transfer gate 10.
[0043]
Therefore, according to the semiconductor integrated circuit of the first embodiment, signal level conversion can be performed at high speed with low current consumption, and the effect is exhibited particularly in inputting / outputting an “L” signal. Further, in addition to the above-described effects, the voltage margin of the input of the “H” signal in the inverter 5a is further improved, so that the inverter 5a can operate sufficiently even at a low power supply voltage.
[0044]
(Embodiment 2)
FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 2 of the present invention. First, an example of the configuration of the semiconductor integrated circuit according to the second embodiment will be described with reference to FIG.
[0045]
In the semiconductor integrated circuit of the second embodiment, for example, the delay circuit 4 of FIG. 1 in the first embodiment is replaced with an inverter circuit (third inverter circuit) 5b using VDDH as a power supply voltage, and its input terminal is connected to the inverter 5a. This is a configuration example in which the output terminal is changed to N6. The rest of the configuration is the same as that of the first embodiment, but the names of the terminals are changed for the sake of explanation, and the input terminal of the inverter circuit 2b with control switch is N4, the output terminal thereof is N5, and the input terminal of the inverter circuit 5a is N5. And The inverter circuit 5b is, for example, a CMOS inverter circuit.
[0046]
In the input terminal shown in the delay circuit 4 of FIG. 1 in the first embodiment, if the delay circuit 4 is constituted by, for example, an inverter circuit, two stages of inverter circuits are required to match the polarities. By changing the position, only one inverter circuit is required, and the circuit area and current consumption can be reduced.
[0047]
Next, an example of the operation of the semiconductor integrated circuit according to the second embodiment will be described. The operation is the same as that of the first embodiment except for the operation related to the control switch 3b, and therefore, a part thereof is omitted and will be described briefly.
[0048]
First, when the VDD “H” signal is input to the terminal N4, QN1 turns on, the terminal N5 approaches 0 V, QP2 turns on, and the terminal N6 approaches VDDH. Then, the pull-up gate 6 turns off, the terminal N5 further approaches 0 V, QN2 is completely turned off, and the terminal N6 becomes VDDH.
[0049]
When the terminal N6 approaches VDDH, the signal is fed back to the inverter circuit 5b, and after a delay time of one stage of the inverter, 0V is output to the gate of the QP3. This output turns on QP3, but turns off after discharging the charge between QP1 and QP3, as described in the first embodiment.
[0050]
Next, when a 0V 'L' signal is input to the terminal N4, QP1 is turned ON, QP3 is also turned ON by the drain voltage VDD, and the terminal N5 approaches VDD. Then, QN2 is turned on, the terminal N6 approaches 0V, and the pull-up gate 6 is turned on, so that the terminal N5 is boosted to VDDH, QP2 is completely turned off, and the terminal N6 becomes 0V.
[0051]
When the terminal N6 approaches 0V, the signal is fed back to the inverter circuit 5b, and after a delay of one stage of the inverter, VDDH is output to the gate of the QP3. Since QP3 is turned off by this VDDH, steady leakage current from the VDDH power supply terminal 12 to the VDD power supply terminal 11 can be prevented.
[0052]
However, when N6 approaches 0 V, QP3 is turned off in response to one-stage driving of the pull-up gate 6 to boost the terminal N5 to VDDH, so that the P-type MOS transistor in the inverter circuit 5b is turned off. And two stages of the P-type MOS transistor QP3. Therefore, depending on the wiring delay and the driving capability of the transistor, depending on the case, the leakage current may occur for a time shorter than the driving time of one stage of the transistor. Considering the potential difference and the leak time, it can be said that the current amount is small. The inverter circuit 5b also generates a through current at the time of switching, but has a general CMOS through current level.
[0053]
Therefore, according to the semiconductor integrated circuit of the second embodiment, a semiconductor integrated circuit having all the effects described in the first embodiment can be realized with a small area.
[0054]
(Embodiment 3)
FIG. 3 is a circuit diagram showing a semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device according to the third embodiment is an example in which, for example, the semiconductor integrated circuit according to the second embodiment is applied to the word line driving circuit.
[0055]
First, an example of the configuration of the semiconductor memory device according to the third embodiment will be described with reference to FIG.
[0056]
The semiconductor memory device 1 according to the third embodiment includes a main word driver 7, a sub word driver 8, and a memory cell 9. The main word driver 7 has transistors QP1, QP3, QN1 and an inverter circuit 5b as a delay circuit similarly to the semiconductor integrated circuit of FIG. 2 in the second embodiment, and an inverter circuit 2b with a control switch having an input terminal of N7. And an inverter circuit 5c connected to the main word line 13 as an output thereof and corresponding to the inverter circuit 5a in FIG. 2 according to the second embodiment, and a pull-up gate 6 having the output of the inverter circuit 5c as a gate input. Be composed. The sub-word driver 8 is an inverter circuit that uses VDDH as a power supply voltage and corresponds to a position connected in parallel with the inverter circuit 5a from the terminal N5 in FIG. Many memory cells 9 are connected.
[0057]
Next, an example of the operation of the semiconductor memory device 1 according to the third embodiment will be described.
[0058]
Although not explicitly shown in FIG. 3, when a selection signal is output to the main word line from a decoder or the like located in a stage preceding the terminal N7, a VDD “H” signal is input to the terminal N7, and the second embodiment is performed. Are performed, and the sub-word line 14 becomes VDDH at high speed. Then, after data writing, data reading, and the like are performed on the memory cell, a non-selection signal is output from a decoder or the like, so that a 0V “L” signal is input to the terminal N7, and the sub-word line 14 is rapidly driven to 0V. It becomes.
[0059]
Usually, since the capacity of the word line is extremely large, the rising and falling speed of the word line is a main factor which determines the operation speed of the memory. Since high-speed operation and low power consumption are required for a SRAM included in a system LSI or the like, especially for an SRAM or the like, the word driver must particularly satisfy these requirements.
[0060]
Under these circumstances, the semiconductor memory device 1 according to the third embodiment has both high speed and low power consumption as described above.
[0061]
Therefore, according to the semiconductor memory device of the third embodiment, it is possible to realize a word line drive circuit that is fast, consumes less current, and has a small area, which is optimal for a system LSI including a memory core.
[0062]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0063]
For example, in the first embodiment, a circuit to which the power supply voltage VDDH is supplied has been described as an example of the delay circuit 4. However, if the condition of the delay time can be satisfied by a resistance element or the like, it is not necessary to supply the power supply voltage. Absent.
[0064]
Further, for example, in the third embodiment, the SRAM included in the system LSI or the like has been described as an example. However, the present invention can be similarly applied to a DRAM, and is not limited to the memory in the system LSI or a single memory. Can also be applied as a high-speed buffer circuit between circuits using.
[0065]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0066]
(1) The N-type MOS transistor used for connection between the inverter circuits to which different power supply voltages are supplied is replaced with a control switch including a delay circuit, thereby improving the signal transfer speed between the inverter circuits and reducing the switching time. High-speed operation is possible, and high-speed signal level conversion can be realized.
[0067]
(2) By providing the control switch in the inverter circuit to which a low power supply voltage is supplied among the inverter circuits to which different power supply voltages are supplied, the through current of the inverter can be reduced and the high power supply voltage can be reduced. Also in the supplied inverter circuit, since the through current is reduced by shortening the switching time, low power consumption can be realized.
[0068]
(3) There is no voltage drop corresponding to the threshold voltage in the transfer of the "H" signal between the inverter circuits to which different power supply voltages are supplied, and the above (1) and (2) achieve high speed and low power consumption. Therefore, the present invention can be applied to a circuit having a low power supply voltage specification.
[0069]
(4) According to the above (1) to (3), it is possible to provide a word line driving circuit most suitable for a system LSI including a memory core.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram illustrating a configuration example of a semiconductor integrated circuit according to a second embodiment of the present invention;
FIG. 3 is a circuit diagram showing an example in which a semiconductor integrated circuit according to a second embodiment is used for a word line drive circuit in a semiconductor memory device according to a third embodiment of the present invention;
FIG. 4 is a circuit diagram showing a configuration of a signal level conversion circuit studied as a premise of the present invention.
FIG. 5 is an explanatory diagram showing a problem of an operation waveform in a signal level conversion circuit studied as a premise of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2a, 2b Inverter circuit with control switch 3a, 3b Control switch 4 Delay circuit 5a, 5b, 5c, 5d Inverter circuit 6 Pull-up gate 7 Main word driver 8 Sub word driver 9 Memory cell 10 Transfer gate 11 VDD power supply terminal 12 VDDH power supply terminal 13 main word line 14 sub-word lines QP1 to QP3 P-type MOS transistors QN1, QN2 N-type MOS transistors N1 to N11 terminals

Claims (5)

A first power supply terminal for supplying a first power supply voltage, a first signal input terminal, a first signal output terminal, a first transistor of a first type, and a second transistor of a second type; A first inverter circuit having the first transistor and the control switch between one power supply terminal and the first signal output terminal;
A second power supply terminal for supplying a second power supply voltage having a voltage higher than the first power supply voltage, a second signal input terminal, a second signal output terminal, a first transistor of a first type; A second inverter circuit comprising: a fourth transistor of a first type, wherein the first signal output terminal is connected to the second signal input terminal;
A semiconductor integrated circuit having a pull-up transistor provided between the second power supply terminal and the second signal input terminal, the pull-up transistor having a signal at the second signal output terminal as a control input;
The semiconductor integrated circuit according to claim 1, wherein the control switch has means for interrupting conduction after a lapse of a predetermined time from the start of electrical conduction between the first power supply terminal and the first signal output terminal. The semiconductor integrated circuit according to claim 1,
The control switch has a fifth transistor of a first type and a function of delaying and outputting input binary information, and a delay circuit in which an output voltage of “H” information is the second power supply voltage. Has,
The semiconductor integrated circuit according to claim 1, wherein the first inverter circuit is connected to the first transistor, the fifth transistor, and the second transistor in series from the first power supply terminal. 3. The semiconductor integrated circuit according to claim 2, wherein
The semiconductor integrated circuit, wherein the delay circuit receives the first signal output terminal as an input, and outputs a control input terminal of the fifth transistor as an output. 3. The semiconductor integrated circuit according to claim 2, wherein
The delay circuit is a third inverter circuit to which the second power supply voltage is supplied, wherein the delay circuit receives the second signal output terminal as an input, and outputs a control input terminal of the fifth transistor as an output. Integrated circuit. A semiconductor memory device including a word line drive circuit, wherein the word line drive circuit includes the semiconductor integrated circuit according to any one of claims 1 to 4.

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