JP2004179301A5 - - Google Patents
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- Publication number
- JP2004179301A5 JP2004179301A5 JP2002342200A JP2002342200A JP2004179301A5 JP 2004179301 A5 JP2004179301 A5 JP 2004179301A5 JP 2002342200 A JP2002342200 A JP 2002342200A JP 2002342200 A JP2002342200 A JP 2002342200A JP 2004179301 A5 JP2004179301 A5 JP 2004179301A5
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- JP
- Japan
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002342200A JP2004179301A (ja) | 2002-11-26 | 2002-11-26 | 半導体集積回路装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002342200A JP2004179301A (ja) | 2002-11-26 | 2002-11-26 | 半導体集積回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004179301A JP2004179301A (ja) | 2004-06-24 |
JP2004179301A5 true JP2004179301A5 (ja) | 2006-01-12 |
Family
ID=32704320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002342200A Pending JP2004179301A (ja) | 2002-11-26 | 2002-11-26 | 半導体集積回路装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2004179301A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100650846B1 (ko) * | 2004-10-06 | 2006-11-27 | 에스티마이크로일렉트로닉스 엔.브이. | 플래시 메모리 소자의 소자 분리막 형성방법 |
KR100590383B1 (ko) * | 2005-03-09 | 2006-06-19 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
KR100607351B1 (ko) * | 2005-03-10 | 2006-07-28 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조방법 |
US7691693B2 (en) * | 2007-06-01 | 2010-04-06 | Synopsys, Inc. | Method for suppressing layout sensitivity of threshold voltage in a transistor array |
KR100913331B1 (ko) | 2007-09-20 | 2009-08-20 | 주식회사 동부하이텍 | 모스 트랜지스터 및 그의 제조 방법 |
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2002
- 2002-11-26 JP JP2002342200A patent/JP2004179301A/ja active Pending