JP2004172365A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which simplifies a manufacturing process, reduces an equipment cost, improves a production efficiency, prevents semiconductor wafers from being damaged in transport or in handling, for improving the manufacturing yield. <P>SOLUTION: In a semiconductor device manufacturing method of obtaining semiconductor devices by dividing a semiconductor wafer 6 where a plurality of semiconductor elements are formed into the separate semiconductor elements, the rear surface of the semiconductor wafer 6 opposite to its circuit forming surface 6a is subjected to machining processing to thin the semiconductor wafer 6, and then a mask determining cutting lines 31b is formed by the use of a resist film 31a. A series of plasma processing of irradiating the rear surface of the semiconductor wafer 6 with plasma from above the mask to perform plasma etching on the part of the wafer 6 corresponding to the cutting lines 31b to divide the wafer 6 into separate semiconductor elements 6c, then removing the resist film 31a by plasma, and removing a micro crack layer 6b produced on the machining processed surface of the wafer 6 by plasma etching are carried out by the same plasma processing device. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor wafer on which a plurality of semiconductor elements are formed is divided into individual semiconductor elements to obtain a semiconductor device having a thickness of 100 μm or less.
[0002]
[Prior art]
Semiconductor devices mounted on electronic equipment substrates are manufactured through a packaging process in which semiconductor elements on which circuit patterns have been formed in the wafer state are connected to pins and metal bumps of lead frames and sealed with resin. Have been. With the recent miniaturization of electronic devices, miniaturization of semiconductor devices has been progressing. In particular, efforts have been actively made to make semiconductor elements thinner, and semiconductor wafers having a thickness of 100 μm or less have been used.
[0003]
Thinned semiconductor elements have low strength against external forces, and are particularly susceptible to damage during cutting, especially in a dicing step of cutting a semiconductor element in a wafer state and dividing it into individual pieces, and a reduction in processing yield cannot be avoided. There is a problem. As a method of cutting such a thinned semiconductor element, there has been proposed a method of cutting a semiconductor wafer by forming a cutting groove by plasma etching instead of a mechanical cutting method (plasma dicing). (See, for example, Patent Document 1).
[0004]
In this method, a stress is applied to remove a microcrack layer generated on a machined surface by first performing a plasma process on a machined surface of a semiconductor wafer in a state of being thinned to some extent by removing a surface opposite to a circuit forming surface by machining. Relief is performed. Thereafter, a mask is formed to cover a region of the semiconductor wafer other than the cutting line with a resist film, and then a plasma process is performed again from the mask forming surface side, so that silicon at the portion of the cutting line is removed by plasma etching. The element is divided into individual pieces. Thereafter, the mask is removed to complete the individual semiconductor device.
[0005]
[Patent Document 1]
JP-A-2002-93752
[Problems to be solved by the invention]
However, in the cutting of the semiconductor wafer described in the above-described conventional technique, since the steps of stress relief, mask formation, and plasma dicing are sequentially performed, it is necessary to use a dedicated processing apparatus for each step. That is, after the plasma processing for stress relief is completed, the semiconductor wafer must be taken out of the plasma processing apparatus, and after the mask is formed, the semiconductor wafer must be transported again into the plasma processing apparatus. As a result, the manufacturing process becomes complicated, leading to an increase in equipment cost of the manufacturing line and a decrease in production efficiency. In addition, the semiconductor device is manufactured by transporting and handling an extremely thin semiconductor wafer thinned by machining between processes. Wafer breakage and damage are likely to occur, and a reduction in processing yield is inevitable.
[0007]
Accordingly, the present invention provides a semiconductor device capable of simplifying a manufacturing process, reducing equipment cost and improving production efficiency, and improving processing yield by eliminating damage to a semiconductor wafer during transport and handling. It is an object of the present invention to provide a method for producing the same.
[0008]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer having a plurality of semiconductor elements formed on the first surface is divided into individual semiconductor elements to obtain a semiconductor device having a thickness of 100 μm or less. A method of manufacturing, comprising: a sheet attaching step of attaching a peelable protective sheet to the first surface; and machining a second surface opposite to the first surface by machining to reduce the thickness of the semiconductor wafer. A thinning step of reducing the thickness of the semiconductor wafer to 100 μm or less, a mask forming step of forming a mask on the second surface that defines a cutting line for dividing the semiconductor wafer into the individual pieces, and applying a plasma to the semiconductor wafer from the mask side. Irradiating and plasma-etching the portion of the cutting line, a plasma dicing step of dividing the semiconductor wafer into the individual pieces, and using the mask by plasma A mask removing step of removing the mask; a micro crack removing step of removing remaining micro cracks generated and remaining on the second surface in the thinning step by plasma etching the second surface from which the mask has been removed; A sheet peeling step of peeling the protective sheet from the semiconductor device obtained by dividing each of the pieces.
[0009]
According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein the plasma dicing step, the mask removing step, and the micro crack removing step are performed by the same plasma processing apparatus.
[0010]
The method for manufacturing a semiconductor device according to claim 3 is the method for manufacturing a semiconductor device according to claim 1 or 2, further comprising: attaching an adhesive sheet to the second surface after the microcrack removing step. Then, the protective sheet is peeled off.
[0011]
A method of manufacturing a semiconductor device according to claim 4 is the method of manufacturing a semiconductor device according to claim 1 or 2, wherein at least a fluorine-based gas is used as the plasma generating gas used in the plasma dicing step. Use a gas mixture.
[0012]
According to a fifth aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to the first or second aspect, wherein the plasma generating gas used in the mask removing step contains oxygen.
[0013]
The method of manufacturing a semiconductor device according to claim 6 is the method of manufacturing a semiconductor device according to claim 1 or 2, wherein the plasma generation gas used in the micro crack removing step is used in the plasma dicing step. The same kind of gas as the plasma generating gas to be used is used.
[0014]
A method for manufacturing a semiconductor device according to claim 7 is the method for manufacturing a semiconductor device according to claim 1 or 2, wherein at least a fluorine-based gas is used as the plasma generation gas used in the microcrack removing step. Use mixed gas containing.
[0015]
The method for manufacturing a semiconductor device according to claim 8 is the method for manufacturing a semiconductor device according to claim 7, wherein the plasma generation gas used in the plasma dicing step is used as the plasma generation gas used in the micro crack removal step. Use the same type of gas as the gas.
[0016]
According to the present invention, as a semiconductor wafer target on which a mask defining a cutting line for dividing a semiconductor wafer into individual semiconductor elements is formed, plasma is irradiated from the mask side to perform plasma etching on a portion of the cutting line. A plasma dicing step of dividing the semiconductor wafer into individual pieces by using a mask, a mask removing step of removing the mask using plasma, and a micro crack removing step of removing the micro cracks generated in the thinning step in the order described above. By doing so, it is possible to reduce the cost of equipment and improve production efficiency by simplifying the manufacturing process of semiconductor devices, and to reduce the damage to semiconductor wafers during transportation and handling, thereby improving the processing yield. Can be.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a side sectional view of a plasma processing apparatus according to one embodiment of the present invention, FIG. 2 is a partial cross-sectional view of a lower electrode of the plasma processing apparatus according to one embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view of a plasma processing apparatus according to an embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of a control system of the plasma processing apparatus according to an embodiment of the present invention. FIG. 6 is a flowchart illustrating a plasma processing method according to an embodiment of the present invention. FIGS. 7, 8, 9, and 10 are side sectional views of a plasma processing apparatus according to an embodiment of the present invention. FIG. 11 is a data table showing plasma processing conditions in the plasma processing according to one embodiment of the present invention.
[0018]
First, a plasma processing apparatus will be described with reference to FIGS. In this plasma processing apparatus, a semiconductor wafer in which a plurality of semiconductor elements are formed on a circuit formation surface (first surface) is divided into individual semiconductor elements to obtain a semiconductor device having a thickness of 100 μm or less. It is used in the manufacturing process.
[0019]
In the process of manufacturing this semiconductor device, first, a protective sheet made of a material that is less likely to be plasma-etched than silicon, which is the main material of the semiconductor, is attached to the circuit formation surface of the semiconductor wafer, and a back surface opposite to the circuit formation surface is attached to the protection sheet. Then, a mask for defining a cutting line for dividing the semiconductor wafer into individual semiconductor elements is formed. The plasma processing apparatus performs plasma dicing, mask removal, and micro crack removal steps on the semiconductor wafer in this state.
[0020]
In FIG. 1, the inside of a vacuum chamber 1 is a processing chamber 2 for performing plasma processing on the above-described semiconductor wafer, and a closed space for generating plasma under reduced pressure can be formed. A lower electrode 3 (first electrode) is disposed below the inside of the processing chamber 2, and an upper electrode 4 (second electrode) is disposed above the lower electrode 3 so as to face the lower electrode 3. I have. The lower electrode 3 and the upper electrode 4 each have a cylindrical shape and are arranged concentrically in the processing chamber 2.
[0021]
The lower electrode 3 is surrounded by two layers of insulators 5A and 5B mounted so as to fill the bottom of the processing chamber 2, and exposes an upper surface for holding a processing object at the center of the bottom of the processing chamber 2. It is arranged in a fixed state. The lower electrode 3 is made of a conductor such as aluminum and has a shape in which a support portion 3b extends downward from a disk-shaped electrode portion 3a. The supporting portion 3b is held in the vacuum chamber 1 via an insulating member 5C, so that the supporting portion 3b is mounted in an electrically insulated state.
[0022]
The upper electrode 4 is made of a conductor such as aluminum similarly to the lower electrode 3, and has a shape in which a support portion 4b extends upward from a disk-shaped electrode portion 4a. The support portion 4b is electrically connected to the vacuum chamber 1 and can be moved up and down by an electrode elevating mechanism 24 (FIG. 7). When the upper electrode 4 is lowered, a discharge space for generating a plasma discharge for plasma processing is formed between the upper electrode 4 and the lower electrode 3. The electrode elevating mechanism 24 functions as an inter-electrode distance changing unit, and can change the inter-electrode distance D (see FIG. 2) between the lower electrode 3 and the upper electrode 4 by raising and lowering the upper electrode 4.
[0023]
Next, the structure of the lower electrode 3 and the semiconductor wafer to be processed will be described. The upper surface of the electrode portion 3a of the lower electrode 3 is a planar holding surface (plane) on which the semiconductor wafer is mounted, and an insulating coating layer 3f is provided on the outer edge of the holding surface. The insulating coating layer 3f is formed of a ceramic such as alumina. When the lower electrode 3 is mounted in the vacuum chamber 1, the outer edge of the insulating coating layer 3f is partially insulated as shown in FIG. Covered by 5A. As a result, the outer edge of the lower electrode 3 is insulated from the plasma generated in the discharge space 2b, and occurrence of abnormal discharge is prevented.
[0024]
FIG. 2 shows a state where the semiconductor wafer 6 is placed on the lower electrode 3 before the plasma dicing is started. The semiconductor wafer 6 is a semiconductor substrate mainly composed of silicon, and a protection sheet 30 is adhered to a circuit forming surface (first surface) on the surface (the lower surface side in FIG. 2) of the semiconductor wafer 6. When the semiconductor wafer 6 is placed on the lower electrode 3, the protective sheet 30 is in close contact with the holding surface 3g on the upper surface of the electrode portion 3a.
[0025]
The protective sheet 30 includes an insulating layer formed of an insulating resin such as polyimide in a film having a thickness of about 100 μm, and is detachably adhered to the circuit forming surface of the semiconductor wafer 6 with an adhesive. . When the lower electrode 3 holds the semiconductor wafer 6 to which the protective sheet 30 is attached, as will be described later, the insulating layer causes a dielectric when the semiconductor wafer 6 is electrostatically attracted to the holding surface 3g of the electrode portion 3a. Function as
[0026]
As the material of the protective sheet 30, a material that is less likely to be etched than silicon, which is the main material of the semiconductor wafer 6, in plasma dicing described below is selected. Thereby, even when the etching rate distribution by the plasma is not uniform in the process of plasma dicing, and the etching rate of the semiconductor wafer partially varies, the protective sheet 30 functions as an etching stop layer. ing.
[0027]
On the back surface (second surface) on the opposite side (upper side in FIG. 2) of the circuit formation surface, a mask for defining a cutting line in plasma dicing to be described later is formed. This mask is formed by grinding the back surface by machining as described later and then patterning it with a resist film, so that the region excluding the cutting line 31b to be subjected to plasma etching is covered with the resist film 31a. .
[0028]
As shown in FIG. 2, the lower electrode 3 is provided with a plurality of suction holes 3 e opened in the holding surface 3 g, and the suction holes 3 e communicate with suction holes 3 c provided inside the lower electrode 3. Suction hole 3c, as shown in FIG. 1, is connected to the vacuum suction pump 12 via a gas line switchover valve 11, the gas line switchover valve 11 is connected to the N ₂ gas supply unit 13 for supplying Chissogasu . By switching the gas line switchover valve 11, it is possible to selectively connect the suction hole 3c to the vacuum suction pump 12, N ₂ gas supply unit 13.
[0029]
By driving the vacuum suction pump 12 while the suction hole 3c is in communication with the vacuum suction pump 12, the semiconductor wafer 6 placed on the lower electrode 3 by vacuum suction from the suction hole 3e is held by vacuum suction. Therefore, the suction hole 3e, the suction hole 3c, and the vacuum suction pump 12 suck the vacuum from the suction hole 3e opened in the holding surface 3g of the lower electrode 3, thereby bringing the protective sheet 30 into close contact with the holding surface 3g of the electrode portion 3a. Thus, it is a suction holding means for holding the semiconductor wafer 6 by vacuum suction.
[0030]
By connecting the suction hole 3c to the N ₂ gas supply unit 13, nitrogen gas can be ejected from the suction hole 3e to the lower surface of the protective sheet 30. As will be described later, this nitrogen gas is a blowing gas for the purpose of forcibly separating the protective sheet 30 from the holding surface 3g.
[0031]
The lower electrode 3 is provided with a coolant channel 3 d for cooling, and the coolant channel 3 d is connected to the cooling mechanism 10. By driving the cooling mechanism 10, a coolant such as cooling water circulates in the coolant channel 3d, thereby cooling the lower electrode 3 and the protective sheet 30 on the lower electrode 3 which have been heated by the heat generated during the plasma processing. Is done. The coolant passage 3 d and the cooling mechanism 10 serve as cooling means for cooling the lower electrode 3.
[0032]
A vacuum pump 8 is connected to an exhaust port 1 a provided in communication with the processing chamber 2 via an exhaust switching valve 7. By switching the exhaust switching valve 7 to the exhaust side and driving the vacuum pump 8, the inside of the processing chamber 2 of the vacuum chamber 1 is evacuated, and the inside of the processing space 2 is depressurized. The processing chamber 2 includes a pressure sensor 28 (not shown in FIG. 1; see FIG. 5), and a control unit 33 (FIG. 5) described later controls the vacuum pump 8 based on the pressure measurement result of the pressure sensor 28. By doing so, the pressure inside the processing chamber 2 can be reduced to a desired pressure. The vacuum pump 8 is a pressure reducing unit that reduces the pressure inside the processing chamber 2 to a desired pressure. By switching the exhaust switching valve 7 to the atmosphere open side, the atmosphere is introduced into the processing space 2 and the pressure inside the processing chamber 2 returns to the atmospheric pressure.
[0033]
Next, a detailed structure of the upper electrode 4 will be described. The upper electrode 4 has a configuration in which a central electrode portion 4a and a projecting portion 4f made of an insulator and provided on the outer peripheral portion so as to project around the electrode portion 4a. The outer shape of the overhang portion 4f is larger than that of the lower electrode 3, and is arranged so as to extend outward from the lower electrode 3. A gas outlet 4e is provided at the center of the lower surface of the upper electrode 4.
[0034]
The gas blowing unit 4e supplies a plasma generating gas for generating a plasma discharge in a discharge space between the upper electrode 4 and the lower electrode 3. The gas blowing portion 4e is a member formed by processing a porous material having a large number of fine holes therein into a circular plate shape, and the gas for plasma generation supplied into the gas retaining space 4g passes through these fine holes. And blow it out uniformly into the discharge space to supply it in a uniform state.
[0035]
A gas supply hole 4c communicating with the gas retaining space 4g is provided in the support portion 4b, and the gas supply hole 4c is connected to the first gas supply gas for plasma generation via the gas flow rate adjusting portion 19 and the gas switching valve 20. The section 21 is connected to the second plasma generating gas supply section 22 and the third plasma generating gas supply section 23. The first plasma generation gas supply unit 21 and the third plasma gas supply unit 23 are provided with a fluorine-based gas such as sulfur hexafluoride (SF ₆ ) or a mixed gas of carbon tetrafluoride (CF ₄ ) and helium gas. Supply the mixed gas containing. The second plasma generation gas supply unit 22 supplies a gas containing oxygen gas (O ₂ ).
[0036]
By switching the gas switching valve 20, the plasma generation gas is supplied from any of the first plasma generation gas supply unit 21, the second plasma generation gas supply unit 22, and the third plasma generation gas supply unit 23. Can be supplied from the gas blowing portion 4e into the discharge space. Therefore, the first plasma generating gas supply unit 21, the second plasma generating gas supply unit 22, the third plasma generating gas supply unit 23, and the gas switching valve 20 are provided in the processing chamber 2 with a plurality of types of plasma. It serves as a plasma generation gas supply means for selectively supplying a generation gas.
[0037]
In the supply of the plasma generation gas described above, the gas flow rate supplied to the discharge space can be arbitrarily adjusted by controlling the gas flow rate adjustment unit 19 according to a command from the control unit 33. As a result, the pressure in the processing chamber 2 in the plasma generating gas supply state is controlled based on the preset plasma processing conditions and the pressure in the processing chamber 2 detected by the pressure sensor 28. Therefore, the gas flow rate adjusting unit 19 serves as a pressure control unit that controls the pressure in the processing chamber 2.
[0038]
The pressure control means for controlling the pressure in the processing chamber 2 includes a well-known technique other than the above-described method for adjusting the flow rate of the gas supplied into the processing chamber 2, for example, exhaust of gas discharged from the vacuum chamber 2 to the outside. A method for controlling the amount may be used. As this method, a variable displacement type pump may be used as the vacuum pump 8, and the exhaust capacity of the vacuum pump 8 may be controlled by the control unit 33, and the degree of opening of the exhaust hole 1a can be freely adjusted. An opening adjustment valve may be provided, and the opening adjustment valve may be controlled by the control unit 33.
[0039]
The lower electrode 3 is electrically connected to a high-frequency power supply 17 via a matching circuit 16. By driving the high-frequency power supply unit 17, a high-frequency voltage is applied between the upper electrode 4 and the lower electrode 3 that are electrically connected to the vacuum chamber 1 grounded to the ground unit 9. As a result, a plasma discharge is generated in the discharge space between the upper electrode 4 and the lower electrode 3 inside the processing chamber 2, and the plasma generating gas supplied into the processing chamber 2 shifts to a plasma state. The matching circuit 16 matches the impedance of the plasma discharge circuit in the processing chamber 2 with the impedance of the high-frequency power supply unit 17 when the plasma is generated.
[0040]
The lower electrode 3 is connected to a DC power supply 18 for electrostatic attraction via an RF filter 15. By driving the DC power supply unit 18 for electrostatic attraction, negative charges are accumulated on the surface of the lower electrode 3 as shown in FIG. In this state, when the high-frequency power supply unit 17 is driven to generate plasma in the processing chamber 2 as shown in FIG. 3B (see the dotted portion 31 in the figure), the protective sheet 30 is placed on the holding surface 3g. A DC application circuit 32 that connects the semiconductor wafer 6 and the grounding unit 9 mounted thereon via the plasma is formed via the plasma in the processing chamber 2. As a result, a closed circuit is formed that sequentially connects the lower electrode 3, the RF filter 15, the DC power supply unit 18 for electrostatic attraction, the grounding unit 9, the plasma, and the semiconductor wafer 6, and the semiconductor wafer 6 stores positive charges. .
[0041]
Then, between the negative charges accumulated on the holding surface 3 g of the lower electrode 3 made of a conductor and the positive charges accumulated on the semiconductor wafer 6, Coulomb is provided via a protective sheet 30 including an insulating layer as a dielectric. A force acts, and the semiconductor wafer 6 is held on the lower electrode 3 by this Coulomb force. At this time, the RF filter 15 prevents the high-frequency voltage of the high-frequency power supply 17 from being directly applied to the DC power supply 18 for electrostatic attraction. The polarity of the DC power supply 18 for electrostatic attraction may be reversed.
[0042]
In the configuration described above, the DC power supply unit 18 for electrostatic attraction acts between the semiconductor wafer 6 separated by the protective sheet 30 and the holding surface 3 g of the lower electrode 3 by applying a DC voltage to the lower electrode 3. A DC voltage applying means for electrostatically adsorbing the semiconductor wafer 6 using Coulomb force. That is, the holding means for holding the semiconductor wafer 6 on the lower electrode 3 is composed of a vacuum suction means for vacuum-sucking the protective sheet 30 through a plurality of suction holes 3e opened on the holding surface 3g, and a DC voltage applying means described above. Two types can be used properly.
[0043]
The upper electrode 4 is provided with a coolant passage 4 d for cooling, and the coolant passage 4 d is connected to the cooling mechanism 10. By driving the cooling mechanism 10, a coolant such as cooling water circulates in the coolant channel 4d, thereby cooling the upper electrode 4 which has been heated by the heat generated during the plasma processing.
[0044]
On the side of the processing chamber 2, an opening 1b for taking in and out the processing object is provided (see FIG. 7). A door 25 which is moved up and down by a door opening / closing mechanism 26 is provided outside the opening 1b, and the opening 1b is opened and closed by moving the door 25 up and down. FIG. 7 shows a state where the semiconductor wafer 6 is taken in and out with the door 25 being lowered to open the opening 1b.
[0045]
When the semiconductor wafer 6 is taken in and out, the upper electrode 4 is raised by the electrode lifting mechanism 24 to secure a space for transport on the lower electrode 3. In this state, the suction head 27 holding the semiconductor wafer 6 by suction is moved into the processing chamber 2 through the opening 1b by operating the arm 27a. As a result, loading of the semiconductor wafer 6 onto the lower electrode 3 and unloading of the processed semiconductor wafer 6 (semiconductor device) are performed.
[0046]
Next, a configuration of a control system of the plasma processing apparatus will be described with reference to FIG. 4, a storage unit 34 for storing various data and processing programs is connected to the control unit 33, and the storage unit 34 stores plasma processing conditions 34a and operation programs 34b for plasma processing. The operation / input unit 35 is an input unit such as a keyboard, and inputs data such as plasma processing conditions and the like and operation commands. The display unit 36 is a display device, and displays a guidance screen or the like at the time of operation input.
[0047]
Here, the plasma processing conditions 34a will be described with reference to the data table of FIG. The plasma processing conditions 34a include a first condition, a second condition, and a second condition corresponding to the respective processes of a plasma dicing process, an ashing process for removing a mask, and a plasma stress relief process for removing microcracks, as described later. 3 conditions are included. As shown in FIG. 11, the plasma processing conditions include RF power [W] indicating high-frequency power supply output, pressure [Pa], and interelectrode distance [mm]. Optimal condition data is stored in the storage unit 34.
[0048]
The acceptable ranges of the condition data in the plasma dicing are as follows: RF power is 500 to 3000 [W], processing pressure is 5 to 300 [Pa], and distance between electrodes is 5 to 50 [mm]. The numerical value considered to be optimal is stored in the storage unit 34 as the first condition.
[0049]
Further, the allowable range of the condition data in the ashing is that the RF power is 100 to 1000 [W], the processing pressure is 5 to 100 [Pa], and the distance between the electrodes is 50 to 100 [mm]. The numerical value considered to be optimal is stored in the storage unit 34 as the second condition.
[0050]
The allowable ranges of the condition data in the plasma stress relief are as follows: RF power is 500 to 3000 [W], processing pressure is 300 to 2000 [Pa], and distance between electrodes is 5 to 20 [mm]. The numerical value considered to be the best among them is stored in the storage unit 34 as the third condition.
[0051]
When the RF power is not changed in the plasma dicing step, the ashing step, and the plasma stress relief step, it is not necessary to individually set the RF power conditions as the first to third conditions.
[0052]
In the plasma processing operation executed based on the operation program 34b, the control unit 33 controls the gas switching valve 20, the gas flow rate adjusting unit 19, the gas line switching valve 11, the high frequency power supply unit 17, and the DC power supply unit 18 for electrostatic attraction. , Exhaust switching valve 7, vacuum pump 8. Each part of the vacuum suction pump 12, the door opening / closing mechanism 26, and the electrode lifting / lowering mechanism 24 is controlled.
[0053]
At this time, the pressure is set by the control unit 33 controlling the gas flow rate adjusting unit 19 based on the pressure detection result of the pressure sensor 28 and the above-described plasma processing condition 34a. Similarly, the control unit 33 controls the high-frequency power supply unit 17 and the electrode lifting / lowering mechanism 24, so that the distance D between the electrodes and the output of the high-frequency power supply are set to the plasma processing conditions.
[0054]
This plasma processing apparatus is configured as described above. Hereinafter, a method of manufacturing a semiconductor device performed by using the plasma processing apparatus and a plasma processing method performed in the process of manufacturing the semiconductor device will be described with reference to FIG. This will be described along with reference to the drawings.
[0055]
First, in FIG. 5A, reference numeral 6 denotes a semiconductor wafer on which a plurality of semiconductor elements have been formed before the thinning process, and in this state, the thickness exceeds 100 μm. Prior to the thinning process, a protective sheet 30 that can be peeled off with an adhesive is attached to the circuit forming surface (first surface) 6a of the semiconductor wafer 6 (sheet attaching step). At this time, the protective sheet 30 is shaped so as to have the same shape as the outer shape of the semiconductor wafer 6 so as to cover the entire surface of the circuit forming surface 6 a and not to protrude outside the semiconductor wafer 6. This prevents the protection sheet 30 from being exposed to the plasma during the subsequent plasma processing, thereby preventing the protection sheet 30 from being damaged by the plasma.
[0056]
Next, as shown in FIG. 5B, the back surface (the second surface) on the opposite side of the circuit formation surface is cut off by machining to reduce the thickness t of the semiconductor wafer to 100 μm or less (thinning step). In this thinning step, a micro crack layer 6b is generated on the machined surface on the back surface. The microcrack layer 6b is removed in a later step in order to lower the bending strength of the semiconductor wafer 6.
[0057]
Next, a mask for defining a cutting line for dividing the semiconductor wafer 6 into individual semiconductor elements is formed on the back surface after the thinning step (mask forming step). First, as shown in FIG. 5C, a resist film 31 made of resin is formed on the back surface so as to cover the entire surface of the semiconductor wafer 6. Next, as shown in FIG. 5D, the resist film 31 is patterned by photolithography to remove only a portion corresponding to the cutting line 31b. As a result, a mask is formed on the back surface of the semiconductor wafer 6 in which the area other than the cutting line 31b is covered with the resist film 31a, and the semiconductor wafer 6 with the mask in this state is subjected to plasma processing.
[0058]
Hereinafter, the plasma processing method for the semiconductor wafer 6 with the mask will be described with reference to the drawings according to the flow of FIG. First, as shown in FIG. 7, a semiconductor wafer 6 with a mask is carried into the processing chamber 2 (ST1). At the time of this loading operation, the arm 27a is operated while the upper electrode 4 is raised by the electrode lifting mechanism 24, and the semiconductor wafer 6 held on the mask forming surface side by the suction head 27 is moved from the opening 1b to the processing chamber. 2, and the semiconductor wafer 6 is placed on the lower electrode 3.
[0059]
Next, the vacuum suction pump 12 is driven to suck the vacuum through the suction holes 3e, thereby turning on the vacuum suction of the semiconductor wafer 6 and turning on the DC power supply 18 for electrostatic suction (ST2). By this vacuum suction, the semiconductor wafer 6 is held by the lower electrode 3 in a state where the protective sheet 30 is in close contact with the holding surface 3g of the lower electrode 3 in the processing chamber 2 (wafer holding step).
[0060]
Thereafter, as shown in FIG. 8, the door 25 is closed, and the upper electrode 4 is lowered (ST3). Thereby, the inter-electrode distance between the upper electrode 4 and the lower electrode 3 is set to the inter-electrode distance D1 shown in the first plasma processing condition. Next, the vacuum pump 8 is operated to start reducing the pressure in the processing chamber 2 (ST4). When the inside of the processing chamber 2 reaches a predetermined degree of vacuum, the first plasma generation gas supply unit 21 supplies a plasma dicing gas (a first plasma generation gas) composed of a mixed gas of sulfur hexafluoride and helium. Is supplied (ST5).
[0061]
Then, in the gas supply process, the gas pressure in the processing chamber 2 is detected and compared with the plasma processing conditions to confirm that the pressure has reached the pressure shown in the first condition (ST6). That is, in (ST3) and (ST6), the interelectrode distance D between the lower electrode 3 and the upper electrode 4 opposed to the lower electrode 3 and the pressure in the processing chamber 2 are determined by the plasma processing conditions. The first condition is set (first condition setting step).
[0062]
When the setting of the conditions is completed, the high-frequency power supply unit 18 is driven to apply a high-frequency voltage between the upper electrode 4 and the lower electrode 3 to start plasma discharge (ST7). Thereby, in the discharge space between the upper electrode 4 and the lower electrode 3, the first plasma generating gas containing the fluorine-based gas is changed to the plasma state. Due to this plasma generation, the semiconductor wafer 6 is irradiated with plasma of a fluorine-based gas such as sulfur hexafluoride from the mask side (the resist film 31a side). By this plasma irradiation, only the portion of the cutting line 31b that is not covered with the resist film 31a among the silicon that is the main material of the semiconductor wafer 6 is plasma-etched by the plasma of the fluorine-based gas.
[0063]
At the same time, a DC application circuit is formed in the discharge space between the upper electrode 4 and the lower electrode 3 by the plasma (see FIG. 3). As a result, an electrostatic attraction force is generated between the lower electrode 3 and the semiconductor wafer 6, and the semiconductor wafer 6 is held by the lower electrode 3 by the electrostatic attraction force. Therefore, the protection sheet 30 is in good contact with the holding surface 3g of the lower electrode 3, the semiconductor wafer 6 is stably held in the plasma processing process, and the protection function of the lower electrode 3 makes the protection sheet 30 good. To prevent thermal damage due to heat generated by the plasma discharge.
[0064]
As the plasma etching progresses, as shown in FIG. 5E, a cutting groove 6d is formed only in the portion of the cutting line 31b in the semiconductor wafer 6, and the depth of the cutting groove 6d is When the semiconductor wafer 6 reaches the entire thickness, the semiconductor wafer 6 is divided into individual semiconductor elements 6c as shown in FIG. 5E (plasma dicing step). The power of the high frequency power supply in this plasma dicing step is a first condition set in a range of 500 to 3000 [W]. When the predetermined plasma processing time has elapsed and the plasma dicing is completed, the plasma discharge is stopped (ST8).
[0065]
Thereafter, the inter-electrode distance is changed to shift to the plasma ashing step (ST9). That is, as shown in FIG. 9, the upper electrode 4 is raised, and the distance between the electrodes between the upper electrode 4 and the lower electrode 3 is set to the distance D2 between the electrodes shown in the second plasma processing condition. The inter-electrode distance D2 when removing the mask is set to be wider than the inter-electrode distance D1 in the above-described plasma dicing and the inter-electrode distance D3 when removing microcracks described below.
[0066]
Next, a plasma ashing gas (second plasma generation gas) is supplied from the second plasma generation gas supply unit 22 (ST10). Then, in the gas supply process, the gas pressure in the processing chamber 2 is detected and compared with the plasma processing conditions to confirm that the pressure has reached the pressure shown in the second condition (ST11). That is, in (ST9) and (ST11), the distance between the electrodes and the pressure in the processing chamber 2 are set to the second condition of the plasma processing conditions (second condition setting step).
[0067]
When the setting of the conditions is completed, the high-frequency power supply unit 18 is driven to apply a high-frequency voltage between the upper electrode 4 and the lower electrode 3 to start plasma discharge (ST12). Thereby, in the discharge space between the upper electrode 4 and the lower electrode 3, the second plasma generating gas including the oxygen gas is shifted to the plasma state. The plasma generated in this manner acts on the mask forming surface side (second surface side) of the semiconductor wafer 6, so that the resist film 31a made of an organic substance is ashed (ashed) by the oxygen gas plasma.
[0068]
As the ashing proceeds, the resist film 31a gradually disappears, and finally the mask is completely removed from the second surface side of the semiconductor wafer 6 as shown in FIG. ). The power of the high-frequency power supply in the mask removing step is a second condition set in the range of 100 to 1000 [W]. After the mask is completely removed, the plasma discharge is stopped (ST13).
[0069]
Thereafter, the distance between the electrodes is changed to shift to the microcrack removing step (ST14). That is, as shown in FIG. 10, the upper electrode 4 is lowered again, and the inter-electrode distance between the upper electrode 4 and the lower electrode 3 is set to the inter-electrode distance D3 shown in the third plasma processing condition. .
[0070]
Next, a plasma etching gas (third plasma generation gas) for removing microcracks is supplied from the third plasma generation gas supply unit 23 (ST15). Here, the same type of gas as the plasma generation gas (first plasma generation gas) used in the plasma dicing step, that is, a mixed gas of sulfur hexafluoride and helium, which is a fluorine-based gas, is also used in the micro crack removal step. I am trying to use it as well. When a gas of the same type as the first plasma generation gas is always used as the third plasma generation gas, the first plasma generation gas supply unit 23 is not provided and the first plasma generation gas is not provided. The gas supply unit 21 may be shared.
[0071]
Then, in the gas supply process, the gas pressure in the processing chamber 2 is detected and compared with the plasma processing conditions to confirm that the pressure has reached the pressure shown in the first condition (ST16). That is, in (ST14) and (ST16), the distance between the electrodes and the pressure in the processing chamber 2 are set to the third condition of the plasma processing condition (third condition setting step).
[0072]
When the setting of the conditions is completed, the high-frequency power supply 18 is driven to apply a high-frequency voltage between the upper electrode 4 and the lower electrode 3 to start the plasma discharge (ST17).
[0073]
Thereby, in the discharge space between the upper electrode 4 and the lower electrode 3, the third plasma-generating gas containing the fluorine-based gas is changed to the plasma state.
[0074]
By causing the plasma generated in this manner to act on the semiconductor wafer 6, as shown in FIG. 5 (g), the surface (second surface) on the mask-removed side of the semiconductor element 6c divided into individual pieces is formed. The remaining micro crack layer 6b is removed by plasma etching (micro crack removing step). The power of the high-frequency power supply in the micro-crack removing step is a third condition set in the range of 50 to 3000 [W]. Then, when a predetermined plasma processing time has elapsed, the plasma discharge is stopped (ST18).
[0075]
Thereafter, the operation of the vacuum pump 8 is stopped (ST19), and the exhaust switching valve 7 is switched to open to the atmosphere (ST20). Thereby, the pressure in the processing chamber 2 returns to the atmospheric pressure. Then, the vacuum suction is turned off, and the DC power supply for electrostatic suction is turned off (ST21). As a result, the suction holding of the semiconductor wafer 6 in the state of being divided into individual pieces of the semiconductor element 6c and being held by the protective tape 30 is released.
[0076]
After that, the semiconductor wafer 6 after the plasma processing is carried out (ST22). That is, the semiconductor wafer 6 is sucked and held by the suction head 27 and is carried out of the processing chamber 2 while blowing nitrogen gas through the suction hole 3e. Thus, the plasma processing in which the respective steps of plasma dicing, ashing, and plasma etching are continuously performed by the same plasma processing apparatus is completed.
[0077]
In this series of plasma processing, the protection sheet 30 is entirely covered with the semiconductor wafer 6 as described above, and does not suffer damage such as thermal deformation due to exposure to plasma. Therefore, the protection sheet 30 is always in good contact with the holding surface 3g and the semiconductor wafer 6, and can function well as a protection sheet.
[0078]
Then, the semiconductor wafer 6 carried out together with the protective sheet 30 is sent to a sheet peeling step, and the protective sheet 30 is peeled from the circuit forming surface of the semiconductor device obtained by dividing the semiconductor element 6c into individual pieces ( Sheet peeling step). As shown in FIG. 5 (h), the sheet peeling is performed after the holding adhesive sheet 37 is attached to the second surface of the semiconductor element 6c and each semiconductor element 6c is held on the adhesive sheet 37.
[0079]
As described above, in the method for manufacturing a semiconductor device according to the present embodiment, a cutting line for dividing a semiconductor wafer into individual pieces first is formed on the semiconductor wafer after machining and thinning the semiconductor wafer. Is formed. Then, three plasma processing processes having different purposes are performed on the semiconductor wafer on which the mask is formed.
[0080]
That is, a plasma dicing step of irradiating plasma from the mask side and plasma-etching a portion of the cutting line to divide the semiconductor wafer into individual semiconductor elements, and a mask removing step of removing the mask using plasma, The micro-crack removing step of removing the micro-cracks generated in the thinning step is continuously performed by the same plasma processing apparatus in the order described above.
[0081]
A plasma processing apparatus for performing the above-described series of plasma processing; a pressure control means for controlling a pressure in the processing chamber; and a plasma generating gas supply means for selectively supplying a plurality of types of plasma generating gases into the processing chamber. And inter-electrode distance changing means for changing the inter-electrode distance between the lower electrode and the upper electrode.
[0082]
This makes it possible to switch the plasma processing conditions according to the processing purpose in the same apparatus, to perform a plasma dicing step of dividing the semiconductor wafer into individual semiconductor elements by plasma etching, and to remove the mask using plasma. The mask removing step and the microcrack removing step of removing the microcracks generated in the thinning step can be continuously and efficiently performed by the same plasma processing apparatus.
[0083]
Therefore, as described in the related art, various problems in the form of sequentially performing the steps of stress relief, mask formation, and plasma dicing can be effectively solved.
[0084]
In other words, after the plasma processing for stress relief is completed, the semiconductor wafer is taken out of the plasma processing apparatus, and after the mask is formed, the semiconductor wafer is loaded again into the plasma processing apparatus, which complicates the manufacturing process and the equipment cost of the manufacturing line. A semiconductor device can be manufactured without causing an increase or a decrease in production efficiency. Furthermore, it is possible to minimize the damage and damage of the semiconductor wafer by transporting and handling the extremely thin semiconductor wafer after being thinned by machining between each process, thereby improving the processing yield. Has become.
[0085]
Note that, in this embodiment, an example in which the plasma dicing step is performed by using plasma of one kind of mixed gas including a fluorine-based gas is described. May go. For example, the etching of the SiO ₂ layer of the semiconductor wafer is performed by plasma of a fluorine-based gas having a hydrogen bond, and the etching of the protective film (passivation film) is performed by the plasma of oxygen gas. Configurations and processes may be changed.
[0086]
【The invention's effect】
According to the present invention, as a semiconductor wafer target on which a mask for defining a cutting line that divides a semiconductor wafer into individual semiconductor elements is formed, a portion of the cutting line is plasma-etched by irradiating plasma from the mask side. A plasma dicing step of dividing the semiconductor wafer into individual pieces by using a mask, a mask removing step of removing the mask using plasma, and a micro crack removing step of removing the micro cracks generated in the thinning step in the order described above. By doing so, it is possible to reduce the cost of equipment and improve production efficiency by simplifying the manufacturing process of semiconductor devices, and to reduce the damage to semiconductor wafers during transportation and handling, thereby improving the processing yield. Can be.
[Brief description of the drawings]
FIG. 1 is a side sectional view of a plasma processing apparatus according to an embodiment of the present invention; FIG. 2 is a partial cross-sectional view of a lower electrode of the plasma processing apparatus according to an embodiment of the present invention; FIG. 4 is a cross-sectional view of a plasma processing apparatus according to an embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of a control system of the plasma processing apparatus according to an embodiment of the present invention. FIG. 6 is a flowchart of a plasma processing method according to an embodiment of the present invention. FIG. 7 is a side sectional view of a plasma processing apparatus according to an embodiment of the present invention. FIG. 8 is an embodiment of the present invention. FIG. 9 is a sectional side view of a plasma processing apparatus according to an embodiment of the present invention. FIG. 10 is a sectional side view of a plasma processing apparatus according to an embodiment of the present invention. 11. Plasma processing conditions in plasma processing according to one embodiment of the present invention Figure [EXPLANATION OF SYMBOLS] indicating the data table shown
DESCRIPTION OF SYMBOLS 1 Vacuum chamber 2 Processing chamber 3 Lower electrode 3g Holding surface 4 Upper electrode 6 Semiconductor wafer 6a Circuit formation surface 6c Semiconductor element 8 Vacuum pump 12 Vacuum suction pump 17 High frequency power supply part 18 DC power supply part for electrostatic adsorption 21 First plasma generation Gas supply unit 22 Second gas supply unit for plasma generation 23 Third gas supply unit for plasma generation 30 Protective sheet 31, 31a Resist film 31b Cutting line 37 Adhesive sheet

Claims (8)

A method of manufacturing a semiconductor device in which a semiconductor wafer having a plurality of semiconductor elements formed on a first surface is divided into individual semiconductor elements to obtain a semiconductor device having a thickness of 100 μm or less, A sheet attaching step of attaching a peelable protective sheet, a thinning step of shaving off a second surface opposite to the first surface by machining to reduce the thickness of the semiconductor wafer to 100 μm or less; Forming a mask defining a cutting line for dividing the semiconductor wafer into the individual pieces on the surface of the semiconductor wafer, and irradiating the semiconductor wafer with plasma from the mask side to perform plasma etching on the portion of the cutting line Thereby, a plasma dicing step of dividing the semiconductor wafer into the individual pieces, a mask removing step of removing the mask using plasma, A micro-crack removing step of removing the micro-cracks generated on the second surface in the thinning step by plasma etching the removed second surface; and a semiconductor device obtained by dividing each of the individual pieces. And a sheet peeling step of peeling the protective sheet. 2. The method according to claim 1, wherein the plasma dicing step, the mask removing step, and the microcrack removing step are performed by the same plasma processing apparatus. 2. The method according to claim 1, wherein the protective sheet is peeled off after attaching an adhesive sheet to the second surface after the micro-crack removing step. 3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a mixed gas containing at least a fluorine-based gas is used as a plasma generating gas used in the plasma dicing step. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a gas containing oxygen is used as a plasma generating gas used in the mask removing step. 3. The semiconductor device according to claim 1, wherein a gas of the same type as the plasma generation gas used in the plasma dicing step is used as the plasma generation gas used in the micro crack removal step. Production method. 3. The method according to claim 1, wherein a mixed gas containing at least a fluorine-based gas is used as the plasma generating gas used in the microcrack removing step. 4. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a gas of the same type as the plasma generating gas used in the plasma dicing step is used as the plasma generating gas used in the micro crack removing step.

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