JP2006066663A - Semiconductor package component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element mounting structure for a semiconductor package component in which a semiconductor element is bonded to the surface of an element mount via a bonding material, and which improves the structural strength of the semiconductor package component. <P>SOLUTION: In the mounting structure, the semiconductor package component includes a curved projecting face formed on the end of the mounting side surface of the semiconductor element, and a bonding material filling space which is formed between the curved projecting face covering the entire periphery of the semiconductor element and the surface of the element mount. The bonding material filling space is filled with the bonding material to provide the mounting structure. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor package component having a semiconductor element mounting structure in which a mounting side surface opposite to a circuit forming side surface of a semiconductor element is bonded to the surface of an element mounting body via a bonding material.

  Conventionally, semiconductor package components having this type of semiconductor element mounting structure are known in various structures such as QFP (Quad Flat Package) and BGA (Ball Grid Array). A semiconductor element used for such a semiconductor package component is manufactured by dividing a plurality of semiconductor elements formed on a semiconductor wafer into individual pieces by a dicing process.

  In such a conventional dicing process, for example, each semiconductor element formed on the semiconductor wafer is mechanically cut along the dividing position by using a disk cutter using diamond or the like called a dicer. There is a method of dividing each semiconductor element (see, for example, Patent Document 1). In addition to the method of dicing using such a dicer, there is also a method of dividing by irradiating a laser beam along a dividing line of a semiconductor wafer (see, for example, Patent Document 2).

JP 2003-173987 A JP 2003-151924 A

  In recent years, electronic devices incorporating an electronic circuit using such a semiconductor element have been miniaturized, and along with such miniaturization, the electronic circuit itself is being miniaturized. In particular, efforts to reduce the thickness of semiconductor elements, that is, thinning of semiconductor wafers are being actively carried out, and semiconductor wafers having a thickness of 100 μm or less are being used.

  However, the thinned semiconductor element has a reduced bending strength due to the thinning, and particularly in a dicing process in which a semiconductor element in a wafer state is cut and divided into individual pieces. As a result of mechanical cutting using a laser beam, an edge portion is formed at the end of each semiconductor element, and the presence of such an edge portion is the occurrence of fragments or damage to the element. There is a problem that the bending strength of the semiconductor element is lowered.

  Thus, the reduction in the bending strength of the semiconductor element due to the thinning of the semiconductor element itself or the mechanical dicing process is produced by bonding the semiconductor element to the element mounting body via a bonding material. There is a problem that the structural strength of the semiconductor package component to be manufactured is also lowered.

  Accordingly, an object of the present invention is to solve the above-described problem and improve the structural strength of a semiconductor package component having a semiconductor element mounting structure bonded to the surface of an element mounting body through a bonding material. An object of the present invention is to provide a semiconductor package component that can be used.

  In order to achieve the above object, the present invention is configured as follows.

According to the first aspect of the present invention, a semiconductor package component having a semiconductor element mounting structure in which a mounting side surface opposite to a circuit forming side surface of a semiconductor element is bonded to the surface of an element mounting body via a bonding material. In
A curved convex surface portion formed at an end of the mounting side surface of the semiconductor element;
A bonding material filling space formed between the curved convex surface portion of the entire peripheral portion of the semiconductor element and the surface of the element mounting body;
Provided is a semiconductor package component, wherein the bonding material filling space is filled with the bonding material.

According to the second aspect of the present invention, the bonding material is disposed over the entire peripheral portion of the semiconductor element while contacting the curved convex surface portion, and has a substantially triangular cross section in the circumferential direction of the semiconductor element. Having a joint,
The triangular cross section in the raised joint portion provides the semiconductor package component according to the second aspect, which is a cross section having a divergent shape in each of an inner direction and an outer direction of the semiconductor element.

  According to the present invention, in the semiconductor package component, the curved convex surface portion is formed at the end of the mounting surface of the semiconductor element, and between the curved convex surface portion in the entire peripheral portion of the semiconductor element and the surface of the element mounting body. The space for filling the bonding material formed in this step is filled with the bonding material so that there is almost no gap, so that the structural strength can be improved.

  In particular, the bonding material is disposed over the entire circumference of the semiconductor element while in contact with the curved convex surface, and the triangular cross section in the raised bonding section having a substantially triangular cross section in the circumferential direction of the semiconductor element. In addition to the outward direction of the semiconductor element, it has a divergent shape not only in the inner direction but also in a structure that can withstand external forces from various directions, and its structural strength Can be improved.

  In addition, a semiconductor element having such a curved convex surface portion is difficult to manufacture by a conventional method, but can be specifically manufactured by a method disclosed in this specification.

  Embodiments according to the present invention will be described below in detail with reference to the drawings.

(First embodiment)
A schematic cross-sectional view of a semiconductor package component according to the first embodiment of the present invention is shown in FIG. As shown in FIG. 1, in a semiconductor package component 50, a mounting side surface 6b, which is the surface opposite to the circuit forming surface 6a of the semiconductor element 6d, is bonded to the surface of a substrate 51 as an example of an element mounting body. It has a semiconductor element mounting structure joined through the. Such semiconductor package components include QFP, BGA, and the like, and an electronic circuit can be formed by mounting such a semiconductor package component 50 on a circuit formation substrate or the like. Here, the element mounting body is an object to be bonded on which a semiconductor package component is formed by bonding the semiconductor element, and includes a resin substrate, a paper-phenol substrate, a ceramic substrate, a glass epoxy ( It means an object on which a circuit is formed, such as a circuit board such as a glass-epoxy board, a film board, a circuit board such as a single-layer board or a multilayer board, a component, a housing, or a frame.

  As shown in FIG. 1, in the semiconductor package component 50, the semiconductor element 6 d is fixed at a predetermined position on the surface of the substrate 51 through a bonding material 52 disposed in the vicinity of the mounting surface 6 b and the periphery thereof. Yes. As such a bonding material 52, various materials such as an adhesive such as a resin and a metal paste material can be used.

  Further, on the circuit forming surface 6a of the semiconductor element 6d, a plurality of external connection terminals which are electrode terminals for electrically connecting a circuit forming portion (not shown) formed in the semiconductor element 6d to a circuit outside the element. An electrode 53 is formed. The external connection electrode 53 is made of a conductive metal material. Further, a plurality of electrodes 51 a formed of a conductive metal material are arranged on the surface of the substrate 51, and the external connection electrodes 53 of the semiconductor elements 6 d fixed to the surface of the substrate 51 and the substrates 51 are arranged. Each electrode 51a is electrically connected by a wire 54 formed of a conductive metal material.

  Such a connection method of each electrode using the wire 54 is generally called wire bonding. However, the connection method of each electrode in the semiconductor package component 50 of the first embodiment is as described above. The method is not limited to the method using wire bonding, and other bonding methods such as tape automated bonding (TAB) may be used. In order to protect such a semiconductor element mounting structure in the semiconductor element package component 50, the entire mounting structure may be sealed using a resin or the like.

  Here, FIG. 2 shows a partially enlarged schematic perspective view (with a partial cross-section) for explaining a joint portion between the semiconductor element 6d and the substrate 51 in the semiconductor element package component 50 having such a structure.

  As shown in FIG. 2, an R portion 6e, which is an example of a curved convex surface portion, is formed at the outer peripheral end portion of the mounting surface 6b of the substantially rectangular semiconductor element 6d. That is, in the semiconductor element 6d, there is a corner portion (edge portion) at the outer peripheral end portion of the circuit forming surface 6a that is the upper surface in the figure, whereas the outer peripheral end portion of the mounting side surface 6b that is the lower surface in the figure. The R portion 6e formed of a smooth curved convex surface is formed over the entire outer periphery without any corner portion. In order to join the surface of the R portion 6e and the surface of the substrate 51, a raised joint portion 52a is formed on the entire peripheral portion of the semiconductor element 6d. .

  Further, FIG. 3 shows a partially enlarged sectional view of the vicinity of the R portion 6e and the raised joint portion 52a in the circumferential direction of the semiconductor element 6d. As shown in FIG. 3, a space (bonding material filling space) S surrounded by the curved convex surface of the R portion 6e and the surface of the substrate 51 is filled with the bonding material 52 so that there is almost no gap. ing. Further, the raised joint portion 52a formed of the joining material 52 has a substantially triangular cross section, and the cross section has a divergent shape in the left and right directions in the drawing. That is, the raised joint 52a has a substantially triangular cross section having a divergent shape in each of the inner direction and the outer direction of the semiconductor element 6d.

  The bonding material 52 for fixing the semiconductor element 6d to the substrate 51 is disposed so as to have a substantially triangular cross section as described above due to the presence of the R portion 6e formed in the semiconductor element 6d. The bonding strength between 6d and the substrate 51 can be improved. In particular, such a substantially triangular cross-section has not only a divergent shape in the outer direction of the semiconductor element 6d but also a divergent shape in the inner direction of the semiconductor element 6d. The space S, which is a space between a part of the surface and the surface of the substrate 51, is filled with the bonding material 52 without a gap, so that the resistance to external forces from various directions can be improved. The strength can be further improved. Therefore, the semiconductor element package component 50 that can improve the structural strength can be realized.

  FIG. 3 shows a state in which the bonding material 52 is filled between the mounting side surface 6b of the semiconductor element 6d excluding the R portion 6e and the surface of the substrate 51. In such a case, FIG. Instead, the part may not be filled with the bonding material 52. However, in order to improve the structural strength, it is desirable that the bonding material 52 is also filled in the portion.

  Next, a method for manufacturing the semiconductor element 6d having the R portion 6e that makes it possible to realize such a semiconductor element mounting structure will be specifically described.

  First, a schematic configuration diagram schematically showing the configuration of the plasma processing apparatus 101 used in the manufacturing process of such a semiconductor element is shown in FIG. FIG. 4 is a schematic configuration diagram showing a longitudinal section of the plasma processing apparatus 101. The plasma processing apparatus 101 divides a semiconductor wafer in which a plurality of semiconductor elements are formed on a circuit formation surface (first surface) into individual pieces of semiconductor elements, thereby manufacturing respective semiconductor elements (semiconductors). An element dividing apparatus), which is used for manufacturing a semiconductor element thinned to have a thickness of 100 μm or less, for example.

  In a series of manufacturing processes of such semiconductor elements, first, a protective sheet made of a material that is harder to be plasma etched than silicon, which is the main material of the semiconductor, is attached to the circuit forming surface of the semiconductor wafer. A mask for defining a cutting line (dividing line) for dividing the semiconductor wafer into individual pieces of semiconductor elements is formed on the side surface of the mask that is the side surface. Then, the plasma processing apparatus 101 performs plasma dicing and mask removal processes on the semiconductor wafer in this state.

  Specifically, the configuration of the plasma processing apparatus 101 will be described with reference to FIG.

  In the plasma processing apparatus 101 of FIG. 4, the inside of the vacuum chamber 1 is a processing chamber 2 that performs plasma processing on the above-described semiconductor wafer, and it is possible to form a sealed space for generating plasma under reduced pressure. It has become. A lower electrode 3 (first electrode) is disposed below the inside of the processing chamber 2, and an upper electrode 4 (second electrode) is disposed above the lower electrode 3 so as to face the lower electrode 3. Yes. The lower electrode 3 and the upper electrode 4 have a substantially cylindrical shape, and are arranged concentrically in the processing chamber 2.

  The lower electrode 3 is surrounded by insulating members 5A and 5B, which are two layers mounted so as to fill the bottom of the processing chamber 2, and has an upper surface for holding a processing object at the center of the bottom of the processing chamber 2. It is arranged in an exposed and fixed state. The lower electrode 3 is made of a conductor such as aluminum. The lower electrode 3 protrudes downward from the lower surface of the disk-shaped electrode portion 3a for holding the object to be processed, and one end of the electrode portion 3a is outside the vacuum chamber 1. A cylindrical support portion 3b formed so as to be exposed is provided as an integral state. Further, the support portion 3b is held in the vacuum chamber 1 via the insulating member 5C. By being held in this way, the lower electrode 3 is attached to the vacuum chamber 1 in a state of being electrically insulated. Yes.

  The upper electrode 4 is made of a conductor such as aluminum like the lower electrode 3. The upper electrode 4 protrudes upward from the disk-shaped electrode portion 4 a and the upper surface of the electrode portion 4 a, and one end of the upper electrode 4 is outside the vacuum chamber 1. A cylindrical support portion 4b formed so as to be exposed is provided as an integral state. The support 4b is electrically connected to the vacuum chamber 1 and can be moved up and down by an electrode lifting device 24 (see FIG. 10). The upper and lower electrodes 4 are moved up and down by the electrode lifting / lowering device 24, and a wafer carry-in / out position which is a position where a large space for carrying in / out the semiconductor wafer is formed between the upper electrode 4 and the lower electrode 3. Ascending and descending between the lower end position of the raising and lowering and the discharge space forming position where the discharge space for generating plasma discharge for plasma processing is formed between the upper electrode 4 and the lower electrode 3 It is possible to be done. The electrode lifting / lowering device 24 functions as an inter-electrode distance changing means, and the inter-electrode distance D (see FIG. 5) between the lower electrode 3 and the upper electrode 4 can be changed by moving the upper electrode 4 up and down. it can.

  Next, the detailed structure of the lower electrode 3 and the semiconductor wafer to be processed will be described. As shown in FIG. 4, the upper surface of the electrode portion 3a of the lower electrode 3 is a planar holding surface (an example of a holding portion) on which the semiconductor wafer 6 is placed. An insulating coating layer 3f is provided over the entire circumference. The insulating coating layer 3f is made of ceramic such as alumina. When the lower electrode 3 is mounted in the vacuum chamber 1, the outer edge portion of the insulating coating layer 3f is partially insulated as shown in FIG. Covered by the member 5A. By having such a structure, the outer edge portion of the lower electrode 3 is insulated from the plasma generated in the discharge space, and it is possible to prevent the occurrence of abnormal discharge.

  FIG. 5 is a partial schematic cross-sectional view showing a state in which the semiconductor wafer 6 is placed on the lower electrode 3 before plasma dicing is started. The semiconductor wafer 6 is a semiconductor substrate whose main material is silicon, and a protective sheet 30 is attached to the circuit forming surface 6a (first surface) on the surface (lower surface side in FIG. 5) of the semiconductor wafer 6. In a state where the semiconductor wafer 6 is placed on the holding surface 3g of the electrode portion 3a that is the upper surface of the lower electrode 3, the protective sheet 30 comes into close contact with the holding surface 3g.

  The protective sheet 30 includes an insulating layer in which an insulating resin such as polyimide is formed into a film having a thickness of about 100 μm, and is attached to the circuit forming surface 6a of the semiconductor wafer 6 so as to be peelable by an adhesive. It is done. When the semiconductor wafer 6 to which the protective sheet 30 is attached is held on the lower electrode 3, as will be described later, this insulating layer is a dielectric when the semiconductor wafer 6 is electrostatically adsorbed by the holding surface 3g of the electrode portion 3a. Function as.

  Further, as the material of the protective sheet 30, it is preferable to select a material that is less likely to be etched than silicon, which is the main material of the semiconductor wafer 6, in the plasma dicing described later. By doing so, the protective sheet 30 functions as an etching stop layer even if the etching rate distribution due to the plasma is not uniform during the plasma dicing process and the semiconductor wafer etching rate partially varies. It is like that.

  Further, on the surface opposite to the circuit forming surface 6a (upper side in FIG. 5), a mask arrangement surface 6b (second surface, on which a mask for defining a cutting line (partition line) in plasma dicing described later is arranged is further provided. It becomes the mounting side surface 6b described above). As will be described later, the mask is formed by, for example, machining the surface on the side of the mask arrangement surface 6b by machining and then patterning with the resist film 31a, and thereby the portion of the cutting line 31b to be plasma etched. The region excluding is covered with the resist film 31a. That is, the mask arrangement surface 6b of each semiconductor element in the semiconductor wafer 6 is covered with the resist film 31a.

As shown in FIG. 5, the lower electrode 3 is provided with a plurality of suction holes 3 e that open to the holding surface 3 g, and the suction holes 3 e communicate with suction holes 3 c provided in the lower electrode 3. Yes. Suction hole 3c, as shown in FIG. 4, is connected to the vacuum suction pump 12 via a gas line switchover valve 11, the gas line switchover valve 11 is connected to the N ₂ gas supply unit 13 for supplying N ₂ gas ing. By switching the gas line switching valve 11, the suction hole 3 c can be selectively connected to the vacuum adsorption pump 12 or the N ₂ gas supply unit 13.

  Specifically, the vacuum suction pump 12 is selected by the gas line switching valve 11, and the vacuum suction pump 12 is driven in a state where the suction hole 3c is in communication with the vacuum suction pump 12, so that each suction hole 3e The semiconductor wafer 6 placed on the lower electrode 3 by vacuum suction can be held by vacuum suction. Accordingly, the suction holes 3e, the suction holes 3c, and the vacuum suction pump 12 hold the protective sheet 30 on the electrode portion 3a by vacuum suction from the suction holes 3e opened on the holding surface 3g of the lower electrode 3. It is a vacuum suction means for holding the semiconductor wafer 6 by vacuum suction in a state of being in close contact with the surface 3g.

Further, when the N ₂ gas supply unit 13 is selected by the gas line switching valve 11 and the suction hole 3 c is connected to the N ₂ gas supply unit 13, the N ₂ gas supply unit 13 is connected to the lower surface of the protective sheet 30 from each suction hole 3 e. _Two gas can be ejected. As will be described later, this N ₂ gas is a blow gas for forcibly removing the protective sheet 30 from the holding surface 3g.

  As shown in FIG. The lower electrode 3 is provided with a cooling coolant channel 3d, and the coolant channel 3d is connected to the cooling device 10. By driving the cooling device 10, a coolant such as cooling water circulates in the coolant channel 3 d, and thereby the lower electrode 3 heated by the heat generated during the plasma processing and the protective sheet 30 on the lower electrode 3. Thus, the semiconductor wafer 6 is cooled. The refrigerant flow path 3d and the cooling mechanism 10 serve as cooling means for cooling the lower electrode 3.

  In the plasma processing apparatus 101 of FIG. 4, a vacuum pump 8 is connected to an exhaust port 1 a provided in communication with the processing chamber 2 via an exhaust switching valve 7. By switching the exhaust switching valve 7 to the exhaust side and driving the vacuum pump 8, the inside of the processing chamber 2 of the vacuum chamber 1 is evacuated and the inside of the processing sky 2 can be decompressed. Further, the processing chamber 2 is provided with a pressure sensor 28 (not shown in FIG. 4, refer to FIG. 7). By controlling 8, the inside of the processing chamber 2 can be reduced to a desired pressure. Note that the vacuum pump 8 for reducing the pressure to such a desired pressure is, for example, directly controlling the vacuum pumping capacity of the vacuum pump 8 using a variable capacity pump as the vacuum pump 8. Alternatively, it can be performed by providing an opening adjustment valve (such as a butterfly valve) in the evacuation path and controlling the evacuation capacity indirectly by controlling the opening degree. Note that the vacuum pump 8 and the exhaust switching valve 7 serve as a vacuum exhaust device (decompression unit) that depressurizes the inside of the processing chamber 2 to a desired pressure. Further, by switching the exhaust switching valve 7 to the atmosphere opening side, the atmosphere is introduced into the processing air 2 through the exhaust port 1a, and the pressure inside the processing chamber 2 can be returned to the atmospheric pressure.

  Next, the detailed structure of the upper electrode 4 will be described. The upper electrode 4 includes a central electrode portion 4a and an annular member 4f made of an insulator fixed to the outer peripheral portion so as to surround the electrode portion 4a. The inner diameter of the annular member 4f is substantially the same as the outer diameter of the electrode portion 4a of the lower electrode 3, and is arranged concentrically so as to spread outward from the peripheral surface of the lower electrode 3. The annular member 4f is It has a function of holding a disk-like gas blowing portion 4e disposed at the lower center portion of the upper electrode 4.

  The gas blowing portion 4 e supplies a plasma generating gas for generating a plasma discharge in a discharge space formed between the upper electrode 4 and the lower electrode 3. The gas blowing portion 4e is a member obtained by processing a porous material having a large number of micropores into a disk shape, and includes a lower surface of the electrode portion 4a of the upper electrode 4, an upper surface of the gas blowing portion 4e, and an annular member 4f. The plasma generating gas supplied into the gas retention space 4g surrounded by the peripheral surface can be uniformly blown out into the discharge space through these fine holes and supplied in a uniform state. .

  A gas supply hole 4c communicating with the gas retention space 4g is provided in the support portion 4b, and the gas supply hole 4c is connected to a plasma generation gas supply device disposed outside the vacuum chamber 1. . The plasma generator includes a first gas supply unit 20A, a second gas supply unit 20B, and a third gas supply unit 20C as a plurality of gas supply units that individually supply different types of gases, and respective gases. A gas mixing section (joint section of piping) 19 that mixes gases supplied from the supply sections 20A, 20B, and 20C to make the gas composition uniform, and the gas mixing section 19 and the respective gas supply sections 20A and 20B , 20C, and a gas flow rate adjusting unit 21 for individually adjusting the supply flow rate of each gas supplied to the gas mixing unit 19.

  The gas flow rate adjusting unit 21 includes a first flow rate control valve 23A that uniquely adjusts the gas flow rate supplied from the first gas supply unit 20A, a first on-off valve 22A that can shut off the supply of gas, The second flow rate control valve 23B for independently adjusting the gas flow rate supplied from the gas supply unit 20B, the second on-off valve 22B capable of shutting off the gas supply, and the third gas supply unit 20C A third flow control valve 23C for independently adjusting the gas flow rate and a third open / close valve 22C capable of shutting off the gas supply are provided, and the opening degree control and the open / close control of each valve will be described later. 33.

In the plasma processing apparatus 101 of the present embodiment, for example, sulfur hexafluoride gas (SF ₆ ) can be supplied from the first gas supply unit 20A, and helium gas (He) can be supplied from the second gas supply unit 20B. It is possible to supply oxygen (O ₂ ) from the third gas supply unit 20C. By configuring the plasma generation gas supply device in this way, the gas supply flow rate of the gas supplied from one or more gas supply units selected from the respective gas supply units 20A, 20B, and 20C is changed to the gas flow rate. A gas (mixed gas) that is individually adjusted by the adjusting unit 21 and is supplied to the gas mixing unit 19 with a desired gas composition and flow rate (or a single gas) and mixed in the gas mixing unit 19 Can be supplied into the discharge space through the gas supply hole 4c, the gas retention space 4g, and the gas blowing portion 4e.

  Further, by using the function of the gas flow rate adjusting unit 21 that can individually adjust the flow rate of each gas, by changing only the supply flow rate without changing the gas composition, that is, the gas supply ratio, the processing chamber 2 The pressure inside can be controlled. Specifically, the pressure in the processing chamber 2 is controlled by controlling the gas flow rate adjusting unit 21 by the control device 33 based on the preset pressure condition and the pressure in the processing chamber 2 detected by the pressure sensor 28. Can be adjusted to meet the above pressure conditions. Therefore, the gas flow rate adjusting unit 21 has both a function of adjusting the gas composition supplied into the processing chamber 2 and a function of controlling the pressure in the processing chamber 2.

  Further, as shown in FIG. 4, the lower electrode 3 is electrically connected to the high frequency power supply unit 17 through the matching circuit 16. By driving the high-frequency power supply unit 17, a high-frequency voltage is applied between the upper electrode 4 and the lower electrode 3 that are electrically connected to the vacuum chamber 1 grounded to the ground unit 9. As a result, plasma discharge is generated in the discharge space between the upper electrode 4 and the lower electrode 3 inside the processing chamber 2, and the plasma generating gas supplied into the processing chamber 2 shifts to a plasma state. The matching circuit 16 has a function of matching the impedance of the plasma discharge circuit in the processing chamber 2 and the high-frequency power supply unit 17 when the plasma is generated. In the present embodiment, the high frequency power supply unit 17 and the matching circuit 16 are an example of a high frequency power application device.

  Furthermore, a DC power supply unit 18 for electrostatic attraction is connected to the lower electrode 3 through an RF filter 15. By driving the electrostatic attraction DC power supply unit 18, as shown in the schematic diagram of the plasma processing apparatus 101 in FIG. 6A, the surface of the lower electrode 3 is negatively charged (indicated by “−” in the figure). ) Is accumulated. In this state, as shown in the schematic diagram of the plasma processing apparatus 101 in FIG. 6B, the high frequency power supply unit 17 is driven to generate plasma 34 (shown by a dot display portion in the figure) in the processing chamber 2. Then, a direct current application circuit 32 that connects the semiconductor wafer 6 placed on the holding surface 3g via the protective sheet 30 and the grounding portion 9 is formed via the plasma 34 in the processing chamber 2. As a result, a closed circuit that sequentially connects the lower electrode 3, the RF filter 15, the electrostatic adsorption DC power supply unit 18, the ground unit 9, the plasma 34, and the semiconductor wafer 6 is formed. Are accumulated).

  An insulating layer serving as a dielectric is provided between the negative charge “−” accumulated on the holding surface 3 g of the lower electrode 3 formed of a conductor and the positive charge “+” accumulated on the semiconductor wafer 6. Coulomb force acts through the protective sheet 30 including the semiconductor wafer 6 is held by the lower electrode 3 by this Coulomb force. At this time, the RF filter 15 prevents the high frequency voltage of the high frequency power supply unit 17 from being directly applied to the electrostatic adsorption DC power supply unit 18. The polarity of the electrostatic attraction DC power supply unit 18 may be positive or negative. In this way, in the plasma processing apparatus 101, components that substantially contribute to the generation of plasma can be collectively referred to as a plasma generation apparatus.

  Further, in the above configuration, the electrostatic adsorption DC power supply unit 18 applies a DC voltage to the lower electrode 3, so that the semiconductor wafer 6 separated by the protective sheet 30 and the holding surface 3 g of the lower electrode 3 are interposed. The electrostatic attraction means for electrostatically adsorbing the semiconductor wafer 6 by using the acting Coulomb force. That is, the holding means for holding the semiconductor wafer 6 on the lower electrode 3 includes a vacuum suction means for vacuum-sucking the protective sheet 30 through a plurality of suction holes 3e opened on the holding surface 3g, and the electrostatic suction means described above. Two types can be used properly.

  Similarly to the lower electrode 3, the upper electrode 4 is also provided with a cooling coolant channel 4 d, and the coolant channel 4 d is connected to the cooling device 10. By driving the cooling device 10, a coolant such as cooling water circulates in the coolant flow path 4 d, so that the upper electrode 4 heated by heat generated during the plasma processing can be cooled.

  Further, an opening 1b for taking in and out the semiconductor wafer 6 as a processing object is provided on the side surface of the processing chamber 2 (see FIG. 10). A door 25 that is moved up and down by a door opening / closing device 26 is provided outside the opening 1b, and the opening 1b is opened and closed by moving the door 25 up and down. FIG. 10 shows a state in which the semiconductor wafer 6 is taken in and out in a state where the door 25 is lowered by the door opening / closing device 26 and the opening 1b is opened.

  Further, as shown in FIG. 10, when the semiconductor wafer 6 is put in and out, the upper electrode 4 is lifted by the electrode lifting device 24 and positioned at the wafer loading / unloading position, and is transferred between the upper electrode 4 and the lower electrode 3. To secure space. In this state, the suction head 27 holding the semiconductor wafer 6 is moved into the processing chamber 2 through the opening 1b by operating the arm 27a. As a result, the semiconductor wafer 6 is carried into the lower electrode 3 and the processed semiconductor wafer 6 (semiconductor device) is carried out.

  Next, the configuration of the control system in the plasma processing apparatus 101 having such a configuration will be described below with reference to the control system block diagram shown in FIG.

  As shown in FIG. 7, the control device 33 controls the operation of each component in the plasma processing apparatus 101 based on the storage unit 92 that stores various data and processing programs and these data and processing programs. And a process control unit 91 for controlling the plasma processing. The storage unit 92 stores a plasma processing condition 81 (may be a plasma condition or an operating condition) and a plasma processing operation program 82, and the process control unit 91 stores the operation program 82 and plasma. Plasma processing is controlled based on the processing condition 81. The operation / input unit 94 is input means such as a keyboard, and inputs data such as plasma processing conditions and operation commands. The display unit 93 is a display device, and displays a guidance screen at the time of operation input. Although not shown, the control device 33 may be provided with an external input / output interface to exchange information with the outside of the device.

  Here, plasma processing conditions used in the plasma processing apparatus 101 of the first embodiment will be described. In plasma etching, anisotropic etching having etching characteristics stronger in the thickness direction than the direction along the surface of the semiconductor wafer 6 (that is, etching characteristics with the thickness direction as the main direction), and the direction and thickness along the surface. There are two types of etching with different etching characteristics called isotropic etching having etching characteristics substantially equal to the direction. In the present invention, during the plasma dicing process, the etching characteristics are switched (that is, changed), so that either anisotropic etching or isotropic etching is performed and then switched to the other. Then, dicing processing of the semiconductor wafer is performed.

An example of the plasma processing conditions 81 for performing such anisotropic etching and isotropic etching is shown in the data table of FIG. As shown in FIG. 13, the plasma processing conditions 81 include, for example, the gas composition of each plasma generating gas, the pressure in the processing chamber 2, and the high frequency applied between the upper electrode 4 and the lower electrode 3. It is determined by the combination condition with the frequency (discharge frequency). Specifically, the plasma processing conditions 81A for the anisotropic etching, the gas composition of the mixed gas (i.e., the mixing ratio of each gas) SF _6, O ₂ 10: As 2 ratio, the pressure The condition is a combination of 100 Pa and a frequency of 60 MHz. The plasma processing condition 81B for isotropic etching is a combination of the gas composition of SF ₆ and He at a ratio of 10:30, a pressure of 10 Pa, and a frequency of 13.56 MHz. Yes.

Such switching of etching characteristics is preferably performed by switching the plasma conditions 81A and 81B determined by the combination of the gas composition, pressure, and frequency as described above, but only in such conditions. It is not something that can be done. Instead of such a case, for example, even when only one parameter of the gas composition, pressure, and frequency is switched, the etching characteristics can be switched. In such switching of etching characteristics, the gas composition is the most effective parameter, followed by the order of pressure and frequency. For example, in the case where the etching characteristics are changed by changing only the gas composition, the gas composition of SF ₆ : O ₂ : He is changed from 10: 2: 0 to 10: 0: 30. Thus, switching from anisotropic etching to isotropic etching can be performed. Further, in the case where the etching characteristics are switched by changing only the pressure in the processing chamber 2, the pressure is reduced (for example, from 100 Pa to 10 Pa), so that the anisotropic etching can be performed. Switching to isotropic etching can be performed. In the case where the etching characteristics are switched by changing only the high frequency, the frequency is lowered (for example, from 60 Hz to 13.56 Hz), so that the anisotropic etching is performed. Switching to isotropic etching can be performed. In addition to these parameters, for example, a high-frequency output (for example, set in a range of 500 to 3000 W) and a gas supply flow rate are also used as one parameter.

Moreover, as a gas composition for anisotropic etching, it is preferable to use a gas composition that generates a reaction product that is easily deposited (deposition: vapor deposition or deposition). For example, by using a gas composition containing oxygen as a gas composition for anisotropic etching, fluorine oxide (Si _x F _y O _z ) of silicon can be generated as a reaction product (where x x Y, z are integers). This fluorine oxide has a characteristic that it is harder to etch than silicon. By utilizing these characteristics, a groove is formed on the surface of a semiconductor wafer by anisotropic etching, and a fluorine oxide generated on the inner surface of the formed groove is attached to the film. Can be formed (side wall deposition). On the other hand, it is difficult for fluorine oxide to adhere to the bottom surface of the groove due to physical etching with accelerated ions. As a result, the inner surface of the groove portion can be made harder to etch than the bottom surface, and as a result, the etching can be strongly performed in the thickness direction of the semiconductor wafer, realizing a more ideal anisotropic etching. can do. Therefore, as the gas composition for anisotropic etching, it is preferable to use a gas composition that promotes anisotropic etching, that is, a gas composition that easily causes sidewall deposition.

  In the plasma processing apparatus 101, the plasma dicing process and the ashing process can be performed. The conditions other than the above in the plasma dicing process include the condition of the interelectrode distance D between the upper electrode 4 and the lower electrode 3. For example, values that are considered to be optimal in the range of 5 to 50 mm as the interelectrode distance D (interelectrode distance D1) are set as the plasma processing conditions 81A and 81B. On the other hand, as plasma processing conditions in the ashing process, for example, a high frequency output is 100 to 1000 W, a pressure is 5 to 100 Pa, and a distance D between electrodes is 50 to 100 mm. ) Is set.

  The anisotropic etching plasma processing conditions 81A, the isotropic etching plasma processing conditions 81B, and the ashing plasma processing conditions are stored in the storage unit 92 of the control device 33, respectively. A necessary plasma processing condition 81 is selected for each process based on the operation program 82, and the plasma processing is performed by the process control unit 91 based on the selected plasma processing condition 81.

  In the plasma processing performed based on the operation program 82, as shown in FIG. 7, the gas flow rate adjusting unit 21, the gas line switching valve 11, the high frequency power supply unit 17, the electrostatic adsorption DC power supply unit 18, and the exhaust switching valve 7 are used. Each part of the vacuum pump 8, the vacuum suction pump 12, the door opening / closing device 26, and the electrode lifting / lowering device 24 is controlled by the process control unit 91.

  Further, based on the pressure detection result of the pressure sensor 28, the gas flow rate adjustment unit 21 is controlled by the process control unit 91 to adjust the total amount of each gas supply amount, whereby the pressure inside the processing chamber 2 is adjusted. Can be controlled to match the plasma processing conditions 81.

  Further, as shown in FIG. 7, the control device 33 is provided with a processing time measuring unit 95 that measures the plasma processing time, and measures the processing time of anisotropic etching or isotropic etching, For example, when the measurement result reaches a processing time condition included in each plasma processing condition 81, the process control unit 91 can perform control to end the processing. .

  Next, a semiconductor element manufacturing method performed using the plasma processing apparatus 101 having such a configuration and a semiconductor wafer dividing method (dicing process) performed in the process of the semiconductor element manufacturing method will be described below. To do. 8A to 8H are schematic explanatory diagrams for explaining the processing contents for the semiconductor wafer 6, and FIG. 9 is a flowchart showing the procedure of the manufacturing method, with reference to these drawings. While explaining.

  First, in the state shown in FIG. 8A, the semiconductor wafer 6 is a semiconductor wafer after a plurality of semiconductor elements are formed and further subjected to a thinning process so that the thickness becomes 100 μm or less. . In addition, the protective sheet 30 is detachably attached to the circuit forming surface 6a of the semiconductor wafer 6 via an adhesive, and the circuit forming surface 6a is damaged during each process performed thereafter. To prevent that. In addition, the protective sheet 30 is formed to have the same shape as the outer shape of the semiconductor wafer 6 so as to cover the entire surface of the circuit forming surface 6 a and not to protrude outward from the semiconductor wafer 6. Thereby, the protective sheet 30 is not exposed to the plasma in the plasma treatment, and damage to the protective sheet 30 due to the plasma can be prevented. Further, although the external connection electrode 53 is formed on the circuit forming surface 6a of the semiconductor wafer 6, the illustration thereof is omitted in FIGS.

  Next, as shown in FIG. 8B, a cutting line for dividing the semiconductor wafer 6 into individual semiconductor elements is defined on the mask arrangement surface 6b which is the back surface of the circuit forming surface 6a of the semiconductor wafer 6. A mask to be formed is formed. A resist film 31 made of resin is formed so as to cover the entire mask arrangement surface 6 b of the semiconductor wafer 6. Thereafter, as shown in FIG. 8C, the resist film 31 is patterned by photolithography to remove only the portion corresponding to the cutting line 31b with a width of about 20 μm. As a result, a mask is formed on the mask arrangement surface 6b of the semiconductor wafer 6 so that the region excluding the portion of the cutting line 31b is covered with the resist film 31a, and the semiconductor wafer 6 with the mask in this state is subjected to plasma processing. Become.

  Hereinafter, a plasma processing method for the semiconductor wafer 6 with a mask will be described along the flowchart of FIG. 9 with reference to schematic views of the plasma processing apparatus 101 shown in FIGS. Control of each subsequent operation in the plasma processing apparatus 101 is performed by controlling each component by the process control unit 91 based on an operation program 82 held in the storage unit 92 of the control device 33. Done.

  First, in step S1 of the flowchart of FIG. 9, the semiconductor wafer 6 with a mask is carried into the processing chamber 2 as shown in FIG. During this loading operation, the arm 27a is operated with the upper electrode 4 raised by the electrode lifting device 24, and the semiconductor wafer 6 held by the suction head 27 via the mask is opened from the opening 1b to the processing chamber 2. Then, the semiconductor wafer 6 is placed on the lower electrode 3 via the protective sheet 30.

  Next, the vacuum suction pump 12 is driven to perform vacuum suction from the respective suction holes 3e, thereby turning on the vacuum suction of the semiconductor wafer 6 and turning on the electrostatic suction DC power supply unit 18 (step S2). ). By this vacuum suction, the semiconductor wafer 6 is held by the lower electrode 3 while the protective sheet 30 is in close contact with the holding surface 3 g of the lower electrode 3 in the processing chamber 2.

  Thereafter, the door 25 is closed as shown in FIG. 11, and the upper electrode 4 is lowered by the electrode lifting device 24 (step S3). At this time, in the control device 33, the plasma processing conditions 81A for anisotropic etching in the plasma dicing process are performed by the process control unit 91 based on the operation program 82 out of the respective plasma processing conditions 81 held in the storage unit 92. Is selected and taken out, and the inter-electrode distance D between the upper electrode 4 and the lower electrode 3 is, for example, 5 to 5 based on the condition of the inter-electrode distance D included in the anisotropic etching plasma processing condition 81A. The predetermined condition within the range of 50 mm (that is, the interelectrode distance D1) is set.

Next, the vacuum pump 8 is operated to start the pressure reduction in the processing chamber 2 (step S4). When the inside of the processing chamber 2 reaches a predetermined degree of vacuum, the gas selected by the gas flow rate adjusting unit 21 based on the selected anisotropic etching plasma processing condition 81A has a predetermined gas composition and a predetermined level. The flow rate is adjusted and supplied into the processing chamber 2 (step S5). Specifically, the first opening / closing valve 22A is opened based on the anisotropic etching plasma processing condition 81A, and the SF ₆ is supplied from the first gas supply unit 20A by the first flow control valve 23A. The flow rate is adjusted and supplied to the gas mixing unit 19, the third opening / closing valve unit 22C is opened, and the supply flow rate of O ₂ from the third gas supply unit 20C is changed by the third flow control valve 23C. It is adjusted and supplied to the gas mixing section 19. At this time, the second on-off valve 22B is in a closed state, and He is not supplied. In the gas mixing unit 19, SF ₆ and O ₂ are mixed so as to have a gas composition of 10: 2 and supplied into the processing chamber 2.

  In the gas supply process, the pressure in the processing chamber 2 is detected by the pressure sensor 28 and compared with the pressure condition (for example, 100 Pa) in the plasma processing condition 81A, and the detected pressure is a pressure indicated by the pressure condition. Is confirmed (step S6). That is, the interelectrode distance D between the lower electrode 3 and the upper electrode 4, the gas composition supplied to the processing chamber 2, and the pressure in the processing chamber 2 are set to the plasma processing conditions 81A for anisotropic etching.

  After the above condition setting is completed, the high frequency power supply unit 18 is driven on the basis of the high frequency and output conditions of the plasma processing condition 81A, and the high frequency that meets the conditions is set between the upper electrode 4 and the lower electrode 3. A voltage is applied to start plasma discharge (step S7). Thereby, in the discharge space between the upper electrode 4 and the lower electrode 3, the supplied mixed gas is shifted to a plasma state. Due to the generation of the plasma, the semiconductor wafer 6 is irradiated with the plasma from the mask side (resist film 31a side). By this plasma irradiation, only the portion of the cutting line 31b not covered with the resist film 31a in the silicon which is the main material of the semiconductor wafer 6 is plasma etched by the plasma.

  At the same time, a DC application circuit 32 is formed in the discharge space between the upper electrode 4 and the lower electrode 3 by the plasma (see FIG. 6). Thereby, an electrostatic adsorption force is generated between the lower electrode 3 and the semiconductor wafer 6, and the semiconductor wafer 6 is held by the lower electrode 3 by the electrostatic adsorption force. For this reason, the protective sheet 30 adheres well to the holding surface 3g of the lower electrode 3, the semiconductor wafer 6 is stably held in the plasma processing process, and the protective sheet 30 is good due to the cooling function provided in the lower electrode 3. And the heat damage caused by the heat generated by the plasma discharge is prevented.

  Further, since this plasma etching is performed based on the anisotropic etching plasma processing condition 81 </ b> A, the etching characteristics increase in the thickness direction of the semiconductor wafer 6. Therefore, as shown in FIG. 8D, the surface of the semiconductor wafer 6 corresponding to each cutting line 31b is etched in the thickness direction, and cutting with a width substantially corresponding to the width of the cutting line 31b is performed. A groove 6c is formed.

  In step S8, for example, the time measured by the processing time measuring unit 95 until the depth of the cutting groove 6c reaches a predetermined depth is equal to the processing time of the anisotropic etching plasma processing condition 81A. Plasma dicing by anisotropic etching in step S7 is performed until the conditions elapse.

If it is determined in step S8 that the predetermined time has elapsed, the anisotropic etching is terminated and the isotropic etching plasma processing condition 81B is selected by the process control unit 91, and the condition is satisfied. Based on this, the gas selected by the gas flow rate adjusting unit 21 is adjusted to a predetermined gas composition and a predetermined flow rate, and is supplied into the processing chamber 2 (step S9). Specifically, based on the plasma processing condition 81B for isotropic etching, the first on-off valve 22A is opened, and SF ₆ is supplied from the first gas supply unit 20A by the first flow control valve 23A. The flow rate is adjusted and supplied to the gas mixing unit 19, the second opening / closing valve unit 22B is opened, and the supply flow rate of He is adjusted by the second flow rate control valve 23B from the second gas supply unit 20B. And supplied to the gas mixing unit 19. At this time, the third on-off valve 22C is in a closed state, and O ₂ is not supplied. In the gas mixing unit 19, SF ₆ and He are mixed so as to have a gas composition of 10:30, and supplied into the processing chamber 2.

  In the gas supply process, it is confirmed that the pressure in the processing chamber 2 detected by the pressure sensor 28 has reached the pressure condition (for example, 10 Pa) in the plasma processing condition 81B (step S10). Note that the inter-electrode distance D1 between the lower electrode 3 and the upper electrode 4 is maintained as it is.

  After that, based on the high frequency and output conditions of the plasma processing condition 81B, the high frequency power supply unit 18 is driven to apply a high frequency voltage that matches the conditions between the upper electrode 4 and the lower electrode 3, and plasma discharge Is started to start plasma dicing by isotropic etching (step S11).

  This isotropic etching has the characteristics that the etching characteristics in the direction along the surface of the semiconductor wafer 6 and the etching characteristics in the thickness direction are substantially the same. Etching is performed substantially uniformly in each of the above directions. However, in reality, even in isotropic etching, the etching characteristics in the thickness direction tend to be slightly stronger than the etching characteristics in the direction along the surface, but the etching characteristics clearly differ from the anisotropic etching described above. Is no different.

  When plasma dicing using isotropic etching is performed in this way, each cut groove 6c formed by the anisotropic etching is only in the thickness direction of the semiconductor wafer 6 as shown in FIG. In addition, the entire inner peripheral surface is also etched in the direction along the surface. Accordingly, each cutting groove 6c is expanded in the depth direction while being slightly expanded in the width direction, and when the depth reaches the entire thickness of the semiconductor wafer 6, the semiconductor wafer 6 is connected to each semiconductor element. Divided into 6d pieces (plasma dicing step). In addition, the etching characteristics tend to be stronger in the vicinity of the entrance, which is the upper part of each cutting groove 6c, and become weaker toward the bottom. Therefore, by performing such isotropic etching, as shown in FIG. 8E, an R (R) portion 6e that is a curved convex surface portion is formed at the end portion in contact with the cutting line in each semiconductor element 6d. In particular, R portions 6e are formed at the end portions (corner portions) of the respective semiconductor elements 6d located on the mask arrangement surface 6b side and at the four corner portions of the rectangular plane.

  In step S12, until the depth of the cutting groove 6c reaches the entire thickness of the semiconductor wafer 6, for example, the time measured by the processing time measuring unit 95 is processed under the plasma processing condition 81B for isotropic etching. Plasma dicing by isotropic etching in step S11 is performed until the time condition has elapsed.

  If it is determined in step S12 that the predetermined time has elapsed, isotropic etching is terminated. Thereby, the semiconductor wafer 6 is divided into individual pieces of the semiconductor elements 6d, and R portions 6e are formed at the end portions of the respective semiconductor elements 6d, thereby completing the plasma dicing process.

  When this plasma dicing process is completed, the supply of the mixed gas and the application of the high-frequency voltage are stopped. Thereafter, the inter-electrode distance is changed to shift to the plasma ashing process (step S13). Specifically, the plasma control conditions for plasma ashing are selected by the process control unit 91, and based on the conditions, the upper electrode 4 is raised by the electrode lifting device 24 as shown in FIG. And the lower electrode 3 is set to an interelectrode distance D2. The interelectrode distance D2 when performing mask removal by such plasma ashing is set to be wider than the interelectrode distance D1 in the above-described plasma dicing.

  Thereafter, a plasma ashing gas (for example, oxygen) is supplied from a gas supply unit selected from the gas supply units 20A to 20C based on the plasma processing conditions while adjusting its gas composition and supply flow rate. (Step S14). Then, in the gas supply process, the gas pressure in the processing chamber 2 is detected and compared with the plasma processing conditions, and it is confirmed that the pressure has reached the pressure indicated in the conditions (step S15).

  Thereafter, the high frequency power supply unit 18 is driven to apply a high frequency voltage between the upper electrode 4 and the lower electrode 3, and plasma discharge is started (step S16). Thereby, in the discharge space between the upper electrode 4 and the lower electrode 3, the supplied gas is shifted to a plasma state. The plasma generated in this manner acts on the mask arrangement surface 6b side of the semiconductor wafer 6, whereby the resist film 31a made of an organic substance is ashed (ashed) by the plasma.

  As the ashing proceeds, the resist film 31a gradually disappears, and finally the mask is completely removed from the mask placement surface 6a of the semiconductor wafer 6 as shown in FIG. The output of the high-frequency power source in this mask removal step is set to a predetermined value set in the range of 100 to 1000 W, for example, based on the plasma processing conditions. Then, after the mask is completely removed, the plasma discharge is stopped.

  Thereafter, the operation of the vacuum pump 8 is stopped (step S17), and the exhaust switching valve 7 is switched to release the atmosphere (step S18). Thereby, the pressure in the processing chamber 2 returns to atmospheric pressure. Then, the vacuum suction is turned off, and the electrostatic suction DC power supply is turned off (step S19). As a result, the suction holding of the semiconductor wafer 6 in a state where it is divided into individual pieces of each semiconductor element 6d and held on the protective tape 30 is released.

Thereafter, the semiconductor wafer 6 after the plasma processing is carried out (step S20). That is, the semiconductor wafer 6 is sucked and held by the suction head 27 while N ₂ gas is blown from the suction holes 3 e and is carried out of the processing chamber 2. Thereby, in the plasma processing apparatus 101, the plasma processing which performs each process of plasma dicing and ashing continuously is completed.

  And the semiconductor wafer 6 carried out with the protection sheet 30 is sent to a sheet | seat peeling process, and the protection sheet 30 is peeled from the circuit formation surface 6a of the semiconductor device obtained by dividing | segmenting for every piece of the semiconductor element 6c. . In this sheet peeling, as shown in FIGS. 8G and 8H, the holding adhesive sheet 37 is attached to the mask arrangement surface 6b of each semiconductor element 6d to hold each semiconductor element 6d on the adhesive sheet 37. It is done after letting. Thereby, the manufacturing process of the semiconductor element is completed.

  Here, FIGS. 14 and 15 are partially enlarged cross-sectional views and top views of the semiconductor element 6d formed by performing the plasma dicing performed by combining two types of plasma etching having different etching characteristics as described above. Shown in

  As shown in FIG. 14, an R portion 6e is formed at each end portion (end portion on the upper surface side in the drawing) of the semiconductor element 6d on the mask arrangement surface 6b side. In addition, as shown in FIG. 15, R portions 6e are also formed at four corners of the semiconductor element 6d. By forming the R portion 6e at the end or corner of the thinned semiconductor element 6d, the bending strength can be improved and the occurrence of chip chipping or the like can be suppressed. 6d can be formed by performing a dicing process.

  The processing time of anisotropic etching in such plasma dicing can be determined based on, for example, the line width dimension of the cutting line 31b defined by the mask and the thickness dimension of the semiconductor wafer 6, for example, Based on the line width dimension, the time required to form the cut groove 6c having a depth of about ½ of the thickness dimension of the semiconductor wafer 6 can be determined as the processing time. Further, the processing time of the isotropic etching depends on the line width dimension of the cutting line 31b and the size of the formation region (formation range) of the R portion 6e that can be obtained from the bending strength required for the semiconductor element 6d to be formed. Can be determined based on. For example, when it is desired to increase the bending strength, it is necessary to increase the formation region of the R portion 6e (for example, to increase the R size). Alternatively, the size of the region where the R portion 6e is formed is such that the material of the semiconductor package component 50 to be manufactured is filled with the sex convenience material 52 between the curved convex surface of the R portion 6e of the semiconductor element 6d and the surface of the substrate 51. Can be obtained based on the size of the space S.

  A method for determining each processing time, that is, a method for determining the timing of switching the characteristics of plasma etching will be described using a specific example. For example, in the case where isotropic etching is performed after anisotropic etching, the size of the R portion 6e determined by the required bending strength using the semiconductor wafer 6 having a thickness of 50 μm. Considering the case of forming each semiconductor element 6d having a thickness of R15 μm, the etching amount by anisotropic etching in the thickness direction of the semiconductor wafer 6 is 35 μm, and the etching amount by isotropic etching is 15 μm.

Here, when the etching rate of anisotropic etching is S ₁ μm / min and the etching rate of isotropic etching is S ₂ μm / min, the processing time T ₁ (sec) of anisotropic etching is isotropic. The etching processing time T ₂ (sec) can be calculated as in the numbers (1) and (2).
T ₁ = (35 μm / S ₁ ) × 60 (1)
T ₂ = (15 μm / S ₂ ) × 60 (2)

Since the processing times T ₁ and T ₂ calculated in this way are theoretical values, plasma etching is actually performed on the basis of these processing times, and as a result, the semiconductor elements 6d that have been divided are formed. By measuring the size of the R portion 6e, the respective processing times T ₁ and T ₂ can be corrected to obtain the optimum processing time. Incidentally, when performing anisotropic etching earlier, the processing time T ₁ of the anisotropic etching, the switching timing of the etching characteristics.

  In the plasma dicing process, when switching between anisotropic etching and isotropic etching is repeated a plurality of times, the size of the R portion 6e is determined by the total processing time of each isotropic etching. Can be determined.

  In the above-described plasma dicing, the case where isotropic etching is performed after anisotropic etching has been described as two types of etching having different etching characteristics, but the present embodiment is such a case. It is not limited to only. Instead of such a case, plasma dicing may be performed by performing isotropic etching first and then performing anisotropic etching. Thus, even in the case where isotropic etching is performed first, the cutting groove 6c can be formed by etching the forming position of the cutting line 31b in the thickness direction due to the etching characteristics. The R portion 6e can be formed by etching the cutting groove 6c in the width direction at the time of formation. Further, anisotropic etching is performed on the cut groove 6c in which the R portion 6e is formed in this manner, so that the depth of the cut groove 6c is reduced to the thickness of the semiconductor wafer 6 while maintaining the shape of the R portion 6e. Dicing can be performed up to 2mm.

  Next, a method for manufacturing the semiconductor package component 50 using each semiconductor element 6d in the semiconductor wafer 6 manufactured in this way will be described. In this description, FIG. 16 shows a schematic diagram of a semiconductor element mounting apparatus 201 that takes out the semiconductor element 6 d divided into pieces from the semiconductor wafer 6 and mounts the semiconductor element 6 d on the substrate 51.

  As shown in FIG. 16, the semiconductor element mounting apparatus 201 serves as the base of the semiconductor package component 50 and the element supply unit 210 on which the divided semiconductor wafer 6 is placed so that the respective semiconductor elements 6 d can be taken out. One semiconductor element 6d is sucked and held out from the substrate placing part 220 on which the plurality of substrates 51 are placed and the semiconductor wafer 6 placed on the element supply part 210, and the semiconductor element 6d is placed on the substrate. The mounting head 230 is mounted on the upper surface of one substrate 51 by moving it above the portion 220. The mounting head 230 includes a suction nozzle 231 that performs the suction holding. Further, the mounting head 230 is provided with a moving device (not shown) that moves the mounting head 230 in a direction along the surface of the semiconductor wafer 6.

  With respect to the mounting operation of the semiconductor element 6d to the substrate 51 performed using the semiconductor element mounting apparatus 201 as described above, the schematic explanatory views of FIGS. 17A to 17D and FIGS. This will be described specifically with reference to schematic explanatory diagrams.

  First, in FIG. 16, the mounting head 230 is moved above the element supply unit 210 on which the divided semiconductor wafer 6 is placed, and the positions of the suction element 231 and the semiconductor element 6d to be taken out. Matching is done. On the other hand, as shown in FIG. 17A, the element supply unit 210 pushes up the semiconductor element 6 d attached to the adhesive sheet 37 from below the adhesive sheet 37, thereby removing the semiconductor element 6 d from the adhesive sheet 37. A push-up device 211 that is peeled off and assists removal by the suction nozzle 231 is provided. The push-up device 211 is provided with a push-up pin 212 that can be moved up and down to perform the push-up operation.

  When the suction nozzle 231 and the semiconductor element 6d to be taken out are aligned, the semiconductor element 6d and the push-up device 211 are also aligned at the same time. The state in which this alignment is performed is the state shown in FIG. 17A, and in this state, the push-up pin 212 is in a state stored in the push-up device 211.

  Thereafter, as shown in FIG. 17B, the tip of the suction nozzle 231 is brought into contact with the circuit forming surface 6a of the semiconductor element 6d to perform suction holding, and the lift pin 212 of the thrust device 211 starts to rise. The As shown in FIG. 17C, the raised pin 212 further raised penetrates the adhesive sheet 37 and peels the semiconductor element 6 d from the adhesive sheet 37. Further, as shown in FIG. 17D, the semiconductor nozzle 6 d is taken out from the semiconductor wafer 6 by raising the suction nozzle 231 in conjunction with this push-up operation. During the peeling operation of the semiconductor element 6d from the adhesive sheet 37, the R portion 6e is formed at the end of the mounting side surface 6b of the semiconductor element 6d, so that the peelability is improved. it can. In particular, since the above-described peelability of the thinned semiconductor element 6d is good, the risk of damaging the semiconductor element 6d during the peeling can be reduced, and the semiconductor package component 50 formed thereafter can be reduced. It is possible to reliably prevent the structural strength from decreasing (due to the occurrence of the damage).

  Thereafter, in the semiconductor element mounting apparatus 201 of FIG. 16, the mounting head 230 is moved from above the element supply unit 210 to above the substrate mounting unit 220. In the substrate platform 220, a plurality of substrates 51 are placed, and a bonding material 52 is applied and supplied in advance to the mounting position of the semiconductor element 6d on the upper surface thereof, for example.

  The suction nozzle 231 in a state where the semiconductor element 6d is sucked and held is moved above the substrate 51 in such a state, and the mounting position on the substrate 51 and the position of the suction nozzle 231 as shown in FIG. Align. Thereafter, as shown in FIG. 18B, the suction nozzle 231 is lowered to bond the semiconductor element 6d against the mounting position of the substrate 51 with the bonding material 52 interposed therebetween. By performing such an operation, the bonding material is filled so that there is substantially no gap between the R portion 6e formed at the end of the mounting surface 6b of the semiconductor element 6d and the surface of the substrate 51. Can be made. Thereafter, the semiconductor element 6d is mounted on the substrate 51 by releasing the suction holding by the suction nozzle 231.

  Thereafter, the external connection electrode 53 of the semiconductor element 6d is connected to the electrode 51a of the substrate 51 with a wire 54, thereby completing the semiconductor package component 50 as shown in FIG.

  According to the first embodiment, the following various effects can be obtained.

  First, in the dicing process of dividing the thinned semiconductor wafer 6 into individual pieces of the semiconductor elements 6d, by performing plasma etching without using a dicer or laser light, a semiconductor is used during the dicing. It is possible to reliably prevent generation of a piece of the wafer 6 and suppress a reduction in processing yield in dicing.

  Also, in such plasma dicing, anisotropic etching and isotropic etching, which have different etching characteristics from each other, are used separately, and after etching one of the characteristics, the etching conditions are changed (switched). The semiconductor element 6d can be processed so that the bending strength can be improved by performing etching with the other characteristic.

  Specifically, for example, in plasma dicing, by performing anisotropic etching first, the surface portion of the semiconductor wafer 6 where the cutting line 31b defined by the mask is disposed has a strong etching characteristic in the thickness direction. The cutting groove 6c can be formed as a groove having a fine width. Thereafter, the etching characteristic is switched to isotropic etching, and the inner peripheral surface of the formed cutting groove 6c is etched not only in the thickness direction of the semiconductor wafer 6 but also in the direction along the surface thereof. The cutting groove 6c can be etched not only in the depth direction but also in the width direction. By performing such etching, an R portion 6e that is a curved convex surface portion is formed at the end or corner portion of the semiconductor element 6d, and the bottom of the cutting groove 6c is made to reach the surface of the protective sheet 30 to form a semiconductor. The wafer 6 can be divided. By forming the R portion 6e at the end or corner of each of the semiconductor elements 6d divided in this way, the bending strength of the semiconductor element 6d itself can be improved, and the thinned semiconductor element can be obtained. However, a semiconductor element having high strength can be provided.

  Accordingly, the dicing process for the thinned semiconductor wafer 6 not only prevents the occurrence of damage by preventing the occurrence of fragments, but also forms the R portion 6e in each semiconductor element 6d, thereby increasing the bending strength. Can be improved.

  By performing such a dicing process, it is possible to easily form the R portion 6e at the end of the mounting surface 6b of the semiconductor element 6d, and it is also necessary to perform a complicated process for forming the R portion 6e. Nor.

  Furthermore, in the semiconductor package component 50 having a structure in which the bonding material 52 is filled between the curved convex surface of the R portion 6e of the semiconductor element 6d having such a structure and the surface of the substrate 51, the semiconductor package component 50 from various directions is used. It will have the structure which opposes an external force, and higher structural strength can be obtained.

(Second Embodiment)
In addition, this invention is not limited to the said embodiment, It can implement with another various aspect. For example, the method of forming the R portion in the semiconductor element is not limited to the case according to the first embodiment. A method for manufacturing a semiconductor element while forming an R portion in the semiconductor element by a method different from the first embodiment will be described below as a second embodiment of the present invention.

  First, FIG. 19 shows a schematic configuration diagram schematically showing a configuration of a plasma processing apparatus 300 used in the manufacturing process of such a semiconductor element. The plasma processing apparatus 300 is an apparatus that performs plasma etching on a semiconductor wafer on which a plurality of semiconductor elements are formed, thereby dividing each semiconductor element into individual pieces (plasma dicing process). First, a schematic configuration of the plasma processing apparatus 300 will be described below with reference to FIG.

  As shown in FIG. 19, the plasma processing apparatus 300 includes a vacuum chamber 311 that forms therein a processing chamber 312 that is a sealed space for performing plasma processing on the semiconductor wafer 1. Inside the vacuum chamber 311, a lower electrode 313 and an upper electrode 314 are arranged in parallel and facing each other. In addition, a mounting surface 313 a on which a substantially disk-shaped semiconductor wafer 301 can be mounted is formed on the upper surface of the lower electrode 313 in the figure, and the semiconductor wafer 301 is formed on the mounting surface 313 a by an insulating ring 318. It is placed in a state where the entire periphery is enclosed. Such an insulating ring 318 has a function of preventing abnormal discharge and protecting the lower electrode 313 from plasma. Further, the mounting surface 313a has a function of sucking and holding the mounted semiconductor wafer 301 by vacuum suction or electrostatic suction.

  The upper electrode 314 has a gas supply hole 314a that is a passage for supplying a plasma generating gas into a space (discharge space) formed between the upper electrode 314 and the lower electrode 313. It is formed so as to penetrate through the inside. Further, in the upper electrode 314, one end of a gas supply hole 314a formed so as to communicate with the outside of the vacuum chamber 311 is connected to a plasma generating gas supply unit 317 provided outside the vacuum chamber 311. For example, a fluorine-based plasma generating gas can be supplied from the plasma generating gas supply unit 317 into the processing chamber 312 through the gas supply hole 314a. In the middle of the gas supply passage between the plasma generating gas supply unit 317 and the one end of the gas supply hole 314a, an example of a gas flow rate adjustment unit that adjusts the supplied gas flow rate to a desired flow rate is shown. A flow control valve 316 is provided. Further, a porous plate 315 is provided on the lower surface of the upper electrode 314 in the figure, and a plasma generating gas supplied through the gas supply hole 314a passes through the porous plate 315 through which the lower electrode 313 is placed. It can be supplied into the processing chamber 312 so as to be sprayed uniformly on the semiconductor wafer 1 placed on 313a.

  In addition, the plasma processing apparatus 300 includes an exhaust pump 319 that is an example of a vacuum exhaust apparatus that exhausts the inside of the processing chamber 312 to reduce the inside of the processing chamber 312 to a desired pressure (that is, evacuates). Yes. In addition, a high frequency power supply unit 320 is electrically connected to the lower electrode 313, and a high frequency voltage can be applied to the lower electrode 313 by the high frequency power supply unit 320.

  In the plasma processing apparatus 300 having such a configuration, after the semiconductor wafer 301 is mounted on the mounting surface 313a of the lower electrode 313 and the vacuum chamber 311 is sealed, the inside of the processing chamber 312 is evacuated by the exhaust pump 319 and vacuumed. In the state where a predetermined amount of plasma generating gas is supplied into the processing chamber 312 from the plasma generating gas supply unit 317, the high frequency power supply unit 320 is driven to apply a high frequency voltage to the lower electrode 313. Fluorine-based plasma can be generated in the discharge space between the upper electrode 314 and the lower electrode 313. By irradiating the surface of the semiconductor wafer 301 with the plasma generated in this manner, the irradiated surface can be etched (ie, plasma etching). The plasma processing apparatus 300 includes a cooling unit 321 that cools the semiconductor wafer 301 mounted through the mounting surface 313a of the lower electrode 313 by circulating a coolant inside the lower electrode 313. . By providing the cooling unit 321 in this way, it is possible to prevent the semiconductor wafer 301 from being heated to a predetermined temperature or higher due to heat generated during the plasma processing.

  Next, a series of manufacturing steps of each semiconductor element including the dividing process of the semiconductor wafer 301 performed using the plasma processing apparatus 300 having such a configuration will be described below. In the description, FIG. 20 is a flowchart showing the procedure of the manufacturing process of the semiconductor element, and schematic explanatory diagrams for explaining the procedure of the manufacturing process are shown in FIGS. 21 (A) to (D) and FIG. 22 (A). ) To (D).

  First, in step S31 of the flowchart of FIG. 20, as shown in FIG. 21A, the circuit formation surface 301a that is the first surface of the semiconductor wafer 301 is subjected to processing such as film formation, exposure, and etching. Thus, a plurality of circuit forming portions 302 to be semiconductor elements are formed (semiconductor element forming step). Further, a plurality of external connection electrodes 303 are formed on each circuit formation portion 302 with a conductive material so as to be exposed from the circuit formation surface 301a. Thus, the semiconductor wafer 301 on which the respective circuit forming portions 302 and the external connection electrodes 303 are formed has the respective circuit forming portions 302 and external connection in order to determine whether or not there are any defective portions in the formation state. The formation state of the electrode 303 is inspected (semiconductor element inspection step, step S32). It should be noted that for semiconductor elements that are determined to be defective in such an inspection, necessary measures are taken so that they are not used as semiconductor elements afterwards by storing their positional information on the semiconductor wafer 301 or the like. Is taken.

  In addition, the protective sheet 304 is placed on the circuit forming surface 301a with an adhesive so that the circuit forming surface 301a is not damaged during the subsequent processing of the semiconductor wafer 301 on which the inspection process has been completed. It is attached so that it can be peeled off. The protective sheet 304 is formed by covering the entire surface of the circuit forming surface 301 a and shaping it to approximately the same shape as the outer shape of the semiconductor wafer 301 so as not to protrude outward from the end of the semiconductor wafer 301. By using the protective sheet 304 having such a shape, it is possible to prevent occurrence of damage in which the protective sheet 304 protruding from the semiconductor wafer 301 is burned out by plasma in subsequent processing, for example, plasma processing.

  Next, in step S33 of FIG. 20, a polishing step for reducing the thickness of the semiconductor wafer 301 is performed. Specifically, as shown in FIG. 21C, the semiconductor wafer 301 is placed on the holding table 332 of the polishing apparatus via the protective sheet 304 with the circuit forming surface 301a of the semiconductor wafer 301 as the lower side in the figure. At the same time, the mounting position is held. In this state, polishing is performed using the grinding wheel 331 on the surface 301b to be processed (the second surface and then the surface on the mounting side) which is the surface opposite to the circuit forming surface 301a of the semiconductor wafer 301. Is called. A grinding wheel is fixed to the lower surface of the grinding wheel 331 in the drawing, and the grinding surface 301b is ground by rotating the grinding wheel along the surface while contacting the grinding surface 301b of the semiconductor wafer 301. . By such a polishing process, the semiconductor wafer 301 is thinned to have a thickness of about 100 μm or less, for example, a thickness of 50 μm in the second embodiment.

  Next, a dividing groove 301c is formed on the surface 301b of the semiconductor wafer 301 thus thinned in accordance with the dividing position of each semiconductor element (groove forming step (half-cut dicing), step. S34). Specifically, as shown in FIG. 21D, the semiconductor wafer 301 is placed on the holding table 342 of the dicer via the protective sheet 304 and the placement position is held, so that the semiconductor wafer 301 is covered. A dividing groove 301c is formed on the processing surface 301b by using a disk-shaped rotary blade 341. In the semiconductor wafer 301, the respective circuit forming portions 302 are arranged in a lattice shape, and the division positions thereof are determined in a lattice shape so that the respective circuit forming portions 302, that is, the respective semiconductor elements can be individually divided. Yes. While rotating the disk-shaped rotary blade 341, the disk-shaped rotary blade 341 is brought into contact with the processing surface 301b of the semiconductor wafer 301 and moved linearly along the above-mentioned division position, so that a lattice can be formed along the division position. Can be formed. In addition, as such a disk type rotary blade 341, what is called a dicer can be used.

  Here, FIG. 23 shows an enlarged cross-sectional view of the dividing groove 301c formed in this way. As shown in FIG. 23, the dividing groove 301c is formed with a depth dimension L determined so that the bottom surface does not reach the circuit forming surface 301a (that is, half-cut is performed). By forming in this way, it is prevented that each semiconductor element is divided into individual pieces due to the formation of the dividing groove 301c. Here, the “dividing groove portion” is a recess formed in the processing target surface 301b of the semiconductor wafer 301, and its bottom surface does not reach the circuit forming surface 301a. That is, such a concave portion whose bottom surface reaches (or penetrates) the circuit forming surface 301a is not referred to as a dividing groove 301c in this specification.

  Further, the depth dimension L of the dividing groove 301c is determined to be equal to or greater than the thickness dimension of each semiconductor element to be finally formed. In the present embodiment, the depth dimension L of the dividing groove 301c is 25 μm with respect to the thickness dimension 50 μm of the thinned semiconductor wafer 301, and the thickness dimension of the semiconductor element finally formed is Is 25 μm. In this case, the distance between the bottom surface of the dividing groove 301c and the circuit forming surface 301a is, for example, in the range of 5 to 25 μm in consideration of the minimum distance that can be retained as the dividing groove 301c. Can be determined. Further, by performing mechanical processing such as a polishing process (step S33) and a groove forming process (step S34), as shown in FIG. 23, the surface to be processed 301b of the semiconductor wafer 301 and the dividing groove 301c In the vicinity of the surface, a damage layer 301f in which the applied stress remains is formed.

  Thus, the first reason for the lower limit of the distance dimension between the bottom surface of the dividing groove 301c and the circuit forming surface 301a being defined as 5 μm is that the strength of the semiconductor wafer 301 after the half-cut dicing is as follows. The second reason is to reduce the time during which the protective sheet 304 is exposed to plasma. In order to remove the damaged layer 301f formed on the processing target surface 301b of the semiconductor wafer 301, it is necessary to remove the processing target surface 301b with a thickness of at least 5 μm from the surface. However, if the distance between the bottom surface of the dividing groove 301c and the circuit forming surface 301a is less than 5 μm, the dividing groove 301c is removed before the damage layer 301f formed on the processing target surface 301b is removed. Thus, the protective sheet 304 corresponding to the portion where the dividing groove 301c was formed is exposed to high-temperature plasma until the damaged layer 301f on the surface 301b to be processed is completely removed. Therefore, by preventing the dividing groove 301c from being removed before the removal of the damaged layer 301f on the surface to be processed 301b, it is possible to prevent such a problem from occurring, and the bottom surface and circuit of the dividing groove 301c can be prevented. The lower limit of the distance dimension with respect to the formation surface 301a is defined as 5 μm or more.

  Next, plasma etching is performed on the semiconductor wafer 301 thus formed with the dividing groove 301c (plasma etching step, step S35). In the second embodiment, this plasma etching is performed without forming a mask layer on the surface of the semiconductor wafer 301.

  Specifically, in the plasma processing apparatus 300 shown in FIG. 19, the semiconductor wafer 301 is disposed via the protective sheet 304 with the processing surface 301 b on which the dividing groove 301 c is formed on the mounting surface 313 a of the lower electrode 313. Is placed. Thereafter, the vacuum chamber 311 is sealed, the exhaust pump 319 is driven to evacuate the inside of the processing chamber 312, and the gas with the flow rate adjusted by the flow rate adjustment valve 316 is supplied from the plasma generation gas supply unit 317 to the gas supply. The gas is supplied into the processing chamber 312 through the holes 314 a and the porous plate 315. By applying a high frequency voltage to the lower electrode 313 by the high frequency power supply unit 320 in such a state, plasma can be generated in the discharge space between the upper electrode 314 and the lower electrode 313.

  As shown in FIG. 22A, the plasma 351 generated in the discharge space and the entire surface to be processed 301b of the semiconductor wafer 301 in a state of being placed on the placement surface 313a of the lower electrode 313 and the respective surfaces. The inner surface of the dividing groove 301c is irradiated. By irradiating with plasma in this way, etching is performed on the entire surface to be processed 301b and the inner surface of the dividing groove 301c.

  By performing plasma etching on the entire surface to be processed 301b of the semiconductor wafer 301, the thickness of the semiconductor wafer 301 is reduced, and at the same time, plasma etching is performed on the inner surface of each dividing groove 301c. By being applied, each of the dividing groove portions 301c is removed. By removing each of the dividing groove portions 301c in this manner, the semiconductor wafer 301 is divided into individual pieces of the semiconductor elements 301d along the dividing position as shown in FIG. 22B. It becomes. Here, “the dividing groove 301c is removed” means that the bottom surface of the dividing groove 301c is etched to bring the bottom surface closer to the circuit forming surface 301a, and finally the bottom surface forms the circuit. By matching with the surface 301a, it means that the bottom surface is extinguished. That is, by removing the dividing groove 301c, the surface 301b to be processed and the circuit forming surface 301a are penetrated along the dividing position in the semiconductor wafer 301.

  FIG. 24 shows a partially enlarged cross-sectional view of the semiconductor element 301d in the state of being divided into individual pieces in the vicinity of the division position. As shown in FIG. 24, by performing the plasma etching, the inner surface of the dividing groove 301c is also etched together with the surface to be processed 301b, but the surface to be processed 301b is masked like the conventional plasma etching. Since the layer is not disposed, the corner portion (edge portion) where the entrance end portion of the dividing groove portion 301c is formed is similarly etched. As a result, the corner portion is removed, and the semiconductor element is removed. An R (R) portion 301e, which is an example of a curved convex surface portion, is formed at the end of 301d to be processed 301b. Note that etching is mainly performed in the thickness direction of the semiconductor wafer 301 by plasma etching with respect to the dividing groove 301c. However, etching is slightly performed in the direction along the surface of the semiconductor wafer 301 due to the etching characteristics. Such etching characteristics contribute to the formation of the respective R portions 301e. In consideration of the fact that the width dimension of the dividing groove 301c is enlarged by the etching, the width dimension of the dividing groove 301c is previously set. It is desirable to decide.

  Further, by performing plasma etching on the processing target surface 301b of the semiconductor wafer 301 and the inner surfaces of the respective dividing groove portions 301c, the dividing process into the respective semiconductor elements 301d is performed, and the above-described mechanical processing is performed. The damaged layer 301f generated by the processing can be removed.

  When such plasma etching is completed in the plasma processing apparatus 300, the application of the high frequency voltage by the high frequency power supply unit 320, the supply of the gas from the plasma generating gas supply unit 317, and the driving of the exhaust pump 319 are stopped, and then the vacuum processing is performed. The chamber 311 is opened and the semiconductor wafer 301 is taken out.

  As shown in FIG. 22C, an adhesive sheet (die bonding sheet) 306 is attached to the surface 301b to be processed (die bonding sheet attaching step, step S36) to the semiconductor wafer 301 taken out from the plasma processing apparatus 300. ). At the same time, as shown in FIG. 22D, the protective sheet 304 protecting the circuit forming surface 301a of the semiconductor wafer 301 is peeled off. Here, the pressure-sensitive adhesive sheet 306 has a size larger than that of the semiconductor wafer 301, and is further fixed around it by a wafer ring (jig) (not shown). By gripping the wafer ring, the semiconductor wafer 301 is held. It is possible to handle. The semiconductor element manufacturing process is thus completed.

  In this way, the circuit formation surface 301a of each semiconductor element 301d in the state of being stuck to the adhesive sheet 306 is sucked and held by, for example, a suction nozzle, and the suction nozzle is raised in that state, so that the semiconductor that is sucked and held. The element 301d can be peeled off from the adhesive sheet 306 and taken out.

  In the semiconductor element 301d formed in this manner, an R portion 301e is formed at the end of the mounting side surface 301b. Using the semiconductor element 301d, the semiconductor package of the first embodiment is formed. Similar to the component 50, a semiconductor package component having improved structural strength can be manufactured.

  Furthermore, in the method according to the second embodiment, a semiconductor element having an R portion can be manufactured while eliminating the steps of mask placement and removal, and the efficiency of manufacturing the semiconductor element can be improved.

  It is to be noted that, by appropriately combining arbitrary embodiments of the various embodiments described above, the effects possessed by them can be produced.

1 is a schematic cross-sectional view of a semiconductor package component according to a first embodiment of the present invention. It is a model perspective view containing the partial cross section of the semiconductor package component of the said 1st Embodiment. FIG. 3 is an enlarged cross-sectional view in the vicinity of an R portion in the semiconductor package component of the first embodiment. It is a schematic block diagram which shows the structure of the plasma processing apparatus of the said 1st Embodiment. It is a partial expanded sectional view of the lower electrode of the said plasma processing apparatus. It is a schematic block diagram of the said plasma processing apparatus, Comprising: (A) is a schematic block diagram which shows the state by which the negative charge was accumulate | stored on the surface of the lower electrode by the drive of the power supply part for electrostatic attraction, (B) It is a schematic block diagram which shows the state by which the plasma was generated in the process chamber by the drive of the high frequency power supply part. It is a control block diagram which shows the structure of the control system of the said plasma generator. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic explanatory drawing of the semiconductor wafer which shows each process in the manufacturing method of the semiconductor element concerning the said 1st Embodiment, (A) shows the semiconductor wafer in the state where the protective sheet was stuck, (B) A semiconductor wafer in which a resist film is formed is shown, (C) shows a semiconductor wafer in a state in which a mask for defining a cutting line is formed, and (D) shows a semiconductor in a state in which anisotropic etching is performed. (E) shows a semiconductor wafer subjected to isotropic etching, (F) represents a semiconductor wafer subjected to an ashing process, and (G) represents a semiconductor wafer in each semiconductor element. The state where the adhesive sheet was stuck on the mask arrangement | positioning surface is shown, (H) shows the state from which the protective sheet was peeled from the circuit formation surface. It is a flowchart which shows the procedure of the division | segmentation method of the semiconductor wafer concerning the said 1st Embodiment. It is a schematic cross section of the plasma processing apparatus in the state in which the semiconductor wafer is carried in. It is a schematic cross section of the plasma processing apparatus in the state where the plasma dicing process is performed. It is a schematic cross section of the plasma processing apparatus in the state where the plasma ashing process is performed. It is a figure which shows the data table of the plasma processing conditions used in the said plasma dicing process. It is a schematic cross section of a semiconductor element subjected to the plasma dicing process. It is a model top view of the semiconductor element in which the said plasma dicing process was given. It is a schematic diagram which shows the structure of the semiconductor element mounting apparatus which mounts the semiconductor element of the said 1st Embodiment. It is a schematic explanatory drawing which shows the mounting method of a semiconductor element, Comprising: (A) is a figure which shows the state by which the position alignment of a suction nozzle and a pushing-up apparatus is performed, (B) shows the state by which pushing-up operation was started. (C) is a figure which shows the state from which the semiconductor element was peeled, (D) is a figure which shows the state from which the semiconductor element was taken out. It is a schematic explanatory drawing which shows the mounting method of a semiconductor element, Comprising: (A) is a figure which shows the state with which the mounting position of a board | substrate and the suction nozzle are aligned, (B) is a figure which shows a semiconductor element on a board | substrate. It is a figure which shows the joined state. It is a schematic block diagram which shows the structure of the plasma processing apparatus concerning the 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the manufacturing process of the semiconductor element in which the division | segmentation of the semiconductor element of the said 2nd Embodiment is performed. FIG. 21A is a schematic explanatory diagram for explaining a manufacturing process of the semiconductor element of FIG. 20, in which FIG. 20A is a diagram in a state where a circuit formation portion and external connection electrodes are formed on a semiconductor wafer, and FIG. It is a figure of the state in which the protective sheet was stuck on the circuit formation surface of a wafer, (C) is a figure of the state in which the grinding | polishing process for thinning of a semiconductor wafer is performed, (D) is a semiconductor wafer It is a figure of the state by which the groove part for a division | segmentation is formed in the to-be-processed surface. FIG. 21 is a schematic explanatory diagram for explaining the manufacturing process of the semiconductor element of FIG. 20 following FIG. 21, in which (A) is a state in which plasma etching is performed, and (B) is a diagram of (A). It is the figure of the state divided | segmented into the piece of each semiconductor element by plasma etching, (C) is a figure of the state by which the adhesive sheet is affixed on the to-be-processed surface of a semiconductor wafer, (D) is protection It is a figure of the state by which the sheet | seat was peeled. It is a partial expanded sectional view of the groove part for a division | segmentation formed in the semiconductor wafer. It is a partial expanded sectional view of the division | segmentation position vicinity in each divided | segmented semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vacuum chamber 2 Processing chamber 3 Lower electrode 4 Upper electrode 5A, 5B, 5C Insulating member 6 Semiconductor wafer 6a Circuit formation surface 6b Mask placement surface or mounting side surface 6e R portion 8 Vacuum pump 17 High frequency power supply portion 18 For electrostatic adsorption DC power supply unit 19 Gas mixing unit 20A, 20B, 20C 1st to 3rd gas supply unit 21 Gas flow rate adjustment unit 22A, 22B, 22C 1st to 3rd on-off valve 23A, 23B, 23C 1st to 3rd Flow control valve 28 Pressure sensor 30 Protective sheet 33 Controller 50 Semiconductor package component 51 Substrate 52 Bonding material 53 External connection electrode 54 Wire 81 Plasma processing condition 82 Operation program 91 Process control unit 92 Storage unit 95 Processing time measurement unit 101 Plasma processing Device S space

Claims (2)

In a semiconductor package component having a semiconductor element mounting structure in which a mounting side surface opposite to a circuit forming side surface in a semiconductor element is bonded to the surface of an element mounting body via a bonding material,
A curved convex surface portion formed at an end of the mounting side surface of the semiconductor element;
A bonding material filling space formed between the curved convex surface portion of the entire peripheral portion of the semiconductor element and the surface of the element mounting body;
A semiconductor package component, wherein the bonding material filling space is filled with the bonding material. The bonding material is disposed over the entire peripheral portion of the semiconductor element while in contact with the curved convex surface portion, and has a raised bonding portion having a substantially triangular cross section in the circumferential direction of the semiconductor element,
2. The semiconductor package component according to claim 1, wherein the triangular cross section in the raised joint is a cross section having a divergent shape in each of an inner direction and an outer direction of the semiconductor element.

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