JP2004172296A - Polishing method for semiconductor wafer, and polishing pad therefor - Google Patents

Polishing method for semiconductor wafer, and polishing pad therefor Download PDF

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Publication number
JP2004172296A
JP2004172296A JP2002335617A JP2002335617A JP2004172296A JP 2004172296 A JP2004172296 A JP 2004172296A JP 2002335617 A JP2002335617 A JP 2002335617A JP 2002335617 A JP2002335617 A JP 2002335617A JP 2004172296 A JP2004172296 A JP 2004172296A
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Japan
Prior art keywords
polishing
semiconductor wafer
polishing pad
grooves
traveling direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2002335617A
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Japanese (ja)
Inventor
Eigo Shirakashi
衛吾 白樫
Masashi Hamanaka
雅司 濱中
Fumitaka Itou
史隆 伊藤
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Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002335617A priority Critical patent/JP2004172296A/en
Priority to US10/665,015 priority patent/US20040097174A1/en
Priority to CNA2003101161835A priority patent/CN1503332A/en
Publication of JP2004172296A publication Critical patent/JP2004172296A/en
Pending legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/26—Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B21/00—Machines or devices using grinding or polishing belts; Accessories therefor
    • B24B21/04—Machines or devices using grinding or polishing belts; Accessories therefor for grinding plane surfaces

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To contrive to achieve a desired level of flatness by using a belt type polishing apparatus. <P>SOLUTION: On the surface of a belt-type surface plate 11 wound around two rollers 10 with their rotation axes arranged to be parallel with each other, sheet-shape polishing pads 12 are stuck, each comprising, for instance, four polyurethane sheets. Grooves 12a in each of the polishing pads 12 extend in the same direction as the drive direction of the surface plate 11, but the polishing pads 12 adjacently arranged in the drive direction of the surface plate 11 are stuck apart so that the grooves 12a of one polishing pad 12 are spaced not to be in line with the grooves 12a of the other polishing pads 12. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する分野】
本発明は、半導体ウェーハの研磨方法及び研磨パッドに関し、特に半導体ウェーハに対する化学的機械的研磨装置に用いる複数の溝部を有する研磨パッド及びそれを用いた半導体ウェーハの研磨方法に関する。
【０００２】
【従来の技術】
近年、半導体装置の微細化は著しく、この微細化を実現するために、半導体装置の製造方法についても種々の新しい技術が開発されている。特に、金属配線材料と絶縁材料とからなる配線層を幾層にも積層する多層配線技術は、半導体装置の微細化及び高機能化に大きく貢献できる反面、同時に数多くの技術的な課題を有している。
【０００３】
その課題の１つに、各配線層における平坦性の確保が上げられる。例えば、各配線層の表面に平坦性が確保されずに凹凸が残った状態では、微細化の鍵となるフォトリソグラフィ工程においてフォーカスずれが発生し、配線パターンの形成が不可能となる。この課題を解決するために、近年、半導体ウェーハの表面を化学的機械的に研磨して平坦化するケミカルメカニカルポリッシュ（ＣＭＰ）法が多用されるようになってきている（例えば、特許文献１参照）。
【０００４】
以下、従来のターンテーブル方式ではなく、いわゆるベルト研磨方式のＣＭＰ装置について図面を参照しながら説明する。
【０００５】
図８（ａ）は従来のベルト研磨方式のＣＭＰ装置における研磨機構部の構成を概略的に示している。
【０００６】
図８（ａ）に示すように、基材が発泡ポリウレタンからなる複数のシート状の研磨パッド１０１がベルト状の定盤１０２に貼り付けられており、ノズル１０３から研磨パッド１０１上にスラリ１０４を供給しながら定盤１０２を走行させ、、キャリア１０５に吸着した半導体ウェーハ１０６の表面をキャリア１０５に回転を加えながら押し当てることにより、半導体ウェーハ１０３を研磨する。また、研磨パッド１０１の表面を活性化させる（毛羽立たせる）ために、シリンダ１０７の下面に装着したドレッサ１０８を研磨パッド１０１に押し当てて、定盤１０２の走行方向に対して垂直な方向に随時移動させる。
【０００７】
図８（ｂ）は定盤１０２に貼り付ける前の状態の１枚の研磨パッド１０１を示している。図８（ｂ）に示すように、研磨パッド１０１の表面（研磨面）には直線状で且つ平行に並ぶ複数の溝部１０１ａが形成されている。これらの溝部１０１ａは、半導体ウェーハ１０６を研磨する際に、スラリ１０４を半導体ウェーハ１０１の表面（被研磨面）上に効率良く供給するために設けられており、定盤１０２の走行方向に対して平行に且つ直線状に形成されている。
【０００８】
複数の研磨パッド１０１を定盤１０２の表面に貼り付ける際には、定盤１０２の進行方向に隣接するパッド同士の間にわずかに間隔を空けるようにする。
【０００９】
【特許文献１】
特開平１１−５８２１９号公報
【００１０】
【発明が解決しようとする課題】
本願発明者らは、従来のベルト研磨方式のＣＭＰ装置において以下のような２つの問題点を認めている。
【００１１】
第１の問題点は、図９（ａ）に示すように、それぞれが複数の溝部１０１ａを有する複数の研磨パッド１０１をベルト状の定盤１０２の表面に、進行方向に隣接する研磨パッド１０１同士の溝部１０１ａの位置を一致させるように貼り付ける場合に生じる。
【００１２】
図８（ａ）に示したＣＭＰ装置においては、半導体ウェーハ１０３の研磨を行なう際に、研磨パッド１０１を貼り付けた定盤１０２は、ノズル１０３から遠ざかる方向に所定の速度で走行する。すなわち、研磨パッド１０１の溝部１０１ａは、半導体ウェーハ１０６に対して一定の位置を保ちながら移動する。
【００１３】
一方、半導体ウェーハ１０６を吸着するキャリア１０５は所定の位置で自転するため、半導体ウェーハ１０６の中央部と研磨パッド１０１の中央部分の溝部１０１ａとの位置が一致した場合には、図９（ｂ）に示すように、半導体ウェーハ１０６の被研磨面の中央部に研磨パッド１０１の研磨面と触れない部分が発生する。
【００１４】
また、半導体ウェーハ１０６の研磨パッド１０１による研磨速度は、半導体ウェーハ１０６の被研磨面の中心に近づくにつれて遅くなるため、図１０（ａ）のウェーハポジションと膜厚との関係を示すグラフから分かるように、半導体ウェーハ１０６における被研磨面の中央部の膜厚が周縁部の膜厚よりも大きくなるという、複数の研磨パッド１０１の隔溝部が１０１ａが直線状に連続して配置されたことに起因する膜厚のばらつきが発生する。すなわち、研磨後の半導体ウェーハ１０６の被研磨面には、図１０（ｂ）に示すように、半導体ウェーハ１０６の中心に向かって同心円状にその周囲よりも膜厚が大きい部分が発生するため、半導体ウェーハ１０６の被研磨面に所望の平坦性を得ることができない。この膜厚のばらつきは、前述したように、半導体装置の微細化の鍵となるフォトリソグラフィ工程において、フォーカスずれを発生させるため、配線パターンの形成が不可能となる。
【００１５】
次に、第２の問題点を説明する。
【００１６】
第２の問題点は、図８（ｂ）に示すように、研磨パッド１０１の研磨面に設けられた複数の溝部１０１ａが、研磨パッド１０１の端部にまで設けられていないことにより生じる。このように、溝部１０１ａが研磨パッド１０１の研磨面の端部にまで設けられていないことから、図１１（ａ）の断面図に示すように、ドレッサ１０８の接触面積は、研磨パッド１０１の内側部分Ａがその端部Ｂと比べて小さくなる。これにより、研磨パッド１０１の内側部分Ａにおいては、ドレッサ１０８による単位面積当たりの圧力が端部Ｂと比べて大きくなるため、ドレッサ１０８の圧力差によって、研磨パッド１０１の内側部分Ａの研磨面はその端部Ｂよりも多く削られてしまうので、研磨パッド１０１の内側部分Ａの厚さは端部Ｂと比べて薄くなる。その結果、図１２（ａ）に示すように、研磨パッド１０１はドレッサ１０８によって活性化されるたびにその端部Ｂよりも内側部分Ａが薄くなってしまい、その進行方向に対して垂直な方向の断面形状は凹状となる。このような断面凹状となった研磨パッド１０１を用いて研磨された半導体ウェーハ１０６は、図１２（ｂ）のウェーハポジションと膜厚との関係を示すグラフから分かるように、その周縁部が中央部よりも大きく削られてしまうことになり、所望の平坦性を得ることができない。
【００１７】
前記従来の問題を解決するため、本発明は、ベルト研磨方式の研磨装置を用いて所望の平坦性を得られるようにすることを目的とする。
【００１８】
【課題を解決するための手段】
前記の目的を達成するため、本発明は、半導体ウェーハの研磨方法を、複数の研磨パッドを定盤に貼り付ける際に、進行方向に互いに隣接する研磨パッドにおける溝部同士を揃えない構成とする。また、本発明は、半導体ウェーハの研磨パッドの複数の溝部をその進行方向に対して垂直な方向の端部にまで設ける構成とする。
【００１９】
具体的に、本発明に係る半導体ウェーハの研磨方法は、それぞれがその表面に進行方向に延びる複数の溝部を有する複数の研磨パッドを貼り付けた定盤を連続的に走行させることにより半導体ウェーハを研磨し、定盤の表面に複数の研磨パッドを貼り付ける工程と、定盤を走行させると共に半導体ウェーハを研磨パッドの表面に押し当てながら研磨する工程とを備え、研磨パッドを貼り付ける工程は、各研磨パッドを定盤の走行方向に隣接する研磨パッドの溝部同士が揃わないように貼り付ける。
【００２０】
本発明の半導体ウェーハの研磨方法によると、各研磨パッドを定盤の表面に貼り付ける際に、該定盤の走行方向に隣接する研磨パッドの溝部同士が揃わないように貼り付けるため、研磨中に半導体ウェーハを自転させたとしても、半導体ウェーハの被研磨面と接触する溝部の位置が、貼り付けられた一の研磨パッドから他の研磨パッドに移動するたびに変化する。従って、半導体ウェーハの被研磨面には、同心円状にその周囲よりも膜厚が大きくなるという第１の問題点が解消されるので、所望の平坦性を得ることができる。
【００２１】
本発明の半導体ウェーハの研磨方法において、研磨パッドを貼り付ける工程は、進行方向に隣接する各研磨パッドにおける溝部同士を所定の間隔でずらせて貼り付けることが好ましい。
【００２２】
本発明の半導体ウェーハの研磨方法において、半導体ウェーハの研磨工程は、研磨パッドの表面に研磨材を含むスラリを流しながら半導体ウェーハを研磨することが好ましい。
【００２３】
本発明に係る第１の半導体ウェーハの研磨パッドは、ベルト状の定盤の表面に貼り付ける半導体ウェーハの研磨パッドを対象とし、研磨パッドの表面には、研磨パッドの進行方向に延びる複数の溝部がその進行方向に対して垂直な方向側の端部にまで形成されている。
【００２４】
第１の半導体ウェーハの研磨パッドによると、研磨パッドの表面には、研磨パッドの進行方向に延びる複数の溝部がその進行方向に対して垂直な方向側の端部にまで形成されているため、研磨中にドレッサによる研磨パッドの活性化を行なったとしても、ドレッサと研磨パッドとの接触面積が研磨パッドの端部と内側部分とで異ならなくなる。このため、ドレッサによる単位面積当たりの圧力が端部と内側部分とで同等となるので、活性化を続行したとしても、研磨パッドの進行方向に対して垂直な方向の断面形状が凹状とはならなくなる。その結果、半導体ウェーハの被研磨面の端部のみがより大きく削られるという第２の問題点が解消されるので、所望の平坦性を得ることができる。
【００２５】
本発明に係る第２の半導体ウェーハの研磨パッドは、ベルト状の定盤の表面に貼り付ける半導体ウェーハの研磨パッドを対象とし、研磨パッドの表面には、研磨パッドの進行方向に延びる複数の溝部がその進行方向に対して斜めとなるように形成されている。
【００２６】
第２の半導体ウェーハの研磨パッドによると、研磨パッドの表面には、研磨パッドの進行方向に延びる複数の溝部がその進行方向に対して斜めとなるように形成されているため、研磨中に半導体ウェーハを自転させたとしても、半導体ウェーハの被研磨面と接触する溝部の位置が、一の研磨パッドにおいてもそれが進行するたびに移動して変化する。従って、半導体ウェーハの被研磨面には、同心円状にその周囲よりも膜厚が大きくなるという第１の問題点が解消されるので、所望の平坦性を得ることができる。
【００２７】
本発明の第１又は第２の半導体ウェーハの研磨パッドにおいて、複数の溝部は互いの間隔が均等となるように形成されていることが好ましい。このようにすると、研磨時における半導体ウェーハの被研磨面と研磨パッドの研磨面との接触時間を均一にすることができるため、研磨後の半導体ウェーハの被研磨面はより一層平坦化される。
【００２８】
また、本発明の第１又は第２の半導体ウェーハの研磨パッドにおいて、研磨パッドは発泡ポリウレタンからなることが好ましい。
【００２９】
【発明の実施の形態】
（第１の実施形態）
本発明の第１の実施形態について図面を参照しながら説明する。
【００３０】
図１（ａ）は本発明の第１の実施形態に係るベルト研磨方式のＣＭＰ装置における研磨機構部の構成を概略的に示している。
【００３１】
図１（ａ）に示すように、互いの回転軸が平行に配置された２つのローラ（プーリ）１０に懸けられたベルト状の定盤１１の表面上には、例えば基材がポリウレタンからなる４枚のシート状の研磨パッド１２が貼り付けられている。ここで、研磨パッド１２の基材として用いるポリウレタンは独立発泡ポリウレタンが好ましい。
【００３２】
キャリア１３に吸着された半導体ウェーハ２０を研磨するには、定盤１１を所定の方向に走行させ、研磨パッド１２の表面（研磨面）上にノズル１４から研磨材を含むスラリ１５を供給し、半導体ウェーハ２０の表面（被研磨面）を研磨パッド１２の表面に回転を加えながら押し当てる。また、研磨パッド１２の表面を活性化させるために、シリンダ１６の下面に装着したドレッサ１７を研磨パッド１２に押し当てて、定盤１１の走行方向に対して垂直な方向に随時移動させる。
【００３３】
図１（ｂ）の拡大平面図に示すように、第１の実施形態に係る研磨パッド１２は、そのいずれもが溝部１２ａの延伸方向を定盤１１の走行方向と合わせると共に、該定盤１１の走行方向に隣接する研磨パッド１２同士は、互いに間隔をおき且つ互いの溝部１２ａが揃わないように貼り付けられている。なお、この溝部１２ａは、スラリ１５を半導体ウェーハ２０の表面上に効率良く供給するために設けられている。
【００３４】
このように、進行方向に互いに隣接する各研磨パッド１２は、互いの溝部１２ａ同士が揃わないように貼り付けられているため、図２（ａ）に示すように、研磨開始直後において半導体ウェーハ２０の中心位置が、一の研磨パッド１２に形成された実線で示す溝部１２ａによって研磨されない状態となったとしても、該一の研磨パッド１２に続く他の研磨パッド１２に形成された破線で示す溝部１２ａの位置は一の研磨パッド１２の溝部１２ａとずれているため、半導体ウェーハ２０が自転していても、研磨パッド１２の研磨面は、半導体ウェーハ２０の被研磨面と確実に接触するので、半導体ウェーハ２０の被研磨面の中央部の未研磨部分をなくすことがができる。
【００３５】
なお、ベルト状の定盤１１に貼り付ける研磨パッド１２の枚数には制限はないが、第１の実施形態においては、４枚の研磨パッド１２のそれぞれの隣接間で各溝部１２ａの幅の２分の１のピッチでずらせながら貼り付けている。このようにすると、半導体ウェーハ２０における研磨パッド１２の溝部１２ａによって研磨されない時間をも均等化できるため、図２（ｂ）に示すように、半導体ウェーハ２０の中央部の未研磨部分がなくなって、半導体ウェーハ２０の被研磨面を全面にわたって均一に研磨することができる。
【００３６】
（第２の実施形態）
以下、本発明の第２の実施形態について図面を参照しながら説明する。
【００３７】
図３は本発明の第２の実施形態に係るベルト研磨方式のＣＭＰ装置に用いる研磨パッドを示している。
【００３８】
図３に示すように、第２の実施形態に係る研磨パッド１２には、その研磨面に設けられ、進行方向に互いに平行に延びる複数の溝部１２ａが、研磨パッド１２の進行方向に対して垂直な方向の端部にまで形成されている。
【００３９】
これにより、半導体ウェーハを研磨する際には、図４（ａ）の断面図に示すように、研磨パッド１２の研磨面におけるドレッサ１７との接触面積が、研磨パッド１２の内側部分Ａとその端部Ｂとで均一化されるため、ドレッサ１７による活性化が研磨パッド１２の研磨面の全面にわたって均一に行なえる。その結果、活性化時に研磨パッド１２の内側部分Ａのみがドレッサ１７によって大きく削られることがなくなるので、図２（ｂ）に示すように、半導体ウェーハの周縁部の膜厚が中央部よりも薄くなることがなく、半導体ウェーハの被研磨面の全面にわたって均一に研磨を行なうことができる。
【００４０】
なお、図４（ｂ）に示すように、その進行方向に隣接する研磨パッド１２を、その溝部１２ａ同士が揃わないように貼り付けることにより、第１の実施形態と同様に、半導体ウェーハの中央部の膜厚がその周囲よりも厚くなることをも防止することができる。
【００４１】
（第３の実施形態）
以下、本発明の第３の実施形態について図面を参照しながら説明する。
【００４２】
図５（ａ）は本発明の第３の実施形態に係るベルト研磨方式のＣＭＰ装置に用いる研磨パッドを示している。
【００４３】
図５（ａ）に示すように、第３の実施形態に係る研磨パッド１２は、その進行方向に互いに平行に延びる複数の溝部１２ｂに、研磨パッド１２の進行方向に対して所定の角度θを持たせている。所定の角度θは、ノズルから研磨パッド１２上に吐出されるスラリを半導体ウェーハにまで効率良く供給するという溝部本来の機能を損なわない程度とし、例えば１°〜１５°程度が好ましい。研磨パッド１２における複数の溝部１２ｂを形成する範囲は、該研磨パッド１２の進行方向に対して垂直な方向の端部にまで形成する。また、複数の研磨パッド１２を定盤１１の表面に貼り付ける場合には、図５（ｂ）の拡大平面図に示すように、進行方向に互いに隣接する研磨パッド１２同士の間に隙間を設けるようにする。
【００４４】
このように、第３の実施形態に係る研磨パッド１２を用いて半導体ウェーハの研磨を行なうと、図６のウェーハ中央部のポジションと膜厚との関係を示すグラフから分かるように、半導体ウェーハの中央部分に研磨されていない部分がなくなると共に、半導体ウェーハに周縁部が薄くなることもなくなり、従って、半導体ウェーハにはその被研磨の全面にわたって均一な膜厚を得ることができる。
【００４５】
（第３の実施形態の一変形例）
図７に示すように、複数の研磨パッド１２を定盤１１の表面に貼り付ける場合には、一の研磨パッド１２における溝部１２ｂの進行方向からずれる方向と、それと隣接する他の研磨パッド１２における溝部１２ｂの進行方向からずれる方向とを交互に入れ換えて、溝部１２ｂを千鳥状に配置すると、半導体ウェーハの被研磨面の平坦性がより向上する。
【００４６】
【発明の効果】
本発明に係る半導体ウェーハの研磨方法によると、研磨中に半導体ウェーハを自転させたとしても、半導体ウェーハの被研磨面と接触する溝部の位置が、貼り付けられた一の研磨パッドから他の研磨パッドに移動するたびに変化するため、半導体ウェーハの被研磨面に同心円状にその周囲よりも膜厚が大きくなるという膜厚のばらつきが解消されるので、所望の平坦性を得ることができる。
【００４７】
本発明に係る半導体ウェーハの研磨パッドによると、研磨中にドレッサによる研磨パッドの活性化を行なったとしても、ドレッサと研磨パッドとの接触面積が研磨パッドの端部と内側部分とで異ならなくなるため、研磨パッドの進行方向に対して垂直な方向の断面形状が凹状にならなくなる。その結果、半導体ウェーハの被研磨面の端部のみがより大きく削られるという膜厚のばらつきがなくなるので、所望の平坦性を得ることができる。
【図面の簡単な説明】
【図１】（ａ）及び（ｂ）は本発明の第１の実施形態に係る半導体ウェーハの研磨方法を実現するベルト研磨方式のＣＭＰ装置を示し、（ａ）は研磨機構部を示す概略的な斜視図であり、（ｂ）は研磨パッドの定盤に貼り付けられた状態を示す部分的な平面図である。
【図２】（ａ）は本発明の第１の実施形態に係る半導体ウェーハの研磨方法であって、研磨パッドが半導体ウェーハと接触する様子を示す断面図である。
（ｂ）は本発明の第１の実施形態に係る半導体ウェーハの研磨方法によるウェーハのポジションと膜厚との関係を示すグラフである。
【図３】本発明の第２の実施形態に係るベルト研磨方式のＣＭＰ装置に用いる研磨パッドを示す斜視図である。
【図４】（ａ）は本発明の第２の実施形態に係る半導体ウェーハの研磨パッドがドレッサと接触する様子を示す断面図である。
（ｂ）は本発明の第２の実施形態に係る半導体ウェーハの研磨パッドを示す部分的な平面図である。
【図５】（ａ）は本発明の第３の実施形態に係る半導体ウェーハの研磨パッドの定盤上に貼り付けられた状態を示す部分的な斜視図である。
（ｂ）は本発明の第３の実施形態に係る半導体ウェーハの研磨パッドの定盤上に貼り付けられた状態を示す部分的な平面図である。
【図６】本発明の第３の実施形態に係る半導体ウェーハの研磨方法によるウェーハのポジションと膜厚との関係を示すグラフである。
【図７】本発明の第３の実施形態の一変形例に係る半導体ウェーハの研磨パッドの定盤上に貼り付けられた状態を示す部分的な平面図である。
【図８】（ａ）及び（ｂ）は従来のベルト研磨方式のＣＭＰ装置を示し、（ａ）は研磨機構部を示す概略的な斜視図であり、（ｂ）は研磨パッドを示す斜視図である。
【図９】（ａ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドの定盤上に貼り付けられた状態を示す部分的な平面図である。
（ｂ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドの半導体ウェーハと接触する様子を示す断面図である。
【図１０】（ａ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドを用いた場合のウェーハのポジションと膜厚との関係を示すグラフである。
（ｂ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドを用いた場合の半導体ウェーハの被研磨面を示す平面図である。
【図１１】（ａ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドのドレッサと接触する様子を示す断面図であり、（ｂ）はドレッサによる活性化処理を継続して行なった場合を示す断面図である。
【図１２】（ａ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドにドレッサによる活性化を継続して行なった場合の研磨パッドと半導体ウェーハとの断面図である。
（ｂ）は従来のベルト研磨方式のＣＭＰ装置における研磨パッドにドレッサによる活性化を継続して行なった場合のウェーハのポジションと膜厚との関係を示すグラフである。
【符号の説明】
１０ ローラ（プーリ）
１１ 定盤
１２ 研磨パッド
１２ａ 溝部
１２ｂ 溝部
１３ キャリア
１４ ノズル
１５ スラリ
１６ シリンダ
１７ ドレッサ
２０ 半導体ウェーハ[0001]
[Field of the Invention]
The present invention relates to a polishing method and a polishing pad for a semiconductor wafer, and more particularly to a polishing pad having a plurality of grooves used in a chemical mechanical polishing apparatus for a semiconductor wafer and a method for polishing a semiconductor wafer using the same.
[0002]
[Prior art]
In recent years, the miniaturization of semiconductor devices has been remarkable, and in order to realize the miniaturization, various new techniques have also been developed for semiconductor device manufacturing methods. In particular, the multilayer wiring technology of laminating wiring layers composed of a metal wiring material and an insulating material as many as possible can greatly contribute to miniaturization and high performance of a semiconductor device, but also has many technical problems at the same time. ing.
[0003]
One of the problems is to ensure the flatness of each wiring layer. For example, when unevenness remains without ensuring flatness on the surface of each wiring layer, a focus shift occurs in a photolithography process that is a key to miniaturization, and a wiring pattern cannot be formed. In order to solve this problem, in recent years, a chemical mechanical polishing (CMP) method for polishing and flattening the surface of a semiconductor wafer chemically and mechanically has been widely used (for example, see Patent Document 1). ).
[0004]
Hereinafter, a so-called belt polishing type CMP apparatus, not a conventional turntable type, will be described with reference to the drawings.
[0005]
FIG. 8A schematically shows the configuration of a polishing mechanism in a conventional belt polishing type CMP apparatus.
[0006]
As shown in FIG. 8A, a plurality of sheet-like polishing pads 101 whose base material is made of foamed polyurethane are attached to a belt-like platen 102, and a slurry 104 is placed on the polishing pad 101 from a nozzle 103. The platen 102 is run while being supplied, and the surface of the semiconductor wafer 106 adsorbed on the carrier 105 is pressed against the carrier 105 while rotating, so that the semiconductor wafer 103 is polished. Further, in order to activate (fuzz) the surface of the polishing pad 101, a dresser 108 mounted on the lower surface of the cylinder 107 is pressed against the polishing pad 101, and is optionally moved in a direction perpendicular to the traveling direction of the surface plate 102. Move.
[0007]
FIG. 8B shows one polishing pad 101 before being attached to the surface plate 102. As shown in FIG. 8B, a plurality of grooves 101a that are linear and arranged in parallel are formed on the surface (polishing surface) of the polishing pad 101. These grooves 101a are provided for efficiently supplying the slurry 104 onto the surface (polished surface) of the semiconductor wafer 101 when the semiconductor wafer 106 is polished. They are formed in parallel and linearly.
[0008]
When a plurality of polishing pads 101 are attached to the surface of the surface plate 102, a slight space is provided between pads adjacent to each other in the traveling direction of the surface plate 102.
[0009]
[Patent Document 1]
JP-A-11-58219
[Problems to be solved by the invention]
The present inventors have recognized the following two problems in a conventional belt polishing type CMP apparatus.
[0011]
A first problem is that, as shown in FIG. 9A, a plurality of polishing pads 101 each having a plurality of grooves 101a are formed on a surface of a belt-like platen 102 by polishing pads 101 adjacent to each other in the traveling direction. This occurs when sticking is performed so that the positions of the groove portions 101a coincide with each other.
[0012]
In the CMP apparatus shown in FIG. 8A, when polishing the semiconductor wafer 103, the platen 102 to which the polishing pad 101 is attached travels at a predetermined speed in a direction away from the nozzle 103. That is, the groove 101a of the polishing pad 101 moves while maintaining a constant position with respect to the semiconductor wafer 106.
[0013]
On the other hand, since the carrier 105 that adsorbs the semiconductor wafer 106 rotates at a predetermined position, if the center of the semiconductor wafer 106 and the groove 101a at the center of the polishing pad 101 coincide with each other, FIG. As shown in (1), a portion that does not touch the polished surface of the polishing pad 101 occurs at the center of the polished surface of the semiconductor wafer 106.
[0014]
Also, the polishing rate of the semiconductor wafer 106 by the polishing pad 101 becomes slower as it approaches the center of the surface to be polished of the semiconductor wafer 106, and thus can be seen from the graph showing the relationship between the wafer position and the film thickness in FIG. In addition, the thickness of the central portion of the surface to be polished in the semiconductor wafer 106 is larger than the thickness of the peripheral portion. This is because the separation grooves 101a of the plurality of polishing pads 101 are arranged linearly and continuously. The resulting film thickness varies. That is, as shown in FIG. 10B, a portion having a larger film thickness than the periphery thereof is formed concentrically toward the center of the semiconductor wafer 106 on the polished surface of the semiconductor wafer 106 after polishing. The desired flatness cannot be obtained on the surface to be polished of the semiconductor wafer 106. As described above, this variation in film thickness causes a focus shift in a photolithography process, which is a key to miniaturization of a semiconductor device, so that a wiring pattern cannot be formed.
[0015]
Next, a second problem will be described.
[0016]
The second problem arises because the plurality of grooves 101a provided on the polishing surface of the polishing pad 101 are not provided up to the end of the polishing pad 101 as shown in FIG. As described above, since the groove 101a is not provided up to the end of the polishing surface of the polishing pad 101, as shown in the cross-sectional view of FIG. Part A is smaller than end B thereof. Accordingly, in the inner portion A of the polishing pad 101, the pressure per unit area by the dresser 108 is larger than that at the end portion B, and the polishing surface of the inner portion A of the polishing pad 101 is reduced by the pressure difference of the dresser 108. Since the inner portion A of the polishing pad 101 is thinner than the end portion B, the thickness is smaller than the end portion B. As a result, as shown in FIG. 12A, each time the polishing pad 101 is activated by the dresser 108, the inner portion A becomes thinner than the end portion B, and the polishing pad 101 in the direction perpendicular to the traveling direction is The cross-sectional shape is concave. As can be seen from the graph showing the relationship between the wafer position and the film thickness in FIG. 12B, the semiconductor wafer 106 polished using the polishing pad 101 having such a concave cross section has its peripheral portion at the center. Therefore, the desired flatness cannot be obtained.
[0017]
In order to solve the above-mentioned conventional problems, an object of the present invention is to obtain a desired flatness using a polishing apparatus of a belt polishing type.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method for polishing a semiconductor wafer, in which, when a plurality of polishing pads are attached to a surface plate, grooves in polishing pads adjacent to each other in a traveling direction are not aligned. In addition, the present invention has a configuration in which a plurality of grooves of a polishing pad of a semiconductor wafer are provided up to an end in a direction perpendicular to the traveling direction.
[0019]
Specifically, the method of polishing a semiconductor wafer according to the present invention, the semiconductor wafer by continuously running a platen having a plurality of polishing pads each having a plurality of grooves extending in the traveling direction on the surface thereof. Polishing, a step of pasting a plurality of polishing pads on the surface of the surface plate, and a step of polishing while pressing the semiconductor wafer against the surface of the polishing pad while running the surface plate, the step of pasting the polishing pad, The polishing pads are attached so that the grooves of the polishing pads adjacent to each other in the running direction of the surface plate are not aligned.
[0020]
According to the method for polishing a semiconductor wafer of the present invention, when each polishing pad is attached to the surface of the surface plate, because the grooves of the polishing pads adjacent to each other in the running direction of the surface plate are not aligned, during polishing. Even if the semiconductor wafer is rotated on its own, the position of the groove in contact with the surface to be polished of the semiconductor wafer changes each time it moves from one attached polishing pad to another. Therefore, the first problem that the thickness of the surface to be polished of the semiconductor wafer becomes concentrically larger than that of the periphery thereof is eliminated, and desired flatness can be obtained.
[0021]
In the semiconductor wafer polishing method of the present invention, in the step of attaching the polishing pad, it is preferable that the grooves of the adjacent polishing pads in the advancing direction are shifted from each other at a predetermined interval.
[0022]
In the method of polishing a semiconductor wafer according to the present invention, in the polishing step of the semiconductor wafer, it is preferable that the semiconductor wafer is polished while flowing a slurry containing an abrasive on the surface of the polishing pad.
[0023]
The polishing pad of the first semiconductor wafer according to the present invention is intended for a polishing pad of a semiconductor wafer to be attached to a surface of a belt-like surface plate, and has a plurality of grooves extending in the direction of movement of the polishing pad on the surface of the polishing pad. Is formed up to the end on the side perpendicular to the traveling direction.
[0024]
According to the polishing pad of the first semiconductor wafer, on the surface of the polishing pad, a plurality of grooves extending in the traveling direction of the polishing pad are formed up to the end in the direction perpendicular to the traveling direction, Even if the polishing pad is activated by the dresser during polishing, the contact area between the dresser and the polishing pad does not differ between the end portion and the inside portion of the polishing pad. For this reason, the pressure per unit area by the dresser becomes equal between the end portion and the inside portion, so that even if activation is continued, the cross-sectional shape in the direction perpendicular to the direction of travel of the polishing pad is not concave. Disappears. As a result, the second problem that only the end portion of the polished surface of the semiconductor wafer is sharpened is solved, and desired flatness can be obtained.
[0025]
The polishing pad of the second semiconductor wafer according to the present invention is intended for a polishing pad of a semiconductor wafer to be attached to a surface of a belt-like surface plate, and a plurality of grooves extending in the direction of movement of the polishing pad on the surface of the polishing pad. Are formed so as to be oblique to the traveling direction.
[0026]
According to the polishing pad of the second semiconductor wafer, a plurality of grooves extending in the traveling direction of the polishing pad are formed on the surface of the polishing pad so as to be inclined with respect to the traveling direction. Even if the wafer is rotated, the position of the groove in contact with the surface to be polished of the semiconductor wafer moves and changes as one polishing pad advances. Therefore, the first problem that the thickness of the surface to be polished of the semiconductor wafer becomes concentrically larger than that of the periphery thereof is eliminated, and desired flatness can be obtained.
[0027]
In the polishing pad of the first or second semiconductor wafer of the present invention, it is preferable that the plurality of grooves are formed so that the intervals between them are equal. By doing so, the contact time between the polished surface of the semiconductor wafer and the polished surface of the polishing pad during polishing can be made uniform, so that the polished surface of the polished semiconductor wafer is further flattened.
[0028]
Further, in the polishing pad for the first or second semiconductor wafer of the present invention, the polishing pad is preferably made of foamed polyurethane.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
[0030]
FIG. 1A schematically shows a configuration of a polishing mechanism in a belt polishing type CMP apparatus according to a first embodiment of the present invention.
[0031]
As shown in FIG. 1A, on a surface of a belt-like surface plate 11 suspended by two rollers (pulleys) 10 whose rotation axes are arranged in parallel, for example, a base material is made of polyurethane. Four sheet-like polishing pads 12 are attached. Here, the polyurethane used as the base material of the polishing pad 12 is preferably a closed-cell polyurethane.
[0032]
To polish the semiconductor wafer 20 adsorbed on the carrier 13, the platen 11 is moved in a predetermined direction, and a slurry 15 containing an abrasive is supplied from a nozzle 14 onto the surface (polishing surface) of the polishing pad 12. The surface (polished surface) of the semiconductor wafer 20 is pressed against the surface of the polishing pad 12 while rotating. Further, in order to activate the surface of the polishing pad 12, a dresser 17 mounted on the lower surface of the cylinder 16 is pressed against the polishing pad 12 and is moved at any time in a direction perpendicular to the traveling direction of the surface plate 11.
[0033]
As shown in the enlarged plan view of FIG. 1B, the polishing pad 12 according to the first embodiment is configured such that the extending direction of the groove 12 a matches the running direction of the surface plate 11, The polishing pads 12 adjacent to each other in the traveling direction are attached so as to be spaced from each other and the grooves 12a are not aligned. The groove 12a is provided for efficiently supplying the slurry 15 onto the surface of the semiconductor wafer 20.
[0034]
As described above, the polishing pads 12 that are adjacent to each other in the traveling direction are attached so that the grooves 12a are not aligned with each other. Therefore, as shown in FIG. Is not polished by the groove 12a indicated by a solid line formed on one polishing pad 12, the groove indicated by a broken line formed on another polishing pad 12 subsequent to the one polishing pad 12. Since the position of 12 a is shifted from the groove 12 a of one polishing pad 12, even if the semiconductor wafer 20 rotates, the polished surface of the polishing pad 12 surely contacts the polished surface of the semiconductor wafer 20, The unpolished portion at the center of the polished surface of the semiconductor wafer 20 can be eliminated.
[0035]
The number of the polishing pads 12 to be attached to the belt-shaped surface plate 11 is not limited. However, in the first embodiment, the width of each groove 12a between two adjacent polishing pads 12 is two times. It is pasted while shifting at a pitch of 1 /. In this manner, the time during which the semiconductor wafer 20 is not polished by the grooves 12a of the polishing pad 12 can be equalized, and as shown in FIG. 2B, the unpolished portion at the center of the semiconductor wafer 20 is eliminated. The surface to be polished of the semiconductor wafer 20 can be uniformly polished over the entire surface.
[0036]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0037]
FIG. 3 shows a polishing pad used in a belt polishing type CMP apparatus according to a second embodiment of the present invention.
[0038]
As shown in FIG. 3, the polishing pad 12 according to the second embodiment has a plurality of grooves 12 a provided on the polishing surface thereof and extending in parallel with each other in the traveling direction, perpendicular to the traveling direction of the polishing pad 12. It is formed up to the end in a different direction.
[0039]
Thereby, when polishing the semiconductor wafer, as shown in the cross-sectional view of FIG. 4A, the contact area between the polishing surface of the polishing pad 12 and the dresser 17 is changed between the inner portion A of the polishing pad 12 and the end thereof. Since the polishing pad 12 is made uniform, the activation by the dresser 17 can be performed uniformly over the entire polishing surface of the polishing pad 12. As a result, only the inner portion A of the polishing pad 12 is not largely shaved by the dresser 17 during activation, and as shown in FIG. 2B, the thickness of the peripheral portion of the semiconductor wafer is smaller than that of the central portion. The polishing can be performed uniformly over the entire surface to be polished of the semiconductor wafer.
[0040]
As shown in FIG. 4 (b), the polishing pads 12 adjacent in the traveling direction are attached so that the grooves 12a are not aligned with each other, so that the center of the semiconductor wafer is formed in the same manner as in the first embodiment. It is also possible to prevent the thickness of the part from being greater than its surroundings.
[0041]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
[0042]
FIG. 5A shows a polishing pad used in a belt polishing type CMP apparatus according to a third embodiment of the present invention.
[0043]
As shown in FIG. 5A, the polishing pad 12 according to the third embodiment has a plurality of grooves 12 b extending parallel to each other in a direction in which the polishing pad 12 travels at a predetermined angle θ with respect to the traveling direction of the polishing pad 12. I have it. The predetermined angle θ is such that the original function of the groove portion for efficiently supplying the slurry discharged from the nozzle onto the polishing pad 12 to the semiconductor wafer is not impaired, and is preferably, for example, about 1 ° to 15 °. The range in which the plurality of grooves 12b are formed in the polishing pad 12 is formed up to the end in the direction perpendicular to the traveling direction of the polishing pad 12. When a plurality of polishing pads 12 are attached to the surface of the surface plate 11, a gap is provided between the polishing pads 12 adjacent to each other in the traveling direction, as shown in an enlarged plan view of FIG. To do.
[0044]
As described above, when the semiconductor wafer is polished using the polishing pad 12 according to the third embodiment, as can be seen from the graph showing the relationship between the position of the central portion of the wafer and the film thickness in FIG. There is no unpolished portion in the center portion, and the peripheral portion of the semiconductor wafer does not become thin. Therefore, a uniform film thickness can be obtained on the entire surface of the semiconductor wafer to be polished.
[0045]
(Modification of Third Embodiment)
As shown in FIG. 7, when a plurality of polishing pads 12 are attached to the surface of the surface plate 11, a direction deviating from a traveling direction of the groove 12 b in one polishing pad 12 and a direction in another polishing pad 12 adjacent thereto are different. If the directions deviating from the traveling direction of the grooves 12b are alternately switched, and the grooves 12b are arranged in a staggered manner, the flatness of the polished surface of the semiconductor wafer is further improved.
[0046]
【The invention's effect】
According to the method for polishing a semiconductor wafer according to the present invention, even if the semiconductor wafer is rotated during polishing, the position of the groove portion in contact with the surface to be polished of the semiconductor wafer is changed from one bonded polishing pad to another. Since the thickness changes each time the semiconductor wafer moves to the pad, the variation in the film thickness, that is, the film thickness increases concentrically with the surface to be polished of the semiconductor wafer and its surroundings is eliminated, so that desired flatness can be obtained.
[0047]
According to the polishing pad of the semiconductor wafer according to the present invention, even if the polishing pad is activated by the dresser during polishing, the contact area between the dresser and the polishing pad does not differ between the end portion and the inner portion of the polishing pad. In addition, the cross section in the direction perpendicular to the direction of travel of the polishing pad does not become concave. As a result, there is no variation in the film thickness such that only the end of the polished surface of the semiconductor wafer is sharpened, so that desired flatness can be obtained.
[Brief description of the drawings]
FIGS. 1A and 1B show a belt polishing type CMP apparatus for realizing a semiconductor wafer polishing method according to a first embodiment of the present invention, and FIG. 1A is a schematic view showing a polishing mechanism; FIG. 2B is a partial perspective view showing a state in which the polishing pad is attached to a surface plate of a polishing pad.
FIG. 2A is a cross-sectional view illustrating a method of polishing a semiconductor wafer according to a first embodiment of the present invention, showing a state in which a polishing pad contacts a semiconductor wafer.
(B) is a graph showing the relationship between the wafer position and the film thickness by the semiconductor wafer polishing method according to the first embodiment of the present invention.
FIG. 3 is a perspective view showing a polishing pad used in a belt polishing type CMP apparatus according to a second embodiment of the present invention.
FIG. 4A is a cross-sectional view showing a state where a polishing pad of a semiconductor wafer contacts a dresser according to a second embodiment of the present invention.
(B) is a partial plan view showing a polishing pad for a semiconductor wafer according to the second embodiment of the present invention.
FIG. 5A is a partial perspective view showing a state in which a semiconductor wafer according to a third embodiment of the present invention is attached to a polishing pad surface plate.
(B) is a partial plan view showing a semiconductor wafer according to a third embodiment of the present invention attached to a polishing pad surface plate.
FIG. 6 is a graph showing a relationship between a wafer position and a film thickness by a semiconductor wafer polishing method according to a third embodiment of the present invention.
FIG. 7 is a partial plan view showing a state in which a semiconductor wafer is attached on a surface plate of a polishing pad according to a modification of the third embodiment of the present invention.
8A and 8B show a conventional belt polishing type CMP apparatus, FIG. 8A is a schematic perspective view showing a polishing mechanism, and FIG. 8B is a perspective view showing a polishing pad. It is.
FIG. 9A is a partial plan view showing a state in which a polishing pad is pasted on a surface plate of a conventional belt polishing type CMP apparatus.
FIG. 2B is a cross-sectional view illustrating a state in which a polishing pad contacts a semiconductor wafer in a conventional belt polishing type CMP apparatus.
FIG. 10A is a graph showing a relationship between a wafer position and a film thickness when a polishing pad is used in a conventional belt polishing type CMP apparatus.
(B) is a plan view showing a polished surface of a semiconductor wafer when a polishing pad is used in a conventional belt polishing type CMP apparatus.
FIG. 11A is a cross-sectional view showing a state in which a polishing pad comes into contact with a dresser in a conventional belt polishing type CMP apparatus, and FIG. 11B shows a case where activation processing by the dresser is continuously performed. It is sectional drawing.
FIG. 12A is a cross-sectional view of a polishing pad and a semiconductor wafer when a polishing pad in a conventional belt polishing type CMP apparatus is continuously activated by a dresser.
(B) is a graph showing a relationship between a wafer position and a film thickness when a polishing pad in a conventional belt polishing type CMP apparatus is continuously activated by a dresser.
[Explanation of symbols]
10 Rollers (Pulley)
11 surface plate 12 polishing pad 12a groove 12b groove 13 carrier 14 nozzle 15 slurry 16 cylinder 17 dresser 20 semiconductor wafer

Claims (7)

それぞれがその表面に進行方向に延びる複数の溝部を有する複数の研磨パッドを貼り付けた定盤を連続的に走行させることにより半導体ウェーハを研磨する半導体ウェーハの研磨方法であって、
前記定盤の表面に前記複数の研磨パッドを貼り付ける工程と、
前記定盤を走行させると共に前記半導体ウェーハを前記研磨パッドの表面に押し当てながら研磨する工程とを備え、
前記研磨パッドを貼り付ける工程は、前記各研磨パッドを前記定盤の走行方向に隣接する研磨パッドの溝部同士が揃わないように貼り付けることを特徴とする半導体ウェーハの研磨方法。A semiconductor wafer polishing method for polishing a semiconductor wafer by continuously running a platen having a plurality of polishing pads each having a plurality of grooves extending in a traveling direction on the surface thereof,
Affixing the plurality of polishing pads on the surface of the surface plate,
Polishing the semiconductor wafer while pressing the semiconductor wafer against the surface of the polishing pad while running the surface plate,
The method of polishing a semiconductor wafer according to claim 1, wherein the step of attaching the polishing pad includes attaching the polishing pads such that grooves of the polishing pads adjacent to each other in the traveling direction of the surface plate are not aligned. 前記研磨パッドを貼り付ける工程は、前記進行方向に隣接する各研磨パッドにおける前記溝部同士を所定の間隔でずらせて貼り付けることを特徴とする請求項１に記載の半導体ウェーハの研磨方法。2. The method according to claim 1, wherein, in the step of attaching the polishing pad, the grooves in the adjacent polishing pads in the traveling direction are attached at a predetermined interval. 3. 前記半導体ウェーハの研磨工程は、前記研磨パッドの表面に研磨材を含むスラリを流しながら前記半導体ウェーハを研磨することを特徴とする請求項１又は２に記載の半導体ウェーハの研磨方法。The method for polishing a semiconductor wafer according to claim 1, wherein in the polishing step of the semiconductor wafer, the semiconductor wafer is polished while flowing a slurry containing an abrasive on the surface of the polishing pad. ベルト状の定盤の表面に貼り付ける半導体ウェーハの研磨パッドであって、
前記研磨パッドの表面には、前記研磨パッドの進行方向に延びる複数の溝部が、前記進行方向に対して垂直な方向側の端部にまで形成されていることを特徴とする半導体ウェーハの研磨パッド。A polishing pad for a semiconductor wafer to be attached to a surface of a belt-like surface plate,
A plurality of grooves extending in a direction in which the polishing pad travels are formed on a surface of the polishing pad up to an end portion in a direction perpendicular to the traveling direction, and the polishing pad for a semiconductor wafer is provided. . ベルト状の定盤の表面に貼り付ける半導体ウェーハの研磨パッドであって、
前記研磨パッドの表面には、前記研磨パッドの進行方向に延びる複数の溝部が、前記進行方向に対して斜めとなるように形成されていることを特徴とする半導体ウェーハの研磨パッド。A polishing pad for a semiconductor wafer to be attached to a surface of a belt-like surface plate,
A polishing pad for a semiconductor wafer, wherein a plurality of grooves extending in a traveling direction of the polishing pad are formed on a surface of the polishing pad so as to be oblique to the traveling direction. 前記複数の溝部は、互いの間隔が均等となるように形成されていることを特徴とする請求項４又は５に記載の半導体ウェーハの研磨パッド。The polishing pad for a semiconductor wafer according to claim 4, wherein the plurality of grooves are formed so as to be evenly spaced from each other. 前記研磨パッドは発泡ポリウレタンからなることを特徴とする請求項４又は５に記載の半導体ウェーハの研磨パッド。The polishing pad for a semiconductor wafer according to claim 4, wherein the polishing pad is made of foamed polyurethane.
JP2002335617A 2002-11-19 2002-11-19 Polishing method for semiconductor wafer, and polishing pad therefor Pending JP2004172296A (en)

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