JP2004172238A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2004172238A
JP2004172238A JP2002334304A JP2002334304A JP2004172238A JP 2004172238 A JP2004172238 A JP 2004172238A JP 2002334304 A JP2002334304 A JP 2002334304A JP 2002334304 A JP2002334304 A JP 2002334304A JP 2004172238 A JP2004172238 A JP 2004172238A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrodes
wiring board
manufacturing
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002334304A
Other languages
Japanese (ja)
Other versions
JP4055556B2 (en
Inventor
Kozo Shimizu
浩三 清水
Masayuki Ochiai
正行 落合
Seiki Sakuyama
誠樹 作山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2002334304A priority Critical patent/JP4055556B2/en
Publication of JP2004172238A publication Critical patent/JP2004172238A/en
Application granted granted Critical
Publication of JP4055556B2 publication Critical patent/JP4055556B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device wherein a semiconductor element and a circuit wiring board, both of which have many fine electrodes arranged at a narrow pitch, are bonded to each other by flip chip bonding using solder bumps, with a sufficient bonding reliability being secured between the two components. <P>SOLUTION: One embodiment provides the method of manufacturing a semiconductor device. When bonding the semiconductor element and the circuit wiring board, both of which have electrodes on a principal plane, by flip chip bonding using solder bumps, a resist film having openings is formed over the electrodes formed on the principal plane of the semiconductor and/or the circuit wiring board, and metal bumps having a thickness not larger than that of the resist film are formed inside the openings. Thereafter, the resist film is removed, and the metal bumps are abutted in conformity with the electrodes on the principal plane of the other component. A space between both principal planes is filled with a thermosetting adhesive. By heating, the thermosetting adhesive is hardened, and at the same time, the metal bumps are melted to connect the electrodes on both principal planes. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、特に、はんだバンプを用いて半導体素子を回路配線基板に実装するための方法に係わるものである。
【0002】
【従来の技術】
電子部品の高密度実装化への要求が強くなっており、ベアチップ実装方式が注目されている。このベアチップ実装における接続構造は、ワイヤボンディング法によるフェイスアップ実装から、はんだバンプを用いたフリップチップ接合等のフェイスダウン実装へと変化してきている。このはんだバンプを用いた接合では、半導体素子の表面の電極上にはんだバンプを形成する。この形成方法としては電解めっき法や蒸着法あるいは、レジスト膜形成・はんだペースト充填等の工程を経て形成する印刷法等がある。バンプ形成後は、回路配線基板に対する接合のためフラックスを塗布した後位置合わせを行いリフロー加熱して接合を行う。さらに長期接合信頼性を確保するために半導体素子と回路配線基板間の隙間に対し接着剤を注入して硬化することを行っている。
【0003】
従来のバンプ形成・接合プロセスでは、半導体素子上に形成した絶縁膜の電極形成領域に開口を設け、電極パターンを形成し、感光性ポジ型レジスト膜を塗布し、フォトプロセスにより、電極パターン領域以外を感光させ、現像により、電極パターン領域上に開口を有するレジスト膜を残し、レジスト膜の開口に、はんだペーストを充填し、レジスト膜を除去してから加熱・冷却により、はんだを溶融(ウエットバック)して、電極パターン上にはんだバンプが固着する。次に、はんだバンプが形成された半導体素子をフリップチップ方式により、回路配線基板の電極に整合し再加熱により、接合体を作成し、続いて、はんだバンプ間の半導体素子と回路配線基板の間隙にアンダーフィル剤を注入・硬化させ双方を固着する。
【0004】
(3) 発明が解決しようとする問題点
上記の方法では、はんだバンプが溶融時に、表面張力によって球形になるため、電極及び電極間隔の微細化が進むと、ウエットバックの際に、隣接バンプ間にブリッジが発生する。図5のK、L、Mは、電極パターン上にはんだバンプを形成する工程を示すための半導体素子の断面構造である。図5のKで、半導体素子1上に絶縁膜2と電極パターン3とが形成され、絶縁膜2上には感光性ポジ型レジスト膜4が現像され、電極パターン領域のレジスト膜4の開口には、はんだペースト6が充填される。図5のLで、レジスト膜を除去し、電極パターン上に柱状のはんだペースト6を残し、図5のMで、加熱・冷却により、はんだを溶融(ウエットバック)すると、はんだバンプ7は球形になり、隣同士で接触する恐れが生じる。また、はんだバンプ7が球形になるため、微細化により、はんだバンプの高さも減少するので、半導体素子と回路配線基板の間隙が狭くなり、アンダーフィル剤の迅速かつ均一な注入のためには、粘性を減少させる必要が生じ、接着剤組成物の熱膨張率の調整のためのフィラー添加量を減らさざるを得なくなり、結果的に接着強度の低下を招いてしまう。ブリッジの発生を防止するために、レジスト膜を残したままバンプを形成し、且つ、充分なバンプ高さを得るために、電気メッキ法を用いることによりレジスト膜よりバンプを突出させる構造が提案されているが、この方法では、はんだバンプの頂上が球面になり、双方の整合の際に、位置合わせ精度の低下を招き、また、必然的に、バンプの突出部がマッシュルーム状になり、貼付タイプのシート状レジスト膜の剥離が困難になるなどの問題が生じる(例えば、特許文献1参照)。
【0005】
【特許文献1】
特開平6−13382号広報(A)(第6頁、第6図)
【0006】
【発明が解決しようとする課題】
本発明は上記従来技術の不都合を解決するためのものであり、その目的は、電極間隔の微細化において、隣接バンプ間ブリッジの発生を防止し、且つ、充分なバンプ高さを確保することにより、接着剤強度の高く、比較的高い粘性を有するアンダーフィル剤でも迅速かつ均一な注入を可能にする技術を提供することにある。
【0007】
【課題を解決するための手段】
上記の目的を達成するために、本願において開示される第一の手段は、一実施例の図1のAから図3Hの工程断面図に示されるように、レジスト膜に形成した開口内に、はんだバンプ7を電解めっき法によって供給するか、またはこれまでの粒度分布(平均粒径約34μm、20〜40μm)よりさらに微細なはんだ粉末(平均粒径約10μm、5〜20μm)を用いて、はんだペーストを充填した。次に、レジスト膜を残したまま、ウエットバックし、その後、レジスト膜を剥離除去することにより、設計寸法通りのバンプ径が得られ、隣接バンプ間のブリッジが防止できた。
【0008】
さらに第二の手段は、はんだバンプの高さをレジスト膜の膜厚以下に調節することにより、バンプは柱状かつ頂上部に平坦な面を有する形状を実現した。これにより、半導体素子と回路配線基板同士の整合・位置合わせ精度が向上した。
第三の手段は、多層膜又は複数回の工程により、レジスト膜の膜厚を2倍以上に形成し、バンプ高さを高くし、図4のI及びJに示すように、ピッチサイズPに対して隣接バンプと接触しないパッド径D(最大ピッチサイズの80%、Max.D=0.8P)の開口をパターニングし、その電極に対して電解めっき法によりはんだバンプを形成した。次に、ウエットバック処理した後、レジスト膜を剥離除去した。そして、はんだバンプを有する半導体素子をフリップチップ方式により、対応する回路配線基板の電極に位置合わせし、その間の間隙がフラックス成分および熱膨張係数調整用の無機物(アルミナまたはAlN粉末)フィラーを充填した接着剤で満たされた構造を形成する。
【0009】
このとき半導体素子の電極は以下のような効果からピッチサイズの約80%の範囲まで許容される。レジスト膜を除去してウエットバックする従来の方法では、はんだ溶融時には金属の表面張力によって球体化するため、パッド径ではピッチサイズの60%程度以上となると隣接バンプと接触しウエットバック終了時にはブリッジによるショートが発生するが、レジスト膜を残したままウエットバックすることによってバンプ形状は柱状となって接合後は接着剤によって覆われるために隣接バンプとのショートは生じない。
【0010】
尚、第四の手段として、柱状バンプの口径を電極間隔のピッチサイズの40〜80%に限定した理由として40%以下では接合面積の低下によって所望の接合信頼性が確保できないことおよび80%以上とすると感光性レジストの剛性が劣化してプロセス中に破損する可能性があるとともに配線基板との接合時に接着剤が全面に広がらないことによるブリッジ等のショートが生じて接合信頼性が確保できないことによる。
【0011】
また、第五の手段として、接合時に接着剤組成物として添加する熱膨張係数調整用のフィラーは従来の方法ではピッチサイズに見合った半導体素子と回路配線基板のギャップが小さく接着剤の流動性の点から添加量は最大70%程度と制約されたが、本発明ではバンプ形状を柱状とし、且つ、はんだ量(高さ)を2倍以上としているため半導体素子と回路配線基板間ギャップ量は2倍以上となって粘度の高い接着剤でも注入可能となる。 本発明にて検討した結果最大80%程度の添加量でも注入できて接合が可能となっている。したがって、回路配線基板の選択に伴う熱膨張係数の調整範囲(無機物の添加量)も大きいことから接合信頼性向上が期待される。回路配線基板との接合に際してはフラックス成分を有する接着剤を塗布して、接着剤の硬化により半導体素子と回路配線基板間同士を接着すると共に、はんだの溶融個化により電極間接合とを行うことによってさらに応力緩和効果を高めた。
【0012】
さらに、第六の手段として、半導体素子或いは回路配線基板の、少なくともいずれか一方の主表面に熱硬化性接着剤を塗布した後、金属バンプを他方の主表面の電極に整合当接することにより、両主表面間が熱硬化性接着剤で満たされた構造を形成することも可能である。これにより、両主表面間のギャップによらず、熱硬化性接着剤の最適なフィラー量と粘度を先に選択することが可能になる。
【0013】
尚、本発明に用いるはんだバンプのめっき組成、及び、はんだ粉末の組成は多種多様の組成を用いることができるが、 例えば、 Sn、 Pb、 Ag、 Cu、 In、 Bi、 Zn、 Sbなどのめっき液、或いは、これら組成の材料を適宜混合・合金化したはんだ粉末を用いる方法が好ましい。
本発明での耐熱性膜の開口部への、はんだバンプの供給方法としては、はんだ合金の電解めっき、及び、はんだペースト充填の両者のいずれでも良い。これらの方法の選択尺度としては、比較的ピッチサイズが大きく、はんだバンプ高さを必要としない場合は、低コストで形成できるはんだペーストによる印刷法を、又、はんだ高さを稼ぐことによる応力緩和を期待し、狭ピッチサイズが要求される実装方式においては、電解めっき法を各々選択して、はんだバンプを形成することが望ましいと考える。
【0014】
以上により、本発明では50μm以下の狭ピッチで微細な電極に接合用のバンプと樹脂による接着を高精度に行うことが可能であり、微細な接続部における接合信頼性を向上できる。
【0015】
【発明の実施の形態】
本発明の実施例において共通に使用される材料を以下に一括例示するが、これらによって限定されるものではない。
金属材料−1(はんだめっき膜)
Sn−Bi電解めっき液、組成Sn−57wt%Biとなるように、SnとBiのめっき液を混合建浴したものゝ膜厚ばらつき:レジスト厚さ±10%以内の高さの範囲内に収まるよう電流値および攪拌条件を設定した。
金属材料−2(はんだペースト)
はんだ粉末は、組成がSn−3.5wt%Ag、平均粒径14μm粒度分布10〜20μmの形状を使用した。
ロジンとしてポリペールを47g、安息香酸ベンジル53g、無水こはく酸2gを混合したものをフラックスビフィクルとし、はんだ粉末と1:9の割合で混合してはんだペーストとした。
金属材料− (はんだペースト)
はんだ粉末は、組成がSn−57wt%Bi−1wt%Ag、平均粒径14μm粒度分布10〜20μmの形状を使用した。
ロジンとしてポリペールを47g、安息香酸ベンジル53g、無水こはく酸2gを混合したものをフラックスビフィクルとし、はんだ粉末と1:9の割合で混合してはんだペーストとした。
金属材料− (はんだペースト)
はんだ粉末は、組成がSn−3.5wt%Ag、平均粒径35μm、粒度分布20〜40μmの形状を使用した。
ロジンとしてポリペールを47g、安息香酸ベンジル53g、無水こはく酸2gを混合したものをフラックスビフィクルとし、はんだ粉末と1:9の割合で混合してはんだペーストとした。
樹脂材料 −1(感光性ポジレジスト膜)
アクリレート系フィルム、膜厚25μm
樹脂材料−2(接着組成物)
エポキシ系フラックスフィルにシリカ粉末(平均粒径4μm)を50〜80wt%の割合で混合したものを樹脂材料−2とした。
【0016】
以下に、図1のAから図3のHまでと、図4のIとJの各工程断面図に沿って、本発明の半導体装置の製造方法を具体的に示す。
実施例1:半導体素子1の表面に形成された絶縁膜2と、ピッチサイズが200μm、電極パッド径が100μm(電極数2000個)の電極パターン3の上に、樹脂材料−1からなるフォトレジスト膜4を100℃で貼り付け、フォトマスク5を用い、フォトレジスト膜4を露光/現像し、電極パターン3上に100μmφの開口部を形成した。現像はnメチル2−ピロリドンを用いた。形成した開口部に金属材料−1からなるはんだめっき膜6を電解めっきにより膜厚約20±2μmとなるように成膜した。次にフラックス(図示せず)を塗布した後、溶融・固化(ウエットバック)した。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去することにより、電極パターン3上に、フォトレジスト膜4の開口部と同じ口径の柱状のはんだバンプ7を得た。この半導体素子1を搭載する回路配線基板(BTレジン製)8に電極を位置合わせして搭載し、樹脂材料−2を塗布した後、20gの荷重を加えながらMax.230℃(融点138℃)以上約5分の温度プロファイルにてリフロー接合を行った。その結果良好な接合部9を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好であった。
【0017】
実施例2:ピッチサイズが100μm、電極パッド径が50μm(電極数2000個)の半導体素子の表面に、樹脂材料−1を100℃で貼り付け、露光/現像で電極上部に50μmφの開口部を形成した。現像はnメチル2−ピロリドンを用いた。形成した開口部に金属材料−1を電解めっきにより膜厚約20±2μmとなるように成膜した。次にフラックスを塗布した後、ウエットバックした。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去した。この半導体素子を搭載する配線基板(BTレジン製)に電極を位置合わせして搭載し樹脂材料−2を塗布した後、20gの荷重を加えながらMax.230℃(融点138℃)以上約5分の温度プロファイルにてリフロー接合を行った。その結果良好な接合部を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好であった。
【0018】
実施例3:ピッチサイズが50μm、電極パッド径が25μm(電極数2000個)の半導体素子の表面に樹脂材料−1を100℃で貼り付け、露光/現像で電極上部に25μmφの開口部を形成した。現像はnメチル2−ピロリドンを用いた。形成した開口部に金属材料−1を電解めっきにより膜厚約20±2μmとなるように成膜した。次にフラックスを塗布した後、ウエットバックした。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去した。この半導体素子を搭載する配線基板(BTレジン製)に電極を位置合わせして搭載し樹脂材料−2を塗布した後、20gの荷重を加えながらMax.230℃(融点138℃)以上約5分の温度プロファイルにてリフロー接合を行った。その結果良好な接合部を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好であった。
【0019】
実施例4:ピッチサイズが50μm、電極パッド径が40μm(電極数2000個)の半導体素子の表面に樹脂材料−1を2枚重ねて100℃で貼り付け、露光/現像で電極上部に40μmφの開口部を形成した。現像はnメチル2−ピロリドンを用いた。形成した開口部に金属材料−1を電解めっきにより膜厚約40±4μmとなるように成膜した。次にフラックスを塗布した後、ウエットバックした。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去した。この半導体素子を搭載する配線基板(BTレジン製)に電極を位置合わせして搭載し、樹脂材料−2を塗布した後、20g荷重を加えながらMax.230℃(融点138℃)以上約5分の温度プロファイルにてリフロー接合を行った。その結果、良好な接合部を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好であった。
【0020】
実施例5:ピッチサイズが100μm、電極パッド径が50μm(電極数2000個)の半導体素子の表面に樹脂材料−1を100℃で貼り付け、露光/現像で電極上部に50μmφの開口部を形成する。現像はnメチル2−ピロリドンを用いた。金属材料−2を形成した開口部にウレタンゴムスキージを用いて充填した。次にフラックスを塗布した後、ウエットバックした。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去した。この半導体素子を搭載する配線基板(BTレジン製)表面に樹脂材料−2を塗布した後、両主表面の電極を位置合わせして搭載し、20gの荷重を加えながらMax.230℃(融点221℃)以上約2分の温度プロファイルにてリフロー接合を行った。その結果、良好な接合部を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好である。また、121℃/85%の環境下に1000hr放置後においても、 サイクル試験と同様に抵抗上昇は10%以下と良好であることを確認した。改善されることは明らかである。
【0021】
実施例6:ピッチサイズが100μm、電極パッド径が50μm(電極数2000個)の半導体素子の表面に樹脂材料−1を100℃で貼り付け、露光/現像で電極上部に50μmφの開口部を形成する。現像はnメチル2−ピロリドンを用いた。金属材料−3を形成した開口部にウレタンゴムスキージを用いて充填した。次にフラックスを塗布した後、ウエットバックした。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去した。この半導体素子を搭載する配線基板(BTレジン製)表面に樹脂材料−2を塗布した後、双方の電極を位置合わせして搭載し、20gの荷重を加えながらMax.230℃(融点138℃)以上約5分の温度プロファイルにてリフロー接合を行った。その結果、良好な接合部を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好である。また、121℃/85%の環境下に1000hr放置後においても、 サイクル試験と同様に抵抗上昇は10%以下と良好であることを確認した。
【0022】
実施例7:ピッチサイズが50μm、電極パッド径が30μm(電極数2000個)の半導体素子の表面に樹脂材料−1を2枚重ねて100℃で貼り付け、露光/現像で電極上部に40μmφの開口部を形成した。現像はnメチル2−ピロリドンを用いた。形成した開口部に金属材料−1を電解めっきにより膜厚約40±4μmとなるように製膜した。次にフラックスを塗布した後、ウエットバックした。その後、5%モノエタノールアミン水溶液で、フィルム状のアクリレート樹脂を除去した。この半導体素子を搭載する回路配線基板(BTレジン製)に電極を位置合わせして搭載し樹脂材料−2を塗布した後、20g荷重を加えながらMax.230℃(融点138℃)以上約5分の温度プロファイルにてリフロー接合を行った。その際、初めの3分間は120℃に維持し樹脂材料−2を硬化させ、次の2分間は200℃に維持しはんだバンプを再溶融した。その結果良好な接合部を形成できていることを確認した。接続信頼性については、−55〜125℃の温度サイクル試験を2000サイクル行った結果、 抵抗上昇は10%以下と良好であった。
【0023】
(付記1)主表面に共に電極を有する半導体素子と回路配線基板の、少なくともいずれか一方の主表面の該電極上に開口部を有する耐熱性膜を形成する工程と、該開口部内に該耐熱性の膜厚以下の高さの金属バンプを形成する工程と、しかる後、該耐熱性膜を除去する工程と、該金属バンプを他方の主表面の該電極に整合当接する工程と、両主表面間の間隙に熱硬化性接着剤を充填する工程と、加熱により、該熱硬化性接着剤を硬化させると共に、該金属バンプによって両主表面の該電極間を接続する工程とを含むことを特徴とする半導体装置の製造方法。
【0024】
(付記2)前記金属バンプの頂上部に平坦部を有することを特徴とする付記1記載の半導体装置の製造方法。
(付記3)前記耐熱性膜は、多層膜又は複数回の工程により形成されることを特徴とする付記1記載の半導体装置の製造方法。
(付記4)前記加熱において、初め前記金属バンプの融点以下の温度で前記熱硬化性接着剤を硬化させ、しかる後、該金属バンプを溶融と冷却固化することを特徴とする付記1記載の半導体装置の製造方法。
【0025】
(付記5)前記両主表面間の間隙に前記熱硬化性接着剤を充填する工程において、前記金属バンプが既に形成された前記半導体素子或いは前記回路配線基板の、少なくともいずれか一方の主表面の主表面に前記熱硬化性接着剤を塗布した後、該金属バンプを他方の主表面の該電極に整合当接することにより、該両主表面間に該熱硬化性接着剤を充填することを特徴とする付記1記載の半導体装置の製造方法。
【0026】
(付記6)前記金属バンプは、はんだ金属であることを特徴とする付記1記載の半導体装置の製造方法。
(付記7)前記開口部内の前記金属バンプは、該開口部へ、電解めっき法による金属の充填、或いは印刷法による金属ペーストの充填の少なくともいずれか一方の工程の後、加熱溶融と冷却固化とにより形成されることを特徴とする付記1記載の半導体装置の製造方法。
【0027】
(付記8)前記耐熱性膜は、樹脂膜であることを特徴とする付記1記載の半導体装置の製造方法。
(付記9)前記金属バンプの径は、前記電極のピッチサイズの40〜80%であることを特徴とする付記1記載の半導体装置の製造方法。
(付記10)前記熱硬化性接着剤のフィラー添加量は、該熱硬化性接着剤の60〜80wt%範囲内にあることを特徴とする付記1記載の半導体装置の製造方法。
【0028】
(付記11)前記金属バンプを他方の主表面の該電極に整合当接した後、該金属バンプの融点以下の温度で加熱し、該金属バンプと該電極とを固着させ、しかる後、両主表面間の間隙に前記熱硬化性接着剤を注入することを特徴とする付記1記載の半導体装置の製造方法。
(付記12)前記金属バンプは、前記基板主表面に対し、垂直な側壁を有することを特徴とする付記1記載の半導体装置の製造方法。
【0029】
(付記13)前記熱硬化性接着剤は、フラックスを含有することを特徴とする付記1記載の半導体装置の製造方法。
(付記14)前記金属バンプの径は、前記電極の径より大であることを特徴とする付記9記載の半導体装置の製造方法。
【0030】
【発明の効果】
本発明によれば、50μmの狭ピッチサイズの電極を有する半導体素子と回路配線基板の接合において、はんだバンプ径がピッチサイズの80%でも十分な接合信頼性を確保できる。
【図面の簡単な説明】
【図1】本発明の半導体装置の製造工程断面図(その1)
【図2】本発明の半導体装置の製造工程断面図(その2)
【図3】本発明の半導体装置の製造工程断面図(その3)
【図4】本発明の半導体装置の製造工程断面図(その4)
【図5】従来のはんだバンプの形成工程断面図
【符号の説明】
1、半導体素子
2、絶縁膜
3、電極パターン
4、フォトレジスト膜
5、フォトマスク
6、はんだめっき膜、又は、はんだペースト
7、はんだバンプ
8、回路配線基板
9、熱硬化性接着剤
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for mounting a semiconductor element on a circuit wiring board using solder bumps.
[0002]
[Prior art]
There is an increasing demand for high-density mounting of electronic components, and the bare chip mounting method is attracting attention. The connection structure in this bare chip mounting has changed from face-up mounting by wire bonding to face-down mounting such as flip chip bonding using solder bumps. In the bonding using the solder bump, the solder bump is formed on the electrode on the surface of the semiconductor element. As this forming method, there are an electrolytic plating method, a vapor deposition method, a printing method for forming through a process such as resist film formation and solder paste filling. After the bumps are formed, the flux is applied for bonding to the circuit wiring board, alignment is performed, and reflow heating is performed for bonding. Further, in order to ensure long-term bonding reliability, an adhesive is injected into the gap between the semiconductor element and the circuit wiring board and cured.
[0003]
In the conventional bump formation / bonding process, an opening is formed in the electrode formation region of the insulating film formed on the semiconductor element, an electrode pattern is formed, a photosensitive positive resist film is applied, and a region other than the electrode pattern region is formed by a photo process. The resist film having an opening on the electrode pattern region is left by developing, and the resist film opening is filled with a solder paste, and after removing the resist film, the solder is melted by heating and cooling (wet back). Then, the solder bumps are fixed on the electrode pattern. Next, the semiconductor element on which the solder bump is formed is aligned with the electrode of the circuit wiring board by a flip chip method, and reheated to form a joined body. Subsequently, the gap between the semiconductor element between the solder bump and the circuit wiring board is formed. Inject and cure the underfill agent to fix both.
[0004]
(3) Problems to be Solved by the Invention In the above method, when the solder bumps are melted, they become spherical due to surface tension. Therefore, when the electrodes and the distance between the electrodes are made finer, the gap between adjacent bumps is increased during wet back. A bridge occurs. K, L, and M in FIG. 5 are cross-sectional structures of the semiconductor element for illustrating a process of forming solder bumps on the electrode pattern. In FIG. 5K, the insulating film 2 and the electrode pattern 3 are formed on the semiconductor element 1, and the photosensitive positive resist film 4 is developed on the insulating film 2 so as to open the resist film 4 in the electrode pattern region. Is filled with solder paste 6. At L in FIG. 5, the resist film is removed, leaving the columnar solder paste 6 on the electrode pattern, and when M is melted (wet back) by heating and cooling at M in FIG. 5, the solder bumps 7 become spherical. And there is a risk of contact between neighbors. In addition, since the solder bumps 7 have a spherical shape, the height of the solder bumps is reduced by miniaturization, so that the gap between the semiconductor element and the circuit wiring board is narrowed, and for quick and uniform injection of the underfill agent, It becomes necessary to reduce the viscosity, and the amount of filler added for adjusting the coefficient of thermal expansion of the adhesive composition must be reduced, resulting in a decrease in adhesive strength. In order to prevent the occurrence of bridging, a structure is proposed in which bumps are formed while leaving the resist film, and in order to obtain a sufficient bump height, a bump is projected from the resist film by using an electroplating method. However, in this method, the top of the solder bump becomes a spherical surface, which causes a decrease in alignment accuracy when aligning the two, and inevitably, the bump protrusion becomes a mushroom, which is a sticking type. This causes problems such as difficulty in peeling off the sheet-like resist film (see, for example, Patent Document 1).
[0005]
[Patent Document 1]
Japanese Laid-Open Patent Publication No. 6-13382 (A) (Page 6, Figure 6)
[0006]
[Problems to be solved by the invention]
The present invention is to solve the above-mentioned disadvantages of the prior art, and its purpose is to prevent the occurrence of bridges between adjacent bumps and to secure a sufficient bump height in the miniaturization of electrode spacing. Another object of the present invention is to provide a technique that enables quick and uniform injection even with an underfill agent having a high adhesive strength and a relatively high viscosity.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the first means disclosed in the present application is, as shown in the process cross-sectional views of FIGS. 1A to 3H in one embodiment, in the opening formed in the resist film, Solder bump 7 is supplied by electrolytic plating, or using a finer solder powder (average particle size of about 10 μm, 5 to 20 μm) than the conventional particle size distribution (average particle size of about 34 μm, 20 to 40 μm), Filled with solder paste. Next, wet back was performed with the resist film left, and then the resist film was peeled and removed to obtain a bump diameter as designed, thereby preventing bridging between adjacent bumps.
[0008]
Furthermore, the second means realizes the shape of the bump having a columnar shape and a flat surface at the top by adjusting the height of the solder bump to be equal to or less than the thickness of the resist film. Thereby, the alignment / alignment accuracy between the semiconductor element and the circuit wiring board is improved.
The third means is that the resist film is formed more than twice by a multilayer film or a plurality of processes, the bump height is increased, and the pitch size P is increased as shown in I and J of FIG. On the other hand, an opening having a pad diameter D (80% of the maximum pitch size, Max. D = 0.8 P) that does not contact the adjacent bump was patterned, and a solder bump was formed on the electrode by electrolytic plating. Next, after the wet back treatment, the resist film was removed. Then, the semiconductor element having solder bumps is aligned with the corresponding electrode of the circuit wiring board by a flip chip method, and the gap between them is filled with an inorganic substance (alumina or AlN powder) filler for adjusting the flux component and the thermal expansion coefficient. Form a structure filled with adhesive.
[0009]
At this time, the electrodes of the semiconductor element are allowed to a range of about 80% of the pitch size due to the following effects. In the conventional method of removing the resist film and performing wet back, the sphere is formed by the surface tension of the metal when the solder is melted. Therefore, when the pad diameter is about 60% or more of the pitch size, it comes into contact with the adjacent bump, Although a short circuit occurs, by performing wet back while leaving the resist film, the bump shape becomes a columnar shape and is covered with an adhesive after bonding, so that a short circuit with an adjacent bump does not occur.
[0010]
As a fourth means, the reason why the diameter of the columnar bump is limited to 40 to 80% of the pitch size of the electrode interval is that if 40% or less, the desired bonding reliability cannot be ensured due to the reduction of the bonding area, and 80% or more. In such a case, the rigidity of the photosensitive resist may be deteriorated and may be damaged during the process, and a short circuit such as a bridge occurs due to the adhesive not spreading over the entire surface when bonded to the wiring board, so that the bonding reliability cannot be ensured. by.
[0011]
In addition, as a fifth means, the filler for adjusting the thermal expansion coefficient added as an adhesive composition at the time of bonding has a small gap between the semiconductor element and the circuit wiring board corresponding to the pitch size in the conventional method, and the fluidity of the adhesive is small. However, in the present invention, the bump shape is columnar and the amount of solder (height) is twice or more, so the gap amount between the semiconductor element and the circuit wiring board is 2 It becomes more than double, and even an adhesive with high viscosity can be injected. As a result of the study in the present invention, even an addition amount of up to about 80% can be injected and bonding is possible. Therefore, since the adjustment range (addition amount of the inorganic substance) of the thermal expansion coefficient associated with the selection of the circuit wiring board is large, an improvement in bonding reliability is expected. When bonding to the circuit wiring board, an adhesive having a flux component is applied, the semiconductor element and the circuit wiring board are bonded to each other by curing the adhesive, and the electrodes are bonded to each other by melting and individualizing the solder. The stress relaxation effect was further enhanced.
[0012]
Furthermore, as a sixth means, after applying a thermosetting adhesive to at least one main surface of the semiconductor element or circuit wiring board, the metal bump is aligned and brought into contact with the electrode on the other main surface, It is also possible to form a structure in which the space between both main surfaces is filled with a thermosetting adhesive. This makes it possible to first select the optimum filler amount and viscosity of the thermosetting adhesive regardless of the gap between the two main surfaces.
[0013]
The solder bump plating composition and the solder powder composition used in the present invention can be of a wide variety of compositions, for example, Sn, Pb, Ag, Cu, In, Bi, Zn, Sb, etc. A method using a liquid or solder powder obtained by appropriately mixing and alloying materials of these compositions is preferable.
As a method for supplying solder bumps to the openings of the heat-resistant film in the present invention, both solder plating electrolytic plating and solder paste filling may be used. As a selection scale of these methods, when the pitch size is relatively large and the solder bump height is not required, a printing method using a solder paste that can be formed at low cost, and stress relaxation by increasing the solder height are used. Therefore, in a mounting method that requires a narrow pitch size, it is desirable to select an electrolytic plating method and form solder bumps.
[0014]
As described above, in the present invention, it is possible to bond a bonding electrode and a resin to a minute electrode with a narrow pitch of 50 μm or less with high accuracy, and it is possible to improve bonding reliability in a minute connection portion.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The materials commonly used in the embodiments of the present invention are exemplified below, but are not limited thereto.
Metal material-1 (Solder plating film)
Sn-Bi electrolytic plating solution, Sn-Bi plating solution mixed so as to have composition Sn-57wt% Bi. Thickness variation: within the range of resist thickness ± 10% height The current value and stirring conditions were set.
Metal material-2 (solder paste)
The solder powder used had a composition of Sn-3.5 wt% Ag, an average particle size of 14 μm, and a particle size distribution of 10 to 20 μm.
As a rosin, a mixture of 47 g of polypele, 53 g of benzyl benzoate, and 2 g of succinic anhydride was used as a flux bificle, which was mixed with solder powder at a ratio of 1: 9 to obtain a solder paste.
Metal material- 3 (Solder paste)
As the solder powder, a composition having a composition of Sn-57 wt% Bi-1 wt% Ag and an average particle diameter of 14 μm and a particle size distribution of 10 to 20 μm was used.
As a rosin, a mixture of 47 g of polypele, 53 g of benzyl benzoate, and 2 g of succinic anhydride was used as a flux bificle, which was mixed with solder powder at a ratio of 1: 9 to obtain a solder paste.
Metal material- 4 (Solder paste)
As the solder powder, a shape having a composition of Sn-3.5 wt% Ag, an average particle size of 35 μm, and a particle size distribution of 20 to 40 μm was used.
As a rosin, a mixture of 47 g of polypele, 53 g of benzyl benzoate, and 2 g of succinic anhydride was used as a flux bificle, which was mixed with solder powder at a ratio of 1: 9 to obtain a solder paste.
Resin material -1 (photosensitive positive resist film)
Acrylate film, film thickness 25μm
Resin material-2 (adhesive composition)
Resin material-2 was prepared by mixing epoxy powder with silica powder (average particle size 4 μm) at a ratio of 50 to 80 wt%.
[0016]
A method for manufacturing a semiconductor device according to the present invention will be specifically described below along A to J in FIG. 1 and sectional views of steps I and J in FIG. 4.
Example 1 : Photoresist made of resin material-1 on insulating film 2 formed on the surface of semiconductor element 1 and electrode pattern 3 having a pitch size of 200 μm and an electrode pad diameter of 100 μm (2000 electrodes). The film 4 was attached at 100 ° C., and the photoresist film 4 was exposed / developed using the photomask 5 to form an opening of 100 μmφ on the electrode pattern 3. N-methyl 2-pyrrolidone was used for development. A solder plating film 6 made of metal material-1 was formed in the formed opening by electrolytic plating so as to have a film thickness of about 20 ± 2 μm. Next, flux (not shown) was applied and then melted and solidified (wet back). Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution to obtain a columnar solder bump 7 having the same diameter as the opening of the photoresist film 4 on the electrode pattern 3. An electrode is positioned and mounted on a circuit wiring board (made of BT resin) 8 on which the semiconductor element 1 is mounted, and after applying the resin material-2, Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point: 138 ° C.) or more and about 5 minutes. As a result, it was confirmed that a good joint 9 was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase was as good as 10% or less.
[0017]
Example 2 : Resin material-1 was applied to the surface of a semiconductor element having a pitch size of 100 μm and an electrode pad diameter of 50 μm (2000 electrodes) at 100 ° C., and an opening of 50 μmφ was formed on the electrode by exposure / development. Formed. N-methyl 2-pyrrolidone was used for development. Metal material-1 was formed into a film thickness of about 20 ± 2 μm by electrolytic plating in the formed opening. Next, after applying the flux, it was wet-backed. Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution. After aligning and mounting the electrodes on the wiring board (made of BT resin) on which this semiconductor element is mounted, and applying the resin material-2, Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point: 138 ° C.) or more and about 5 minutes. As a result, it was confirmed that a good joint was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase was as good as 10% or less.
[0018]
Example 3 : Resin material-1 was attached to the surface of a semiconductor element having a pitch size of 50 μm and an electrode pad diameter of 25 μm (2000 electrodes) at 100 ° C., and an opening of 25 μmφ was formed on the electrode by exposure / development. did. N-methyl 2-pyrrolidone was used for development. Metal material-1 was formed into a film thickness of about 20 ± 2 μm by electrolytic plating in the formed opening. Next, after applying the flux, it was wet-backed. Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution. After aligning and mounting the electrodes on the wiring board (made of BT resin) on which this semiconductor element is mounted, and applying the resin material-2, Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point: 138 ° C.) or more and about 5 minutes. As a result, it was confirmed that a good joint was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase was as good as 10% or less.
[0019]
Example 4 : Two resin materials-1 are stacked on the surface of a semiconductor element having a pitch size of 50 μm and an electrode pad diameter of 40 μm (the number of electrodes is 2000) and bonded at 100 ° C. An opening was formed. N-methyl 2-pyrrolidone was used for development. Metal material-1 was formed into a film thickness of about 40 ± 4 μm by electrolytic plating in the formed opening. Next, after applying the flux, it was wet-backed. Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution. An electrode is aligned and mounted on a wiring board (made of BT resin) on which this semiconductor element is mounted, and after applying resin material-2, Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point: 138 ° C.) or more and about 5 minutes. As a result, it was confirmed that a good joint was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase was as good as 10% or less.
[0020]
Example 5 : Resin material-1 was attached to the surface of a semiconductor element having a pitch size of 100 μm and an electrode pad diameter of 50 μm (2000 electrodes) at 100 ° C., and an opening of 50 μmφ was formed on the upper part of the electrode by exposure / development. To do. N-methyl 2-pyrrolidone was used for development. The opening formed with the metal material-2 was filled with a urethane rubber squeegee. Next, after applying the flux, it was wet-backed. Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution. After applying the resin material-2 on the surface of the wiring board (made of BT resin) on which this semiconductor element is mounted, the electrodes on both main surfaces are aligned and mounted, and Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point 221 ° C.) or more and about 2 minutes. As a result, it was confirmed that a good joint was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase is as good as 10% or less. Further, even after being left for 1000 hours in an environment of 121 ° C./85%, it was confirmed that the resistance increase was as good as 10% or less as in the cycle test. Obviously it will be improved.
[0021]
Example 6 : Resin material-1 was attached to the surface of a semiconductor element having a pitch size of 100 μm and an electrode pad diameter of 50 μm (number of electrodes: 2000) at 100 ° C., and an opening of 50 μmφ was formed above the electrodes by exposure / development. To do. N-methyl 2-pyrrolidone was used for development. The opening formed with metal material-3 was filled with a urethane rubber squeegee. Next, after applying the flux, it was wet-backed. Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution. After applying the resin material-2 on the surface of the wiring board (made of BT resin) on which this semiconductor element is mounted, both electrodes are aligned and mounted, and a Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point: 138 ° C.) or more and about 5 minutes. As a result, it was confirmed that a good joint was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase is as good as 10% or less. Further, even after being left for 1000 hours in an environment of 121 ° C./85%, it was confirmed that the resistance increase was as good as 10% or less as in the cycle test.
[0022]
Example 7 : Two resin materials-1 are stacked on the surface of a semiconductor element having a pitch size of 50 μm and an electrode pad diameter of 30 μm (2000 electrodes) and attached at 100 ° C., and exposed / developed with 40 μmφ on the electrode. An opening was formed. N-methyl 2-pyrrolidone was used for development. The metal material-1 was formed into a film thickness of about 40 ± 4 μm by electrolytic plating in the formed opening. Next, after applying the flux, it was wet-backed. Thereafter, the film-like acrylate resin was removed with a 5% monoethanolamine aqueous solution. After aligning and mounting the electrodes on the circuit wiring board (made of BT resin) on which this semiconductor element is mounted, and applying the resin material-2, Max. Reflow bonding was performed with a temperature profile of 230 ° C. (melting point: 138 ° C.) or more and about 5 minutes. At that time, the resin material-2 was cured by maintaining at 120 ° C. for the first 3 minutes, and the solder bump was remelted by maintaining at 200 ° C. for the next 2 minutes. As a result, it was confirmed that a good joint was formed. As for the connection reliability, as a result of 2000 cycles of a temperature cycle test at −55 to 125 ° C., the resistance increase was as good as 10% or less.
[0023]
(Appendix 1) A step of forming a heat-resistant film having an opening on at least one of the main surface of a semiconductor element and a circuit wiring board both having electrodes on the main surface, and the heat resistance in the opening A step of forming a metal bump having a height equal to or less than the thickness of the conductive film, a step of removing the heat-resistant film, a step of aligning and contacting the metal bump with the electrode on the other main surface, Filling a gap between the surfaces with a thermosetting adhesive, and curing the thermosetting adhesive by heating, and connecting the electrodes on both main surfaces with the metal bumps. A method of manufacturing a semiconductor device.
[0024]
(Additional remark 2) The manufacturing method of the semiconductor device of Additional remark 1 characterized by having a flat part in the top part of the said metal bump.
(Supplementary note 3) The method for manufacturing a semiconductor device according to supplementary note 1, wherein the heat-resistant film is formed by a multilayer film or a plurality of processes.
(Supplementary note 4) The semiconductor according to supplementary note 1, wherein in the heating, the thermosetting adhesive is first cured at a temperature lower than the melting point of the metal bump, and then the metal bump is melted and cooled and solidified. Device manufacturing method.
[0025]
(Supplementary Note 5) In the step of filling the thermosetting adhesive in the gap between the two main surfaces, at least one main surface of the semiconductor element or the circuit wiring board on which the metal bump has already been formed. After the thermosetting adhesive is applied to the main surface, the thermosetting adhesive is filled between the main surfaces by bringing the metal bumps into alignment contact with the electrodes on the other main surface. The manufacturing method of the semiconductor device of Additional remark 1.
[0026]
(Additional remark 6) The said metal bump is a solder metal, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Appendix 7) The metal bumps in the opening are heated and melted and cooled and solidified after at least one of filling the opening with metal by electrolytic plating or filling with metal paste by printing. The method for manufacturing a semiconductor device according to appendix 1, wherein:
[0027]
(Additional remark 8) The said heat resistant film is a resin film, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 9) The diameter of the said metal bump is 40 to 80% of the pitch size of the said electrode, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 10) The filler addition amount of the said thermosetting adhesive agent exists in the range of 60-80 wt% of this thermosetting adhesive agent, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
[0028]
(Appendix 11) After the metal bump is brought into alignment contact with the electrode on the other main surface, the metal bump is heated at a temperature equal to or lower than the melting point of the metal bump to fix the metal bump to the electrode. The method of manufacturing a semiconductor device according to appendix 1, wherein the thermosetting adhesive is injected into a gap between the surfaces.
(Additional remark 12) The said metal bump has a side wall perpendicular | vertical with respect to the said board | substrate main surface, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
[0029]
(Additional remark 13) The said thermosetting adhesive agent contains a flux, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Supplementary note 14) The method of manufacturing a semiconductor device according to supplementary note 9, wherein a diameter of the metal bump is larger than a diameter of the electrode.
[0030]
【The invention's effect】
According to the present invention, when joining a semiconductor element having an electrode with a narrow pitch size of 50 μm and a circuit wiring board, sufficient joining reliability can be ensured even if the solder bump diameter is 80% of the pitch size.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device of the present invention (part 1).
FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device of the present invention (No. 2)
FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor device according to the present invention (part 3);
FIG. 4 is a sectional view of a semiconductor device according to an embodiment of the present invention (part 4).
FIG. 5 is a sectional view of a conventional solder bump formation process.
DESCRIPTION OF SYMBOLS 1, Semiconductor element 2, Insulating film 3, Electrode pattern 4, Photoresist film 5, Photomask 6, Solder plating film or solder paste 7, Solder bump 8, Circuit wiring board 9, Thermosetting adhesive

Claims (5)

主表面に共に電極を有する半導体素子と回路配線基板の、少なくともいずれか一方の主表面の該電極上に開口部を有する耐熱性膜を形成する工程と、該開口部内に該耐熱性膜の膜厚以下の高さの金属バンプを形成する工程と、しかる後、該耐熱性膜を除去する工程と、該金属バンプを他方の主表面の該電極に整合当接する工程と、両主表面間の間隙に熱硬化性接着剤を充填する工程と、加熱により、該熱硬化性接着剤を硬化させると共に、該金属バンプによって両主表面の該電極間を接続する工程とを含むことを特徴とする半導体装置の製造方法。A step of forming a heat-resistant film having an opening on at least one of the main surface of the semiconductor element and the circuit wiring board having electrodes on the main surface; and a film of the heat-resistant film in the opening. Forming a metal bump having a height less than the thickness, then removing the heat-resistant film, aligning and contacting the metal bump with the electrode on the other main surface, and between the two main surfaces A step of filling the gap with a thermosetting adhesive; and a step of curing the thermosetting adhesive by heating and connecting the electrodes on both main surfaces by the metal bumps. A method for manufacturing a semiconductor device. 前記金属バンプの頂上部に平坦部を有することを特徴とする請求項1記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a flat portion is provided on the top of the metal bump. 前記耐熱性膜は、多層膜又は複数回の工程により形成されることを特徴とする請求項1記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat resistant film is formed by a multilayer film or a plurality of processes. 前記加熱において、初め前記金属バンプの融点以下の温度で前記熱硬化性接着剤を硬化させ、しかる後、該金属バンプを溶融と冷却固化させることを特徴とする請求項1記載の半導体装置の製造方法。2. The manufacturing of a semiconductor device according to claim 1, wherein in the heating, the thermosetting adhesive is first cured at a temperature equal to or lower than a melting point of the metal bump, and then the metal bump is melted and cooled and solidified. Method. 前記両主表面基板間の前記金属バンプを除く間隙に前記熱硬化性接着剤を充填する工程において、前記金属バンプが既に形成された前記半導体素子或いは前記回路配線基板の、少なくともいずれか一方の主表面の主表面に前記熱硬化性接着剤を塗布した後、該金属バンプを他方の主表面の該電極に整合当接することにより、該両主表面間に該熱硬化性接着剤を充填することを特徴とする請求項1記載の半導体装置の製造方法。In the step of filling the gap other than the metal bumps between the main surface substrates with the thermosetting adhesive, at least one of the semiconductor element and the circuit wiring board on which the metal bumps have already been formed. After the thermosetting adhesive is applied to the main surface of the surface, the thermosetting adhesive is filled between the two main surfaces by aligning and contacting the metal bumps with the electrode on the other main surface. The method of manufacturing a semiconductor device according to claim 1.
JP2002334304A 2002-11-18 2002-11-18 Manufacturing method of semiconductor device Expired - Fee Related JP4055556B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002334304A JP4055556B2 (en) 2002-11-18 2002-11-18 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002334304A JP4055556B2 (en) 2002-11-18 2002-11-18 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2004172238A true JP2004172238A (en) 2004-06-17
JP4055556B2 JP4055556B2 (en) 2008-03-05

Family

ID=32698785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002334304A Expired - Fee Related JP4055556B2 (en) 2002-11-18 2002-11-18 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4055556B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006128493A (en) * 2004-10-29 2006-05-18 Fujitsu Ltd Forming method for connective bump, semiconductor element, and manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006128493A (en) * 2004-10-29 2006-05-18 Fujitsu Ltd Forming method for connective bump, semiconductor element, and manufacturing method of semiconductor device
JP4533724B2 (en) * 2004-10-29 2010-09-01 富士通株式会社 Method for forming connection bump and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP4055556B2 (en) 2008-03-05

Similar Documents

Publication Publication Date Title
JP4287475B2 (en) Resin composition
JP4084835B2 (en) Flip chip mounting method and inter-board connection method
KR100545008B1 (en) Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same
US7537961B2 (en) Conductive resin composition, connection method between electrodes using the same, and electric connection method between electronic component and circuit substrate using the same
KR101179744B1 (en) Flip chip mounting process and flip chip assembly
JP4477062B2 (en) Flip chip mounting method
US20050218517A1 (en) Semiconductor flip-chip package and method for the fabrication thereof
CN101156238B (en) Methods for manufacturing protruding electrode for connecting electronic component and electronic component mounted body
WO2006112384A1 (en) Protruding electrode for connecting electronic component, electronic component mounted body using such electrode and methods for manufacturing such electrode and electronic component mounted body
JP5173214B2 (en) Electrically conductive resin composition and method for connecting electrodes using the same, and electrical connection method for electronic component and circuit board
WO2006098196A1 (en) Package equipped with semiconductor chip and method for producing same
TW200839968A (en) Conductive ball-or pin-mounted semiconductor packaging substrate, method for manufacturing the same and conductive bonding material
WO2010084858A1 (en) Surface mounting method for component to be mounted, structure with mounted component obtained by the method, and liquid epoxy resin composition for underfill used in the method
US7119000B2 (en) Method of manufacturing semiconductor device
JP2001332583A (en) Method of mounting semiconductor chip
JP2004288785A (en) Joint structure and joining method of electric conduction projection
US20010025874A1 (en) Method of forming solder bumps, method of mounting flip chips, and a mounting structure
JP4055556B2 (en) Manufacturing method of semiconductor device
JP2003086626A (en) Electronic component and manufacturing method thereof, and packaged body and packaging method for electronic component
JPH1187424A (en) Semiconductor device and production thereof
JPH10112515A (en) Ball grid array semiconductor device and its manufacture
JP2000058597A (en) Method of mounting electronic component
JP3078781B2 (en) Semiconductor device manufacturing method and semiconductor device
JPH11186454A (en) Bga type integrated circuit parts, manufacture of the parts and method for mounting the parts
KR20100067702A (en) Fabricating method for solder ball having adhesion coating layer and the same

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20040610

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20040610

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050921

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070523

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070605

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070731

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070828

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071024

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071120

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071203

R150 Certificate of patent or registration of utility model

Ref document number: 4055556

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101221

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121221

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121221

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131221

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees