JP2004165346A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is low in resistance value, operationally balanced well, and has a dual gate structure. <P>SOLUTION: The semiconductor device having a dual gate structure is equipped with a semiconductor substrate, a first transistor provided with a first electrode and a first conductivity-type channel diffusion region formed on the semiconductor substrate, and a second transistor provided with a second electrode and a second conductivity-type channel diffusion region formed on the semiconductor substrate. The first gate electrode and/or the second gate electrode is formed of substituted metal material containing a work function regulating metal, and the substituted metal material containing the work function regulating metal has a work function to enable a corresponding transistor to operate on a threshold voltage nearly symmetrical to that of the other transistor. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure and a method of manufacturing a dual gate transistor using a replacement metal gate.
[0002]
[Prior art]
With the development of high-capacity high-speed communication and the spread of high-performance portable information terminals, high integration and high functionality of semiconductor devices are strongly desired from the market. In order to meet such a demand, it is necessary to improve the performance of the transistors constituting the semiconductor device in addition to the improvement of the function of the semiconductor device itself. One way to improve the performance of a transistor is to use a metal gate. Metal gates are expected to contribute to higher speed and higher performance of transistors because they can significantly reduce the parasitic resistance of the gate and avoid the problem of gate depletion.
[0003]
In order to reduce the parasitic resistance of the transistor and enable high-speed operation, it is inherently desirable that the gate electrode be formed of a material having low resistance, particularly a metal material. However, considering the manufacturing process of the transistor, after forming the gate electrode, a high-temperature heat treatment of 900 ° C. or more for activating the impurities implanted into the source / drain is required. Forming with low metals has been considered difficult. Further, even if the gate electrode is made of a high melting point metal or a high melting point metal silicide, the damage due to the high temperature heat treatment that the resistance itself becomes high or the contact resistance becomes high cannot be avoided.
[0004]
In order to solve this problem, a technique has been proposed in which a gate electrode is formed in advance of a heat-resistant material such as polysilicon, and is replaced with a low-resistance metal such as aluminum (Al) after a high-temperature heat treatment (for example, Patent Document 1). 1 to 6).
[0005]
When such a metal substitution technique is used, a high-temperature heat treatment on the metal electrode is avoided, and finally the gate electrode of the transistor can be formed of a substitution metal material, for example, aluminum (Al) having a low resistance.
[0006]
[Patent Document 1]
JP-A-11-97535
[0007]
[Patent Document 2]
JP-A-10-308515
[0008]
[Patent Document 3]
JP-A-11-261603
[0009]
[Patent Document 4]
Japanese Patent Application No. 11-192011
[0010]
[Patent Document 5]
JP 2001-274379 A
[0011]
[Patent Document 6]
JP-A-10-368146
[0012]
[Problems to be solved by the invention]
By the way, as a device suitable for low power consumption and high integration in recent years, a CMOS device is considered to be an effective circuit type. FIG. 1A shows an example in which a conventionally proposed substituted Al gate structure is applied to a CMOS 1000 as a high-performance transistor. FIG. 1B is a cross-sectional view taken along the line a-a 'or the line b-b' in FIG. The CMOS 1000 includes a P-type MOSFET (hereinafter simply referred to as a PMOS) forming a P-type channel and an N-type MOSFET (hereinafter simply referred to as an NMOS) forming an N-type channel. It has a replacement metal gate 1003 as a material. The source / drain region 1004 of each MOSFET is connected to an upper wiring 1005 via a plug 1007.
[0013]
However, simply applying the conventional replacement Al gate structure to the CMOS 1000 cannot cope with the dual gate structure, which is the mainstream of recent CMOS devices. In recent high-performance semiconductor devices, both the PMOS and the NMOS are constituted by surface-type transistors. This is because the surface-type transistor has little deterioration in performance with respect to miniaturization of the transistor (such as a short channel effect accompanying miniaturization of the gate length). Therefore, even when replacement with a metal gate is performed, a surface-type transistor is desired as a precondition. In a surface-type transistor, impurities are usually implanted using the gate electrode as a mask when forming the source / drain. At this time, the gate electrode of the N-type transistor is doped N-type and the electrode of the P-type transistor is doped P-type. You.
[0014]
FIG. 2 is a graph showing a shift in threshold voltage Vth of an NMOS and a PMOS in which a gate electrode is formed by using a conventional replacement Al gate technique. FIG. 2A shows the Vth shift of the NMOS, and FIG. 2B shows the Vth shift of the PMOS. In each graph, the broken line indicates the current-voltage characteristic of the corresponding conductivity-doped polysilicon gate, and the solid line indicates the current-voltage characteristic of the substituted Al gate.
[0015]
In consideration of the operation balance of the CMOS, the value of the threshold voltage Vth of the NMOS of the replacement metal gate should be substantially equal to that of the threshold voltage Vth of the replacement metal gate of the PMOS. Therefore, for example, in a design corresponding to a polysilicon gate, the NMOS of the replacement metal gate has substantially the same threshold voltage Vth as the transistor using N-type polysilicon as the gate electrode, and the PMOS of the replacement metal gate uses the P-type polysilicon. The threshold voltage Vth should be substantially equal to the transistor used for the gate electrode. However, as shown in FIGS. 2A and 2B, an NMOS using an Al-substituted gate has a threshold voltage Vth close to that of an N-type polysilicon gate electrode. And a threshold voltage shift of as much as 0.7 V with respect to the polysilicon gate electrode. This is a major problem in terms of operation balance.
[0016]
[Means for Solving the Problems]
In order to solve the above-mentioned problem and to apply the replacement metal gate to a high performance semiconductor device well, in order to maintain the operation balance between the PMOS and the NMOS, the final N-type transistor and the P-type transistor after the metal replacement are replaced. It is necessary to keep the absolute values of the threshold voltages almost equal.
[0017]
For example, when the present invention is applied to a current CMOS design, the gate electrode of an N-type transistor is formed of metal having substantially the same work function as N-type polysilicon, and the gate electrode of a P-type transistor is formed of P-type polysilicon. It is desired to realize a dual-gate structure by forming a metal having substantially the same work function as silicon.
[0018]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a dual gate configuration that achieves a low resistance and has a small threshold voltage difference between a PMOS and an NMOS even after metal replacement and has a well-balanced operation. .
[0019]
Another object is to provide a method for efficiently manufacturing such a semiconductor device.
[0020]
In order to suppress the threshold voltage difference, a transistor having a large voltage shift (for example, a PMOS) is connected to the gate electrode so that this transistor can operate at a threshold voltage substantially symmetrical to the threshold voltage of the other transistor. It is necessary to introduce a metal material having an appropriate work function. In addition, in order to avoid high-temperature heat treatment at the time of transistor formation, it is preferable to assume metal replacement for replacing a base metal and a replacement metal after high-temperature heat treatment. In view of these points, a method is proposed in which a metal material having a different work function is introduced into a gate base material of a corresponding conductivity type transistor after a high-temperature heat treatment to form a dual gate.
[0021]
As a method of introducing metal materials with different work functions to the gate,
(1) Based on the aluminum (Al) substitution method, another metal whose work function can be adjusted is mixed with aluminum, and the metal for work function adjustment is injected into the base material together with the diffusion of aluminum at the time of aluminum substitution.
(2) One of the dual gates is a replacement metal gate using a first replacement metal material or a replacement metal material containing a work function adjusting metal, and the other is a second metal different from silicide or the first replacement metal material. The work function of both gate electrodes is adjusted by using the material electrodes.
There is a method that can be considered.
[0022]
Based on such a principle, according to a first aspect, a semiconductor device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate and having a first gate electrode and a channel diffusion region of a first conductivity type, A second transistor formed on the substrate and having a channel diffusion region of a second conductivity type, wherein at least one of the first and second gate electrodes includes a work function adjusting metal-containing metal; The replacement metal material made of a metal material and containing a work function adjusting metal has a work function in which the threshold voltage of the corresponding transistor is substantially symmetric with the threshold voltage of the other transistor.
[0023]
With this configuration, the resistance of the gate electrode is reduced, the shift of the threshold voltage between the first transistor and the second transistor is avoided, and the dual gate having a well-balanced operation and a work function appropriate for the corresponding transistor is provided. A semiconductor device having a structure is realized.
[0024]
According to a second aspect of the present invention, a semiconductor device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate, the first transistor having a first gate electrode and a channel diffusion region of a first conductivity type, and a semiconductor device formed on the semiconductor substrate. A second transistor of a second conductivity type having a channel diffusion region of the second conductivity type, wherein one of the first and second gate electrodes is formed of a replacement metal material or a work material. The other gate electrode is made of a silicide, and the silicide works so that the threshold voltage of the corresponding transistor is substantially symmetric with the threshold voltage of the one transistor. Has a function.
[0025]
According to this configuration, the resistance of the gate electrode is reduced, and at the same time, the shift of the threshold voltage due to the shift of the work function is avoided, and the dual gate structure in which the operation is balanced between the first and second transistors is achieved. Semiconductor device can be realized.
[0026]
As a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a dual gate structure with balanced operation. The method for manufacturing a semiconductor device includes:
(A) A first transistor having a first initial gate electrode and a channel diffusion region of a first conductivity type on a semiconductor substrate, and a first transistor having a second initial gate electrode and a channel diffusion region of a second conductivity type. Forming two transistors;
(B) forming at least one of the first and second initial gate electrodes by a heat treatment with a replacement metal material containing a work function adjusting metal to form a work function adjusting metal-containing replacement metal gate electrode;
The work function adjusting metal-containing replacement metal material has a work function in which the threshold voltage of the transistor corresponding to the work function adjusting metal-containing replacement metal gate electrode is substantially symmetric with the threshold voltage of the other transistor. Is selected to have
[0027]
In this method, an initial gate electrode is used at the time of forming a transistor involving high-temperature heat treatment, and then the initial gate electrode is replaced with a gate electrode of a work function adjusting metal-containing metal having a work function appropriate for the corresponding transistor. Therefore, a semiconductor device having a gate electrode with lower resistance is manufactured by avoiding high-temperature heat treatment. In addition, the gate electrode made of the replacement metal has a work function that allows the corresponding transistor to operate at a threshold voltage substantially symmetrical to the threshold voltage of the other transistor, so that the operation balance between the first and second transistors is maintained. Is maintained.
[0028]
According to a fourth aspect of the present invention, a method of manufacturing a semiconductor device includes:
(A) A first transistor having a first initial gate electrode and a channel diffusion region of a first conductivity type on a semiconductor substrate, and a first transistor having a second initial gate electrode and a channel diffusion region of a second conductivity type. Forming two transistors;
(B) exposing at least a part of a first initial gate electrode and at least a part of the second initial gate electrode simultaneously or individually;
(C) forming a first metal layer at an exposed portion of the first initial gate electrode;
(D) forming a metal layer containing a work function adjusting metal or a second metal layer different from the first metal layer at an exposed portion of the second initial gate electrode;
(E) performing a heat treatment to replace the first initial gate electrode with a first replacement metal gate electrode, and to replace the second initial gate electrode with a threshold voltage of a corresponding second transistor; Substituting a second replacement gate electrode having a work function that is substantially symmetric with the threshold voltage of the first transistor later;
including.
[0029]
The replacement of the first initial gate electrode and the replacement of the second initial gate electrode may be performed simultaneously in the same heat treatment step. Thus, a semiconductor device can be manufactured quickly.
[0030]
When the second metal layer is formed at the exposed portion of the second initial gate electrode, the second initial gate electrode is replaced with a replacement metal gate electrode or a silicide electrode depending on the type of metal material used and the heat treatment temperature. In any case, the corresponding second transistor has a work function capable of operating at a threshold voltage substantially symmetric to the threshold voltage of the other first transistor, and has a lower resistance value than the second initial gate electrode. Have.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
First, before describing an embodiment of the present invention, a metal replacement method using a replacement metal containing a work function adjusting metal will be described.
[0032]
FIG. 3 is a diagram for explaining a method of metal replacement by the replacement metal material 1 containing the work function adjusting metal 3. As an example, a description will be given based on an example in which aluminum (Al) is used as a replacement metal and a polysilicon gate electrode is replaced. In this case, in the PMOS, the difference in work function between the P-type doped polysilicon gate electrode and the Al gate electrode after metal replacement becomes large, and the operation balance with the NMOS is disturbed. In order to eliminate this difference in work function, the work function adjustment metal is used in the metal replacement process so that the work function of the final replacement metal gate is substantially equal to the work function of the P-type doped polysilicon gate. 3 is introduced. That is, at least a part of the polysilicon (base material) gate used as the initial gate electrode is exposed, and a low-temperature heat treatment is applied to the flow of the diffusion of the substituted aluminum (Al) material 1 so that the work function adjusting metal is removed from the exposed portion. 3 is diffused into polysilicon (base material).
[0033]
The type and content of the work function adjusting metal 3 are selected in accordance with the basic substitution metal material and the target work function. Also, Co, Ni, Ru, Ir, Cr, Cu, Pd, Ot, Os, Re, Rh, W, Ag, Au, Mo, Fe, Ru, etc., having a large work function are used.
[0034]
When the work function adjusting metal 3 is introduced along with the flow of the diffusion of the substituted Al material, the replacement distance of the work function adjusting metal 3 is much longer than the simple diffusion length of the work function adjusting metal, and the low-temperature annealing is performed. Also spread over the entire gate electrode. The work function adjusting metal 3 may be contained in the substituted Al material 1 in advance, or may be laminated with the substituted Al material 1 in a state before the substitution. By the heat treatment, the work function adjusting metal 3 is diffused together with the replacement metal 1 to adjust the work function of the final replacement metal gate, thereby realizing a dual gate with a well-balanced operation.
[0035]
This method is not limited to adjustment of the work function (or threshold voltage) of the PMOS gate, but can be used for the purpose of correcting a slight shift of the work function of the NMOS. The substitution metal material for diffusing the work function adjusting metal is not limited to aluminum (Al), but aluminum has a lower resistance of 2.7 μΩcm than other metals, and achieves a lower resistance of the gate electrode. easy. In addition, since the substitution distance of Al substitution is extremely long, even a long gate can be substituted at a practical temperature and time.
[0036]
Hereinafter, a specific embodiment of a dual gate configuration using a substitution metal material containing such a work function adjusting metal will be described.
[0037]
[First Embodiment]
FIG. 4 is a diagram illustrating a configuration of the semiconductor device 10 according to the first embodiment of the present invention. The semiconductor device 10 includes an NMOS (first transistor) forming an N-type channel and a PMOS (second transistor) forming a P-type channel on a silicon (Si) substrate 11. At least one has a replacement metal gate electrode containing a work function adjusting metal such that the threshold voltage characteristic of the other transistor is substantially symmetric. In the example of FIG. 4, the current CMOS design is maintained as it is, and the gate material is replaced with a replacement metal material. The NMOS is a gate electrode 26 of replacement aluminum (Al), and the PMOS contains a work function adjusting metal. It is composed of a gate electrode 28 of substituted Al. In this case, the work function of the work function adjusting metal-containing Al gate electrode 28 is substantially equal to the work function of P-type doped silicon.
[0038]
When aluminum (Al) is used as the basic replacement metal material of the PMOS gate electrode 28, the work function adjusting metal introduced together with Al into the PMOS gate electrode is aluminum (Al) such as Co, Ni, Ru, Ir, and Pt. It is desirable that the metal has a larger work function than that of the metal. As a result, the work function of the replacement metal gate containing the work function adjusting metal in the PMOS becomes substantially equal to the work function of the P-type polysilicon gate, and the shift (voltage shift) from the absolute value of the threshold voltage of the NMOS is eliminated. Thus, the operating characteristics of the CMOS can be balanced.
[0039]
4A to 4C show an example of connection between the substituted Al electrode 26 of the NMOS and the substituted Al gate electrode 28 containing the work function adjusting metal of the PMOS to the upper wiring 38. Keep it.
[0040]
5 to 13 are views showing a manufacturing process of the semiconductor device 10 having the dual gate structure shown in FIG. 5 and 6 are the same as those in the conventional CMOS process, and therefore will be described only briefly.
[0041]
(1) First, as shown in FIG. 5A, in the same manner as in the manufacture of a normal semiconductor device, an element isolation region (STI) 12 and a well diffusion region are formed in a semiconductor substrate region such as a silicon (Si) substrate 11, for example. 18 is formed. The substrate is not limited to the Si substrate, and an SOI (silicon-on-insulator) substrate may be used.
[0042]
(2) Next, the gate insulating film 13 is formed. As the gate insulating film 13, an insulating film obtained by oxidizing and nitriding the surface of the semiconductor substrate 11, a High K dielectric film formed by a CVD method, or the like can be used.
[0043]
(3) On the gate insulating film 13 and the Si substrate 11, a polysilicon film 14 is formed as a base material of an initial gate electrode by a CVD method.
[0044]
(4) The deposited polysilicon film 14 is processed into a convex electrode shape using a lithography method and an etching method to form an initial gate electrode 14. In addition, ion implantation for forming the LDD (or extension) 15 is performed and activated by a later heat treatment.
[0045]
(5) After forming the insulating film by the CVD method, anisotropic etching is performed, and the sidewall 17 is left on the side wall of the gate electrode. Ion implantation for forming the high concentration source / drain 16 is performed, and activation of impurities is performed by a heat treatment performed later. At this time, the polysilicon gate 14 on the P-type well is_N  To N-type, polysilicon gate 14 on N-type well_P  May be doped into a P-type, or when the cap insulating film is left on the polysilicon film 14 in the above step (4), the polysilicon gate 14 may be used._P, 14_NMay be non-doped. In the latter case, after a cap insulating film such as an oxide film is formed on the polysilicon film 14, the cap insulating film and the polysilicon film are collectively processed into a gate shape. This is because the initial gate electrode is replaced with a replacement metal material in a later step, and it is not necessary to consider the conductivity and resistance at this stage, and it is not always necessary to dope.
[0046]
(6) Next, in order to form a plug for connecting the source / drain 16 and the upper wiring, an insulating film 21 is deposited to completely cover the gate electrode 14 and a hole reaching the source / drain 16 is formed. First, a Ti film is formed on the inner wall of the hole, a TiN film is formed thereon, and a barrier metal 19 is formed.
[0047]
(7) Then, as shown in FIG. 6 (7), the inside of the hole is filled with tungsten (W).
[0048]
(8) The surface is polished until it reaches the insulating film 21 to form a plug 23.
[0049]
(9) Next, as shown in FIG. 6 (9), the polysilicon gate electrode 14 of the NMOS_N  A resist mask 25 having a pattern shape having an opening on the top of the substrate is formed. The cross-sectional view taken along the line a-a 'of FIG._N  3 shows an example of a pattern shape of a resist mask 25 having an opening on the upper side.
[0050]
(10) Next, as shown in the a-a 'sectional view of FIG._N  Is formed. Thereby, a part of the polysilicon gate electrode of the NMOS is exposed. At this time, the polysilicon gate electrode 14 of the PMOS is used._P  Is still covered with the insulating film 21 (b-b 'sectional view).
[0051]
(11) Next, as shown in a sectional view taken along the line a-a 'in FIG. 8 (11), the gate opening 24 is buried, and aluminum (Al) 26 is deposited on the entire surface of the wafer as a replacement metal material. On the Al film 26, a titanium (Ti) 27 serving as a so-called blotting paper for efficiently sucking silicon (Si) is formed. Ti is formed for the purpose of increasing the efficiency of Al substitution, and can be omitted when the thickness of the Al film 26 is increased. As shown in the cross-sectional view taken along the line b-b ', the polysilicon gate electrode 14 of the PMOS covered with the insulating film 21 is formed._P  , An Al film 26 and a Ti film 27 are sequentially deposited.
[0052]
(12) Next, as shown in FIG. 9 (12), annealing is performed at about 400 ° C. for Al substitution. By this low-temperature heat treatment, silicon (Si), which is a gate base material of the NMOS, and Al interdiffuse, and the polysilicon gate electrode 14 is replaced with Al (a-a 'cross-sectional view). The replacement is promoted by the Ti film 27 on the Al film 26, and the replacement can be performed in a short time by performing annealing at a relatively low temperature. At this time, the polysilicon gate electrode 14 of the PMOS is used._P  Is immobile (b-b 'sectional view).
[0053]
(13) Next, as shown in FIG. 10 (13), CMP or etch back is performed to remove the titanium film 27 and the replacement metal (Al) 26 on the surface.
[0054]
(14)-(16) Next, as shown in FIGS._P  Is replaced with a work function adjusting metal-containing Al material 28. That is, the PMOS polysilicon gate electrode 14_P  Is formed, and a work function adjusting metal-containing Al film 28 and a titanium (Ti) film 29 are formed inside the gate opening 24 'and on the entire surface of the wafer. Annealing is performed at about 400 ° C., and the work function adjusting metal is diffused into the polysilicon gate along with the diffusion flow of aluminum (Al). The absorption of silicon (Si) is promoted by the upper Ti film 29.
[0055]
In the first embodiment, the work function adjusting metal corrects the work function in the direction of eliminating the threshold voltage shift of the PMOS, so that Co, Ni, Ru, Ir, Cr, Cu, Pd, Pt, Os, Re, Rh, W, Ag, Au, Mo, Fe, Ru, or the like is used. Although the work function adjusting metal-containing Al material 28 is depicted as a single layer in the example of FIG. 11, the work function adjusting metal containing metal layer may be a stacked layer of the Al layer and the work function adjusting metal layer.
[0056]
(17) Next, as shown in FIG. 12, the work function-containing metal Al material 28 on the surface is removed by CMP or etch back. As a result, a dual gate having a gate electrode 26 made of a substituted Al material for an NMOS and a gate electrode 28 made of an Al material containing a work function adjusting metal is completed for a PMOS.
[0057]
(18) Finally, as shown in FIG. 13, the wiring layers 36 and 38 are formed via the TiN film 39, for example, to complete the semiconductor device 10 having the dual gate structure. In the semiconductor device of the first embodiment, the work function of the substituted Al gate electrode 26 of NMOS is substantially equal to the work function of N-type silicon, and the work function adjusting metal-containing Al gate electrode 28 of PMOS is substantially equal to the work function of P-type silicon. And the threshold voltages Vth of both become almost symmetrical (the signs are opposite and the absolute values are almost equal). This provides a low-resistance, high-performance semiconductor device with a well-balanced operation while avoiding a threshold voltage shift.
[0058]
[Second embodiment]
14 to 16 are views showing the steps of manufacturing the semiconductor device according to the second embodiment of the present invention. In the first embodiment, first, the polysilicon gate of the NMOS is replaced with the replacement Al material 26, and then, in a separate step, the polysilicon gate of the PMOS is replaced with the work function adjusting metal-containing Al material 28. That is, a similar process was repeated twice in order to replace one gate electrode with a single Al material and to introduce a work function adjusting metal together with the substituted Al material into the other gate electrode.
[0059]
In the second embodiment, in order to shorten the manufacturing process and efficiently manufacture a dual gate, the metal replacement of the substituted Al material 26 and the work function adjusting metal-containing Al material 28 in the NMOS and the PMOS is performed by a single annealing process. At the same time. Steps (1) to (9) are the same as those in the first embodiment, and a description thereof will not be repeated, and will be described from step (10).
[0060]
(10) When performing metal replacement, as shown in the a-a 'section and the b-b' section of FIG. 14 (10), the polysilicon initial gate electrode 14 of the NMOS and PMOS transistors is used._N, 14_PGate openings 24, 24 'are formed.
[0061]
(11) Next, as shown in FIG. 15 (11), a work function adjusting metal-containing Al material 28 is formed in the gate opening 24 'provided in the PMOS and its peripheral region. The gate opening 24 provided in the NMOS and its peripheral region are exposed without being covered with the work function adjusting metal-containing Al material 28. Specifically, first, the work function adjusting metal-containing Al material 28 is formed on the entire surface. Then, by a lithography process and an etching process, the work function adjusting metal-containing Al material 28 is removed so as to remain in and around the gate opening 24 ′ of the PMOS. As a result, as shown in the a-a 'cross-sectional view, the gate opening 24 of the NMOS remains exposed.
[0062]
(12) Next, as shown in FIG. 16 (12), a substituted Al material 26 is formed on the entire surface. The Al material 26 fills the NMOS gate opening 24 and covers the work function adjusting metal-containing Al material 28 formed in the previous step, as shown in the a-a 'sectional view and the b-b' sectional view. Further, if necessary, a Ti film 27 may be formed on the Al material 26 to promote absorption of silicon (Si) from the polysilicon gate electrode 14 over the entire surface. Note that a material that easily forms silicide, such as Co, Ni, Ru, and Pt, can be used as the absorber instead of Ti. In this state, annealing for metal replacement is performed at about 400 ° C. As a result of this annealing process, in the NMOS, silicon (Si) and Al interdiffuse as shown in the a-a 'cross-sectional view, and the gate electrode 14_NIs replaced by the substituted Al material 26. On the other hand, in the PMOS, as shown in the cross-sectional view taken along the line b-b ', the work function adjusting metal flows from the gate opening 24' to the polysilicon gate electrode 14 through the diffusion flow of Al._PInto the gate electrode 14_PIs replaced by the work function adjusting metal-containing Al material 28.
[0063]
In the case of the second embodiment, the PMOS gate electrode 14_PSince the work function adjusting metal Al material 28 and the substituted Al material 26 are laminated on the gate opening 24 ', it is desirable to adjust both film thicknesses in consideration of the final mixing ratio.
[0064]
The subsequent steps, that is, the removal of the replacement metal layer, the planarization of the surface, and the formation of the upper wiring are the same as those in the step (17) of the first embodiment, and thus the description thereof is omitted. In the second embodiment, the work function adjusting metal Al material 28 is left around the opening 24 'and the replacement Al film 26 is formed on the entire surface thereof. However, the upper and lower relationship may be reversed. That is, the replacement Al material 26 may be formed on the entire surface, and the work function adjusting metal Al material 28 may be left only around the opening 24 ′ thereon.
[0065]
As described above, according to the second embodiment, both the NMOS and the PMOS gate electrodes can be simultaneously replaced with the replacement metal materials having different work functions by a single annealing process. Further, since the formation of the gate opening and the CMP step accompanying the metal replacement can be performed only once, the number of steps in the entire manufacturing process can be greatly reduced. As a result, a dual-gate configuration with a well-balanced operation while maintaining the symmetry of the threshold voltage characteristics between the PMOS and the NMOS is efficiently realized.
[0066]
[Third embodiment]
17 to 21 are views showing the steps of manufacturing the semiconductor device according to the third embodiment of the present invention. In the second embodiment, in the PMOS, metal replacement is performed by annealing while the replacement Al material 28 is laminated on the work function adjusting metal-containing Al material 26. In the third embodiment, the replacement Al material 26 formed for NMOS and the work function adjusting metal-containing Al material 28 formed for PMOS are arranged so as not to overlap with each other, and the corresponding polysilicon is formed independently of each other. The gate 14 is replaced with metal. Thus, the replacement of the metal of the gate electrodes of both MOS transistors is performed by a single annealing process while preventing the replacement metal material from being mixed due to the overlap. Steps (1) to (9) are the same as in the first embodiment, and a description thereof will be omitted.
[0067]
(10) After plug formation in the previous step, gate openings 24 and 24 'reaching the polysilicon gate electrode 14 are formed in the NMOS and the PMOS, as shown in FIG.
[0068]
(11) Next, as shown in FIG. 18 (11), a work function adjusting metal-containing Al material 28 is formed in and around the gate opening 24 'of the PMOS. Specifically, first, a work function adjusting metal-containing Al material 28 is formed on the entire surface, and the lithography and etching techniques are used to leave the work function adjusting metal-containing Al material 28 only on the PMOS gate opening 24 ′ and to form the NMOS gate. It is removed from above the opening 24.
[0069]
(12) Next, as shown in FIG. 19 (12), a replacement Al material 26 is deposited on the entire surface. In the gate opening 24 ′ of the PMOS, the substituted Al material 26 is deposited on the work function adjusting metal-containing Al material 28 so as to overlap.
[0070]
(13) Next, as shown in FIG. 20 (13), the substituted Al material 26 is removed from above the PMOS gate opening 24 'by lithography and etching techniques, leaving only the NMOS gate opening 24. . As a result, the gate opening 24 of the NMOS and the gate opening 24 'of the PMOS are independently covered with the corresponding replacement materials 26 and 28, respectively. For the processing of the substituted Al material 26, CMP may be used instead of the method using lithography and etching. In this case, the surface is first lightly polished by CMP. As a result, only the substituted Al material 26 rising above the height of the substituted Al material on the NMOS above the PMOS is polished. This polishing is performed until the surface of the work function adjusting metal-containing Al material 28 is exposed and is equal to the surface height of the replacement Al material 26 on the PMOS side. When the lithography and etching techniques are used, as shown in FIG. 20, a region of the substitution aluminum material 26 on the NMOS and a region of the substitution aluminum material 28 on the PMOS are formed at an interval. If so, the two regions remain adjacent. However, there is no change in the effect of the replacement by annealing in a later step.
[0071]
(14) Next, as shown in FIG. 21 (14), a Ti film 27 for promoting substitution is formed, and an annealing process is performed at about 400 ° C. By this heat treatment, the NMOS polysilicon gate electrode 14 is formed._NRepresents the PMOS gate electrode 14 of the PMOS_PIs replaced by a work function adjusting metal-containing Al electrode.
[0072]
According to the third embodiment, materials are not mixed into the gate electrodes of the respective MOS transistors, the accuracy of work function adjustment is improved, and the reliability of operation as a CMOS device is further improved.
[0073]
[Fourth embodiment]
FIG. 22 to FIG. 27 are views showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention. In the fourth embodiment, unlike the first to third embodiments, the entire surface area of the polysilicon (base material) gate electrode is exposed without forming the gate openings 24 and 24 ′ in the interlayer insulating film 21. Perform metal replacement.
[0074]
FIG. 22 (5) ′ is a step that follows the step (5) (FIG. 5 (5)) in the first embodiment. That is, after the interlayer insulating film 21 is deposited, the polysilicon initial gate electrode 14 of NMOS and PMOS is deposited._N, 14_P  Is planarized so that the surface of the insulating film 21 is exposed.
[0075]
(6) Next, a contact hole reaching the source / drain 16 of the NMOS and the PMOS is formed in the insulating film 21, and a Ti film and a TiN film are sequentially formed on the inner wall of the contact hole as an adhesion layer to form a barrier metal 19. .
[0076]
(7) After filling the contact hole with tungsten (W) 23 via the barrier metal 19, as shown in FIG. 23 (10), the tungsten (W) 23 is_N, 14_P  Is flattened until the surface is exposed.
[0077]
(11) Next, as shown in FIG. 24 (11), the exposed polysilicon gate electrode of the PMOS_P  Then, the work function adjusting metal-containing Al material 28 is formed so as to cover the surroundings. The partial coating with the work function adjusting metal-containing Al material 28 is the same as the process (11) of the second embodiment shown in FIG.
[0078]
(12) Next, as shown in FIG. 25 (12), a substituted Al material 26 and a Ti film 27 for promoting substitution are formed on the entire surface. Thereby, the polysilicon gate electrode 14 of the PMOS is formed._P  Is coated with a work function adjusting metal-containing Al material 28, and the NMOS polysilicon gate electrode 14_NIs coated with the substituted Al material 26. In this state, annealing is performed at about 400 ° C., and metal replacement is performed simultaneously on the PMOS and NMOS gate electrodes.
[0079]
Next, as shown in FIGS. 26 (13) and 27 (14), the upper layer Ti film 27, the substituted Al material 26 and the work function adjusting metal The Al material 28 is removed, and a substituted Al gate electrode 26 of NMOS and an Al gate electrode 28 containing a work function adjusting metal of PMOS are formed. Then, an upper wiring 36 connected to the source / drain 16 and an upper wiring 38 connected to the respective gate electrodes 26 and 28 are formed.
[0080]
According to the fourth embodiment, there is no need to form a gate opening for exposing the gate electrode in another step. In addition, the contact area between the polysilicon gate 14, which is the base material to be replaced, and the replacement material is widened, and the replacement by the interdiffusion between silicon and the metal material, and the work function adjusting metal on the flow of the diffusion of the replacement metal material. Adoption proceeds more quickly
Similar to the third embodiment, the manufacturing process of the fourth embodiment is a method of independently forming the corresponding replacement metal material 26 and the work function adjusting metal-containing metal material 28 so as not to overlap with each other for the NMOS and the PMOS. Also applicable to Also in this case, the metal replacement of the gate electrodes of the NMOS and the PMOS can be performed simultaneously by a single annealing.
[0081]
28 to 30 are views showing a modification of the method for manufacturing the semiconductor device according to the fourth embodiment. In a modified example, a gate opening 24 reaching one of the polysilicon gate electrodes (for example, NMOS) is formed in the interlayer insulating film 21 over the entire surface region of the gate electrode, and metal replacement is performed. Next, a gate opening reaching the polysilicon gate of the other (for example, PMOS) is formed over the entire surface area of the gate electrode, and is replaced with a work function adjusting metal-containing metal material or a different replacement metal material. The process up to the step (9) of forming a resist mask 25 having an opening pattern on the interlayer insulating film 21 covering the polysilicon gate electrode 14 is the same as the manufacturing process of the first embodiment, and the shape of the opening pattern is Only different.
[0082]
(10) Using the resist mask 25, as shown in FIG._NThe gate opening 24 reaching the polysilicon gate electrode 14_NIs formed so that the surface region of the substrate is exposed almost entirely. At this time, the polysilicon gate electrode 14 of the PMOS is used._PRemains covered with the interlayer insulating film 21.
[0083]
(11) A replacement Al material 26 is formed inside the gate opening 24 and over the entire surface of the wafer. If necessary, a Ti film 27 for promoting substitution is formed on the Al material 26.
[0084]
(12) Anneal at about 400 ° C. to form an NMOS polysilicon gate electrode 14_NIs replaced with Al.
[0085]
(13) After the metal replacement, as shown in FIG. 29 (13), the Ti film 27 and the substituted Al material 26 are removed until the interlayer insulating film 21 is exposed.
[0086]
Next, although not shown, as steps (14) to (17), steps (10) to (13) are repeated for the PMOS, and the polysilicon gate electrode 14 is formed._PIs replaced with a work function adjusting metal-containing Al material 28.
[0087]
(18) Finally, as shown in FIG. 30 (18), upper wirings 36 and 38 are formed.
[0088]
[Fifth Embodiment]
FIG. 31 is a diagram of a semiconductor device 40 according to the fifth embodiment of the present invention. The semiconductor device 40 has, on a silicon (Si) substrate 11, an NMOS forming an N-type channel and a PMOS forming a P-type channel. The NMOS has a gate electrode 46 composed of a substituted Al material or a substituted Al material containing a work function adjusting metal (in the example of FIG. 31, the substituted Al material is used), and the PMOS has a gate electrode 48 of silicide. Have.
[0089]
Here, a distinction is made between silicide and metal substitution based on interdiffusion. Silicide is a compound of metal and silicon, and is obtained by chemically bonding metal atoms and silicon atoms at an integral multiple ratio. Aluminum (Al) is known not to constitute silicide, and the silicide electrode 48 is formed using a second metal other than aluminum (Al).
[0090]
On the other hand, metal substitution is due to diffusion and substitution of a metal into a crystal, and the final mixing ratio is not necessarily an integral multiple, and most of the mixture is replaced with a substituted metal material. For example, in the case of replacing silicon with aluminum (Al), it finally contains 0.4% silicon and 99.6% becomes Al. Even when Al contains a work adjustment metal, the work function adjustment metal is uniformly diffused and replaced, and ultimately almost becomes a substituted metal material including the work function adjustment metal.
[0091]
In the fifth embodiment, the entire gate electrode of silicide is configured as silicide not only at the head but also up to the gate insulating film. At this time, the work function of the PMOS silicide electrode 48 is selected so as to operate at a threshold voltage substantially symmetric to that of the NMOS. In the example of the fifth embodiment, the metal material of the silicide is selected to have a work function approximately equal to that of P-doped silicon. When the silicide electrode 48 is used for the PMOS as shown in FIG._xSi_y  , Ni_xSi_y  , Pt_xSi_y  For example, use a metal having a large work function.
[0092]
Even with the same silicide, by changing the ratio of x and y, a work function closer to the target work function can be obtained. Further, the work function can be further finely adjusted by adding boron (B), phosphorus (P), arsenic (As), antimony (Sb), iridium (Ir), or the like.
[0093]
Contrary to the example of FIG. 31, the NMOS gate electrode may be made of silicide and the PMOS gate electrode may be made of an Al material containing a work function adjusting metal. Also in this case, the material of the silicide material and the material of the work function adjusting medal are selected such that the threshold voltages of the PMOS transistor and the NMOS transistor have a work function that is substantially symmetric.
[0094]
The method for manufacturing the semiconductor device 40 of the fifth embodiment may employ any of the methods of the first to fourth embodiments. When the manufacturing method of the first embodiment or the modification of the fourth embodiment is adopted, the gate electrode of the substituted Al material of the NMOS or the Al material containing the work function adjusting metal and the silicide gate electrode of the PMOS are replaced by separate annealing steps. It is formed. Therefore, the metal replacement temperature and the reaction temperature for silicidation can be individually adjusted, and the degree of freedom in material selection is increased. When the heat treatment temperature for silicidation is higher than the treatment temperature for metal substitution, silicidation at one gate electrode is performed first, and then metal substitution at the other gate electrode is performed.
[0095]
When the manufacturing method of the second to fourth embodiments is used, the gate electrode 46 made of a substituted Al material or a substituted Al material containing a work function adjusting metal and the gate electrode 48 of silicide are formed simultaneously in the same annealing step. You. At this time, a first substitution metal material (for example, Al) is formed at an exposed portion of one (for example, NMOS) polysilicon initial gate electrode, and a first replacement metal material (for example, Al) is formed at an exposed portion of the other (for example, PMOS) polysilicon initial gate electrode. A second metal material different from the first replacement metal material is formed. By the same heat treatment, metal replacement proceeds by mutual diffusion of aluminum (Al) and silicon in one of the gates, and silicidation proceeds in the other gate by a chemical bond between the second metal other than Al and silicon. In this case, Co is used as silicide.₂Si, CoSi₂, Ni₂Si, NiSi, Pt₂Si, MoSi₂  When such a method is used, the silicidation is sufficiently performed at the metal replacement temperature (for example, about 400 ° C.).
[0096]
Note that Al may be included in the formation of the silicide electrode. For example, when annealing is performed by the method of the second embodiment, Al may further enter the place where the silicide is formed, but this may be the case. In this case, Al in silicide replaces Si in MxSiy (M means metal), so Al enters by the proportion of Si. For example, CoSi₂  May further enter, and finally about 70% of Al may enter.
[0097]
Further, when the fourth embodiment is applied, metal replacement and silicidation proceed from the entire surface of the initial gate electrode, so that independent metal replacement and silicidation in both gate electrodes are promoted.
[0098]
As a result, a complementary high-performance transistor circuit having a low resistance and a well-balanced operation is realized.
[0099]
[Other embodiments]
In the above-described embodiment, Al is used for the replacement metal, and since the threshold voltage shift hardly occurs in the NMOS, the gate electrode of the PMOS is replaced with an Al material to which a work function adjusting metal is added. However, when a substitute metal other than Al (for example, a metal material having a work function close to the work function of P-type polysilicon) is used, a dual gate is formed using a substitute metal material to which a work function adjusting metal is added on the NMOS side with reference to the PMOS. May be realized. In this case, a metal having a smaller work function than the replacement metal material used in the PMOS can be used as the work function adjusting metal.
[0100]
Further, in the first embodiment, the metal replacement of the NMOS gate electrode is first performed, and then the PMOS gate electrode is replaced with the replacement metal containing the work function adjusting metal. However, the order of the metal replacement is not limited to this. Instead, metal replacement of the PMOS gate electrode may be performed first.
[0101]
When the gate electrode of the NMOS is made of a substituted Al material, the work is performed by adding impurities such as boron (B), phosphorus (P), arsenic (As), antimony (Sb), and iridium (Ir). The function may be further fine-tuned.
[0102]
Further, in the first to fifth embodiments, instead of the replacement metal gate electrode to which the work function adjusting metal is added, or in place of the silicide gate electrode, the replacement metal gate is configured by a second metal having a different work function. Is also good. For example, the first replacement metal material can be aluminum (Al) and the second metal material can be Pt, Cu, Au, Ag, Pd, Ni, or the like.
[0103]
As for the base material on the side to be replaced, a single crystal, polycrystal, or amorphous form of SiGe, Ge, C, or the like can be adopted in addition to silicon (polysilicon).
[0104]
In these cases, the principle of metal replacement is the same, and there is no change in the fabrication process. However, in one transistor, a work function adjusting metal containing metal electrode or silicide electrode is replaced with a work function different from that of the other replacement metal electrode. Is formed. As a result, an operation balanced low resistance dual gate configuration having two gate electrodes with adjusted work functions is realized.
[0105]
Based on metal replacement technology, by introducing a work function adjusting metal into a base material in a diffusion flow of a basic replacement metal material, a replacement metal gate configuration can be widely applied not only to a dual gate but also to a hybrid CMOS. it can.
[0106]
In the above-described embodiment, at least one polysilicon gate electrode of the P-type transistor and the N-type transistor in the current CMOS design has been described based on an example in which a replacement metal material containing a work function adjusting metal is used. The function tuning metal was selected to be approximately equal to the work function of the corresponding conductivity type polysilicon. However, the present invention is not limited to this example, and it is only necessary to maintain the symmetry of the threshold voltage Vth at which the replaced NMOS and PMOS operate. Therefore, depending on the design, the threshold voltage Vth of the PMOS and NMOS may be reduced. A work function that can maintain balance can be selected. The threshold voltage Vth depends on the work function, but also on the impurity concentration on the semiconductor surface and the amount of electric charge on the sea surface. In contrast, a work function that operates at a threshold voltage such that the absolute values are equal may be selected.
[0107]
Finally, regarding the above description, the following supplementary notes are disclosed.
[0108]
(Supplementary Note 1) A semiconductor transistor, a first transistor formed on the semiconductor substrate and having a first gate electrode and a channel diffusion region of a first conductivity type, a second transistor formed on the semiconductor substrate, and a second transistor And at least one of the first and second gate electrodes is made of a substitution metal material containing a work function adjustment metal, and contains a work function adjustment metal. A semiconductor device, wherein the replacement metal material has a work function in which a threshold voltage of a corresponding transistor is substantially symmetric with a threshold voltage of another transistor.
[0109]
(Supplementary Note 2) A semiconductor substrate, a first transistor formed on the semiconductor substrate and having a first gate electrode and a channel diffusion region of the first conductivity type, a second transistor formed on the semiconductor substrate, and a second transistor And a second transistor of a second conductivity type having a channel diffusion region of the first conductivity type, wherein one of the first and second gate electrodes has a substitution metal material or a substitution metal material containing a work function adjusting metal. And the other gate electrode is formed of silicide, and the silicide has a work function such that the threshold voltage of the corresponding transistor is substantially symmetric with the threshold voltage of the one transistor. Semiconductor device.
[0110]
(Supplementary Note 3) The replacement metal material is aluminum, and the work function adjusting metal is Co, Ni, Ru, Ir, Cr, Cu, Pd, Pt, Os, Re, Rh, W, Ag, Au, Mo, 3. The semiconductor device according to claim 1, wherein the semiconductor device is selected from Fe.
[0111]
(Supplementary Note 4) The silicide is CoxSiy, TixSiy 4. The semiconductor device according to claim 2, wherein the semiconductor device is selected from the group consisting of RuxSiy, NixSiy, PtxSiy, and MoxSiy.
[0112]
(Supplementary Note 5) The replacement metal material containing the work function adjusting metal has a work function substantially equal to a work function of the semiconductor substrate material doped with the same conductivity type as a corresponding transistor. 13. The semiconductor device according to claim 1.
[0113]
(Supplementary note 6) The semiconductor device according to supplementary note 2, wherein the silicide has a work function substantially equal to a work function of the semiconductor substrate material doped to the same conductivity type as a corresponding transistor.
[0114]
(Supplementary Note 7) A first transistor having a first initial gate electrode and a channel diffusion region of a first conductivity type and a second initial gate electrode and a channel diffusion region of a second conductivity type are formed on a semiconductor substrate. Forming a second transistor;
Forming at least one of the first or second initial gate electrode by a heat treatment with a substitution metal material containing a work function adjustment metal to form a work function adjustment metal-containing substitution metal gate electrode;
Wherein the work function adjusting metal-containing replacement metal material has a work function in which a threshold voltage of a transistor corresponding to the work function adjusting metal-containing replacement metal gate electrode is substantially symmetric with a threshold voltage of the other transistor. A method of manufacturing a semiconductor device, wherein the method is selected to have:
[0115]
(Supplementary Note 8) A first transistor having a first initial gate electrode and a channel diffusion region of a first conductivity type, and a second initial gate electrode and a channel diffusion region of a second conductivity type are formed on a semiconductor substrate. Forming a second transistor;
Exposing at least a part of the first initial gate electrode and at least a part of the second initial gate electrode simultaneously or individually;
Forming a first metal layer at an exposed portion of the first initial gate electrode;
Forming a metal layer containing a work function adjusting metal or a second metal layer different from the first metal layer at an exposed portion of the second initial gate electrode;
By performing the heat treatment, the first initial gate electrode is replaced with a first replacement metal gate electrode, and the second initial gate electrode is replaced with the threshold voltage of the corresponding second transistor after the replacement. Replacing with a second replacement gate electrode having a work function that is substantially symmetric with the threshold voltage of one transistor;
A method for manufacturing a semiconductor device including:
[0116]
(Supplementary note 9) The method of manufacturing a semiconductor device according to supplementary note 8, wherein the replacement of the first initial gate electrode and the replacement of the second initial gate electrode are performed simultaneously in the same heat treatment step.
[0117]
(Supplementary Note 10) The method of manufacturing a semiconductor device according to Supplementary Note 8, wherein the replacement of the first initial gate electrode and the replacement of the second initial gate electrode are performed in separate heat treatment steps.
[0118]
(Supplementary Note 11) The semiconductor according to Supplementary Note 8, wherein the second replacement gate electrode is formed by performing a metal replacement of a second initial gate electrode with a second metal by the heat treatment. Device manufacturing method.
[0119]
(Supplementary Note 12) The supplementary note 8, wherein the second replacement gate electrode is formed by silicidizing a second initial gate electrode with the second metal by the heat treatment. A method for manufacturing a semiconductor device.
[0120]
(Supplementary note 13) The method for manufacturing a semiconductor device according to supplementary note 8, wherein the step of exposing the initial gate electrode exposes the entire surface of the initial gate electrode.
[0121]
(Supplementary Note 14) The method for manufacturing a semiconductor device according to supplementary note 8, wherein the first metal layer and the second metal layer are formed so as not to overlap with each other in a stacking direction.
[0122]
(Supplementary Note 15) The method for manufacturing a semiconductor device according to Supplementary Note 8, wherein the first metal layer and the second metal layer are formed so as to partially overlap in the stacking direction.
[0123]
(Supplementary Note 16) The first initial gate electrode is replaced with a first replacement metal gate electrode having a work function substantially equal to the work function of the first initial gate electrode, and the second initial gate electrode is replaced with the first initial gate electrode. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is replaced with a second replacement gate electrode having a work function substantially equal to the work function of the second initial gate electrode.
[0124]
【The invention's effect】
A semiconductor device having a dual-gate configuration with a well-balanced operation is realized while reducing the resistance of the gate electrode and eliminating a shift in threshold voltage.
[0125]
Further, the work function of the gate electrode can be adjusted with a high degree of freedom by utilizing the advantages of Al, which is an excellent metal replacement material.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example in which a conventional replacement metal gate is applied to a CMOS device.
FIG. 2 is a graph for explaining a threshold voltage shift that occurs when a conventional replacement metal gate is applied to a CMOS device and an imbalance in operation.
FIG. 3 is a diagram for explaining metal replacement using a replacement metal containing a work function adjusting metal according to the present invention.
FIG. 4 is a diagram of a semiconductor device having a dual gate structure using a substitution metal according to the first embodiment of the present invention.
FIG. 5 is a diagram (part 1) illustrating a process of manufacturing the semiconductor device according to the first embodiment;
FIG. 6 is a diagram (part 2) illustrating a process of manufacturing the semiconductor device according to the first embodiment, which is subsequent to step (6) in FIG. 5;
FIG. 7 is a diagram (part 3) illustrating a process of manufacturing the semiconductor device according to the first embodiment, which is subsequent to step (9) in FIG. 6;
FIG. 8 is a diagram (part 4) illustrating a step of manufacturing the semiconductor device of the first embodiment;
FIG. 9 is a diagram (part 5) illustrating a step of manufacturing the semiconductor device of the first embodiment;
FIG. 10 is a diagram (part 6) illustrating a step of manufacturing the semiconductor device of the first embodiment;
FIG. 11 is a view illustrating a manufacturing step (part 7) of the semiconductor device of the first embodiment;
FIG. 12 is a diagram (part 8) illustrating a process of manufacturing the semiconductor device according to the first embodiment;
FIG. 13 is a diagram (part 9) illustrating a step of manufacturing the semiconductor device of the first embodiment;
FIG. 14 is a diagram (part 1) illustrating a process of manufacturing the semiconductor device according to the second embodiment of the present invention, showing a step that follows the step (9) of FIG. 6;
FIG. 15 is a diagram (part 2) illustrating a process of manufacturing the semiconductor device of the second embodiment;
FIG. 16 is a diagram (part 3) illustrating a process of manufacturing the semiconductor device of the second embodiment;
FIG. 17 is a diagram (part 1) illustrating a step of manufacturing the semiconductor device according to the third embodiment of the present invention, illustrating a step that follows the step (9) in FIG. 6;
FIG. 18 is a diagram (part 2) illustrating a process of manufacturing the semiconductor device of the third embodiment;
FIG. 19 is a diagram (part 3) illustrating a process of manufacturing the semiconductor device of the third embodiment;
FIG. 20 is a view (part 4) illustrating a process of manufacturing the semiconductor device of the third embodiment;
FIG. 21 is a diagram (part 5) illustrating a step of manufacturing the semiconductor device of the third embodiment;
FIG. 22 is a diagram (part 1) illustrating a step of manufacturing the semiconductor device according to the fourth embodiment of the present invention, illustrating a step that follows the step (5) in FIG. 5;
FIG. 23 is a diagram (part 2) illustrating a process of manufacturing the semiconductor device of the fourth embodiment, illustrating a process of exposing the entire surface of the initial gate electrode in both the NMOS and the PMOS;
FIG. 24 is a diagram (part 3) illustrating a process of manufacturing the semiconductor device of the fourth embodiment;
FIG. 25 is a diagram (part 4) illustrating a step of manufacturing the semiconductor device of the fourth embodiment;
FIG. 26 is a diagram (part 5) illustrating a process of manufacturing the semiconductor device of the fourth embodiment;
FIG. 27 is a diagram (part 6) illustrating a process of manufacturing the semiconductor device of the fourth embodiment;
FIG. 28 is a diagram (part 1) illustrating a manufacturing process according to a modification of the fourth embodiment;
FIG. 29 is a diagram (part 2) illustrating a manufacturing process according to a modification of the fourth embodiment;
FIG. 30 is a diagram (part 3) illustrating a manufacturing process according to a modification of the fourth embodiment;
FIG. 31 is a view showing a semiconductor device according to a fifth embodiment.
[Explanation of symbols]
1,26 substituted Al material
3 Work function adjustment metal
10, 40 Semiconductor device
11 Semiconductor substrate
12 Element isolation region (STI)
13 Gate insulating film
14 polysilicon gate electrode (initial gate electrode)
15 Source / drain (diffusion region)
17 Sidewall
23 plug
25 Resist
27, 29 Ti film (metal replacement accelerator)
28 Work function adjusting metal-containing Al material
46 Replacement metal electrode (first replacement metal electrode)
48 silicide electrode (second replacement gate electrode)

Claims (5)

A semiconductor substrate;
A first transistor formed on the semiconductor substrate and having a first gate electrode and a channel diffusion region of a first conductivity type;
A second transistor formed on the semiconductor substrate, the second transistor having a channel diffusion region of a second conductivity type, wherein at least one of the first and second gate electrodes has a work function adjustment function; The replacement metal material containing a metal and containing the work function adjusting metal has a work function such that the threshold voltage of the corresponding transistor is substantially symmetric with the threshold voltage of the other transistor. A semiconductor device having a function. A semiconductor substrate;
A first transistor formed on the semiconductor substrate and having a first gate electrode and a channel diffusion region of a first conductivity type;
A second transistor of a second conductivity type formed on the semiconductor substrate and having a second gate electrode and a channel diffusion region of a second conductivity type;
Wherein one of the first or second gate electrodes is made of a replacement metal material or a replacement metal material containing a work function adjusting metal, the other gate electrode is made of silicide, and the silicide is A semiconductor device having a work function such that a threshold voltage of a corresponding transistor is substantially symmetric with a threshold voltage of the one transistor. A first transistor having a first initial gate electrode and a channel diffusion region of a first conductivity type on a semiconductor substrate; a second transistor having a second initial gate electrode and a channel diffusion region of a second conductivity type; Forming a;
Replacing at least one of the first or second initial gate electrode with a substitution metal material containing a work function adjustment metal by heat treatment to form a work function adjustment metal-containing substitution metal gate electrode; The replacement metal material containing the work function adjustment metal has a work function such that the threshold voltage of a transistor corresponding to the work function adjustment metal-containing replacement metal gate electrode is substantially symmetric with the threshold voltage of the other transistor. A method for manufacturing a semiconductor device, wherein the method is selected to have: A first transistor having a first initial gate electrode and a channel diffusion region of a first conductivity type on a semiconductor substrate; a second transistor having a second initial gate electrode and a channel diffusion region of a second conductivity type; Forming a;
Exposing at least a part of the first initial gate electrode and at least a part of the second initial gate electrode simultaneously or individually;
Forming a first metal layer at an exposed portion of the first initial gate electrode;
Forming a metal layer containing a work function adjusting metal or a second metal layer different from the first metal layer at an exposed portion of the second initial gate electrode;
By performing the heat treatment, the first initial gate electrode is replaced with a first replacement metal gate electrode, and the second initial gate electrode is replaced with the threshold voltage of the corresponding second transistor after the replacement. Replacing with a second replacement gate electrode having a work function substantially symmetric to the threshold voltage of one transistor. The first initial gate electrode and the second initial gate electrode are simultaneously replaced with the first replacement metal gate electrode and the second replacement gate electrode by the same heat treatment process. A method for manufacturing a semiconductor device according to claim 4.

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