JP2002237589A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize reduction of threshold voltage using a metal gate, without requiring complicated manufacturing steps. SOLUTION: A silicon oxide film 15 is formed as an insulation film on a silicon substrate 11, and a tungsten film is formed on the formed film 15 by a PVD method. Then, a PMOS region is covered with a photoresist 17, and thorium is introduced into the film 16 on the NMOS region through ion implantation. In this way, the metal gate of the PMOS is formed of a tungsten, and the metal gate of the NMOS is formed of a thorium-doped tungsten, and thus the metal gates having different work functions can be formed easily on the PMOS and the NMOS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a semiconductor device having a metal gate.

[0002]

2. Description of the Related Art Conventionally, MOSFET (Metal Ox)
ide SemiconductorField Ef
In general, polycrystalline silicon was used for the gate electrode of the FET. Particularly in recent years, it has become common to use a so-called dual gate using N-type polycrystalline silicon for NMOS and P-type polycrystalline silicon for PMOS for reasons of reduction in power consumption.

[0003] However, such a dual gate has a problem of so-called boron penetration, in which boron in P-type polycrystalline silicon diffuses through the gate insulating film to the substrate. In the first place, in polycrystalline silicon, a depletion layer always exists at the interface with the gate insulating film. Therefore, when reducing the thickness of the gate insulating film in order to miniaturize the device, 0.5 nm
It is necessary to make the gate insulating film extra thin, resulting in a problem that the tunnel leak current of the gate insulating film increases.

As a method of solving such a problem of polycrystalline silicon, use of a high melting point metal has been considered. However, in the case of a metal gate using a high melting point metal, although the problems of the boron penetration and the depletion layer are solved, there is a problem that the threshold voltage is newly increased. For example, TiN
It has been reported that the threshold voltage cannot be reduced to 0.4 V or less even when the impurity distribution on the surface of the silicon substrate is adjusted when Ni is used for the gate (Nishinohara e).
t al. , Extended Abstracts
of the 2000 International
Conference on Solid Stat
e Devices and Materials,
p. 46). The reason is that the work function of TiN is 4.
This is because the work function difference is about 0.5 eV for both the PMOS and the NMOS, since it is located near the mid-gap of the silicon forbidden band at about 5 eV.

[0005] On the other hand, there is an idea that different metals having different work functions are used for the PMOS and the NMOS (for example, The International Technology).
logic Roadmap for Semiconductor
Ductors, 1999). For example, Re or Ir having a work function of about 5.0 eV and located near the valence band of silicon of the substrate is used for PMOS, and a work function of about 4.0 eV and located near the conduction band of silicon of the substrate for NMOS. In this case, Nb or Zr is used.

However, in this case, it is necessary to separately form the PMOS and NMOS gate electrodes, which are conventionally performed simultaneously. That is, for example, Ir is formed as a PMOS metal gate over the entire surface with the NMOS gate insulating film hidden by a dummy film such as a polycrystalline silicon film, and then the Ir film other than the PMOS region is peeled off.
After the dummy film in the MOS region is peeled off, for example, Zr is formed as a metal gate of the NMOS on the entire surface, and then the Zr film in the region other than the NMOS region is peeled off. Is also very complicated.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has involved a complicated manufacturing process such as forming a heterogeneous metal film between a PMOS and an NMOS using a metal gate. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of realizing a lower threshold voltage without necessity.

[0008]

That is, a method of manufacturing a semiconductor device according to the first aspect of the present invention is characterized in that tungsten is used for a gate electrode of a PMOS and tungsten to which thorium is added is used for a gate electrode of an NMOS. .

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an insulating film on a semiconductor substrate; forming a tungsten film on the formed insulating film;
Adding thorium to the tungsten film formed in the S region.

Tungsten has a work function of 4.47 eV (111), 4.63 eV (100),
Although different, such as 5.25 eV (110), the average value is about 4.8 eV, which can be a work function near the valence band of silicon. It is known that when thorium is added to this tungsten, the work function is reduced (for example, see Grand Modern Encyclopedia, Gakken), and by adjusting the amount of added thorium, the work function is reduced by 4%. 0.0 eV and can be close to the vicinity of the conduction band of silicon.

Therefore, according to the first and second aspects of the present invention, the number of steps required for forming the gate is increased without increasing the number of steps.
By making the work function of each gate closer to the valence band and conduction band of silicon, it becomes possible to lower the threshold voltage.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. In this embodiment, as the order of forming the FETs, a metal gate electrode is formed, and then a source / drain portion is formed.

First, as shown in FIG. 1, after an element isolation region 12 is formed in a P-type silicon substrate 11, a P well 13 is formed in an NMOS region and an N well 14 is formed in a PMOS region.

Next, in FIG. 2, after a threshold voltage adjusting impurity is introduced into each of the P well 13 and the N well 14, a silicon oxide film 15 is formed as a gate insulating film. The silicon oxide film 15 is formed at an oxidation temperature of 750 using, for example, nitrogen dilution pyrogenic as an oxidation atmosphere.
The film can be formed to a thickness of 2.5 nm at ℃.

Next, referring to FIG.
Is formed to a thickness of 100 nm by a PVD method, the PMOS region is covered with a photoresist 17, and thorium is introduced into the tungsten film 16 in the NMOS region by ion implantation. The ion implantation conditions can be, for example, an implantation energy of 20 keV and a dose of 1E14 cm ⁻² .

Next, referring to FIG.
After removing 7, a new tungsten gate electrode 18 is formed in the PMOS region and a tungsten gate electrode 19 to which thorium is added in the NMOS region by patterning and anisotropic etching of the photoresist.

Further, referring to FIG.
After forming the region 20 and the LDD region 21 of the PMOS, respectively, a sidewall region 22 is formed by forming a silicon nitride film by a CVD method and etching back.

In FIG. 6, after the source / drain region 23 of the NMOS and the source / drain region 24 of the PMOS are formed, the well and the L
DD and activation of impurities in the source / drain regions and diffusion of ion-implanted thorium into the tungsten film are collectively performed to complete the formation of the FET.

FIGS. 7 to 14 are process cross-sectional views for explaining a method of manufacturing a semiconductor device according to the second embodiment. In this embodiment, the source and the drain are formed first, and then the metal gate electrode is formed.

First, in FIG. 7, similarly to the first embodiment, after forming an element isolation region 12 in a P-type silicon substrate 11, a P well 13 is provided in an NMOS region and an N well 14 is provided in a PMOS region. Form.

Next, in FIG. 8, after a threshold voltage adjusting impurity is introduced into each of the P-well 13 and the N-well 14, a 10-nm-thick dummy gate insulating film is formed.
An m-th silicon oxide film 25 is formed.

Next, in FIG. 9, a polycrystalline silicon film having a thickness of, for example, 100 nm is formed as a dummy gate electrode by a CVD method, and then the polycrystalline silicon gate electrode is formed by patterning a photoresist and anisotropically etching. 26 is formed.

Next, referring to FIG.
Region 20, PMOS LDD region 21, sidewall region 22, and NMOS source / drain region 23
And a source / drain region 24 of a PMOS, respectively, and then a silicon oxide film 27 serving as an interlayer insulating film with the wiring
Is formed by a CVD method.

Next, in FIG. 11, the silicon oxide film 27 is removed until the surface of the dummy gate electrode 26 is exposed.
After polishing by the MP method, the dummy gate electrode 26 and the silicon oxide film 25 are removed by etching.

Next, in FIG. 12, a 7 nm-thick aluminum oxide film 28 is formed by a PVD method as a gate insulating film, and a tungsten film 16 is buried by a PVD method as a gate electrode.

Next, in FIG. 13, after the tungsten film 16 is flattened by the CMP method, the region other than the region of the NMOS gate electrode is covered with a photoresist 17 and the NMO is removed.
Thorium is introduced only into the tungsten film 16 of S by ion implantation.

Finally, referring to FIG. 14, the photoresist 17 is removed to obtain a gate electrode 18 of PMOS tungsten and a gate electrode 19 of thorium-doped tungsten of NMOS.
Activation of the impurities in the source / drain regions and diffusion of the ion-implanted thorium into the tungsten film are collectively performed to complete the formation of the FET.

As is clear from the above description, in the first and second embodiments, the dissimilar metal NMOS
A metal gate whose work function is close to the conduction band and valence band of silicon can be formed in each of NMOS and PMOS in a smaller number of steps than in the case of forming a gate of PMOS and PMOS. Can be reduced.

The present invention is not limited to the first and second embodiments. The material and film thickness of the gate insulating film, the method and film thickness of the tungsten film, the conversion of thorium to tungsten The method and amount of introduction, the structure and the order of formation of the FETs are merely examples, and it goes without saying that they can be changed as appropriate without departing from the spirit of the present invention.

[0030]

As described above, according to the first aspect of the present invention, the metal gate of the PMOS is made of tungsten and the NMOS is made of the NMOS.
The work function of the PMOS metal gate and the work function of the NMOS metal gate can be close to the valence band and the conduction band of silicon, respectively, by forming the metal gates of A reduction can be realized.

According to the second aspect of the present invention, the NMOS
When forming a metal gate having a different work function on the NMOS and the PMOS, first, a tungsten film is formed at the same time, and then the NM is formed.
By changing the work function by introducing thorium only into the tungsten film of the OS, the number of steps can be significantly reduced as compared with the case where different kinds of metals are formed on the NMOS and the PMOS.

[Brief description of the drawings]

FIG. 1 is a process sectional view (part 1) for describing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 2) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a process sectional view (part 3) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view (part 4) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a process sectional view (part 5) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a process sectional view (part 6) for describing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a process cross-sectional view (part 1) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process sectional view (part 2) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a process sectional view (part 3) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a process sectional view (part 4) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a process sectional view (part 5) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a process sectional view (part 6) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a process sectional view (part 7) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a process sectional view (part 8) for describing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

11 ... silicon substrate, 12 ... element isolation region, 13 ...
... P well, 14 ... N well, 15 ... Silicon oxide film (gate insulating film), 16 ... Tungsten film, 17 ...
... Photoresist, 18 ... Tungsten gate electrode, 19 ... Thorium-doped tungsten gate electrode, 20 ... NMOS LDD region, 21 ... PMO
S LDD region, 22... Sidewall region, 23.
... NMOS source / drain regions, 24 ... PMOS
25, a silicon oxide film (dummy gate insulating film), 26 a polycrystalline silicon gate electrode (dummy gate electrode), 27 a silicon oxide film (interlayer insulating film), 28 ... Aluminum oxide film (gate insulating film)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB18 BB39 CC05 DD03 DD04 DD33 DD78 DD82 EE16 GG10 HH20 5F048 AA09 AB03 AC03 BA01 BB04 BB09 BB10 BB11 BB14 BB15 BC06 BE03 DA27 5F140 AA06 AA40 AB03 BA01 BD11 BE07 BF08 BG14 BG30 BG36 BG40 BG43 BG53 BH15 BK02 BK21 CB08 CC03 CC12 CE07

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: using tungsten for a gate electrode of a PMOS; and using tungsten doped with thorium for a gate electrode of an NMOS. 2. The method according to claim 1, further comprising: forming an insulating film on the semiconductor substrate; forming a tungsten film on the insulating film; and adding thorium to the tungsten film in an NMOS region. Semiconductor device manufacturing method.