JP2008091501A - Semiconductor integrated circuit device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide metal gate electrode MOSFET where an etching condition of a metal gate electrode becomes the same even if a material constituting a threshold electrode differs. <P>SOLUTION: A semiconductor integrated circuit has n-channel MOSFET having a first gate electrode consisting of a first metal layer formed by bringing it into contact with a gate oxide film and a first low resistance layer formed on the first metal layer and p-channel MOSFET having a second gate electrode consisting of a second metal layer formed by bringing it into contact with the gate oxide film and a second low resistance layer formed on the second metal layer. The first metal layer and the second metal layer are constituted of metals having different work functions. The first low resistance layer and the second low resistance layer are constituted of polycrystals consisting of the same materials. A first intermediate layer is arranged between the first metal layer and the first low resistance layer. A second intermediate layer is disposed between the second metal layer and the second low resistance layer. The first intermediate layer and the second intermediate layer are formed of conductive polycrystalline films whose particle sizes, crystal structures and orientation directions are the same. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a MOS field effect transistor (MOSFET) having a metal layer as a gate electrode.

  In order to achieve high integration of a semiconductor integrated circuit composed of MOSFETs, it is important to increase the gate capacity per unit area by thinning the gate insulating film. However, the gate insulating film thickness of the MOSFET has already been reduced to about 1.5 nm, and further thinning is becoming difficult.

A silicon oxide film (SiO ₂ film) is widely used as the gate insulating film. However, when the SiO ₂ film has a thickness of 1 nm or less, the leakage current increases, and it cannot be used as a gate insulating film. This situation is the same even when other insulating films such as a silicon oxynitride film (SiON film) are used. That is, it is difficult to reduce the thickness of the gate insulating film to 1 nm or less, and the increase in gate capacitance due to the thinning of the gate insulating film is reaching its limit.

Two solutions are currently being considered to solve this problem. The first solution is to use a high dielectric constant dielectric film such as HfO ₂ or HfSiON as the gate insulating film. If a material with a high dielectric constant ε is used as the insulating film, the gate insulating film capacitance Cox (= ε / d, d is the thickness of the gate insulating film) per unit area is increased without thinning the gate insulating film. can do.

  The second solution is to replace the polycrystalline silicon film currently used as the gate electrode with a metal film.

FIG. 23 is a schematic cross-sectional view of a currently used MOSFET. On the channel region 102 sandwiched between the source region 100 and the drain region 101, a gate electrode is formed via a SiO ₂ oxide film 103.

The gate electrode includes a threshold electrode (or work function electrode) made of polycrystalline silicon 104 and a low resistance layer 105 made of NiSi, CoSi ₂ or the like. In order to lower the threshold value, n-type polycrystalline silicon is used as a threshold electrode (or work function electrode) for n-channel MOS, and p-type polycrystalline silicon is used for p-channel MOS. The reason why polycrystalline silicon is used as the threshold electrode (or work function electrode) is that the gate electrode made of polycrystalline silicon can easily adjust the Fermi level by controlling the type and concentration of impurities to be doped. is there.

In order to lower the threshold of n-channel MOSFETs, the Fermi level of the gate electrode must be set near the conduction band. On the other hand, in a p-channel MOSFET, the Fermi level of the gate electrode must be set near the valence band. In polycrystalline silicon, the position of the Fermi level can be adjusted depending on the type and concentration of impurities to be doped. Therefore, by using n ⁺ polycrystalline silicon and p ⁺ polycrystalline silicon as the gate electrode, both the n-channel MOSFET and the p-channel MOSFET can be lowered in threshold value.

In addition, the fact that polycrystalline silicon is excellent in heat resistance and workability is a major reason that it has been used as a gate electrode. However, polycrystalline silicon has a drawback in that there is a limit to reducing the resistance. In order to compensate for this drawback, a metal layer made of silicide such as NiSi or CoSi ₂ is laminated on polycrystalline silicon to reduce the resistance of the gate electrode.

  When the gate electrode has a multilayer structure such as a polycrystalline silicon / silicide electrode, a layer in contact with an oxide film (that is, an insulating film) such as polycrystalline silicon is used as a threshold electrode (or work function electrode). Call it. The low resistance layer laminated on the threshold electrode (or work function electrode) for reducing the resistance of the gate electrode is sometimes called a wiring metal layer.

However, another problem exists with polycrystalline silicon gates. This problem becomes apparent when the gate insulating film is thinned. The SiO ₂ film / polycrystalline silicon interface does not have an ideal structure that suddenly changes from polycrystalline silicon filled with carriers to SiO ₂ film. In fact in the polycrystalline silicon, regions 0.5nm approximately depleted in SiO ₂ film equivalent is present in the contact with the SiO ₂ film / polysilicon interface.

This depleted polycrystalline silicon layer has an apparently thick gate insulating film and a small gate insulating film capacitance Cox per unit area. The capacitance equivalent thickness (CET) of the gate insulating film, that is, the oxide film thickness d ′ (= ε / Cox) calculated backward from the capacitance Cox of the gate insulating film is a polycrystal depleted from the gate insulating film thickness. It is the sum of the silicon film thickness (SiO ₂ equivalent). While the gate insulating film was thick, the existence of a depleted polycrystalline silicon film could be ignored. However, today, when the gate insulating film thickness has approached 1 nm, depletion of about 0.5 nm cannot be ignored.

  As a solution to this problem, a metal gate electrode has been studied. The metal gate electrode refers to a gate electrode whose threshold electrode (or work function electrode) is made of metal (a substance in which the Fermi level enters the conduction band, except for silicide). FIG. 24 is a schematic cross-sectional view of a metal multilayer film deposited for manufacturing a CMOSFET (complementary MOSFET) having a metal gate electrode (Non-Patent Document 1). The metal multilayer film shown in the figure is immediately after being deposited and has not yet been processed into a gate electrode.

In the p-channel MOSFET region 106, a metal layer 107 made of Ru and a metal layer 108 made of TaN are stacked on the HfO ₂ insulating film 111. In the n-channel MOSFET region 109, a metal layer 110 made of TaSi _x N _y , a metal layer 107 made of Ru, and a metal layer made of TaN are stacked on the HfO ₂ insulating film 111.

Ru and TaSi _x N _y have work functions (Fermi levels) close to the valence band and conduction band of silicon, respectively. Therefore, it is suitable for the threshold electrode (or work function electrode) of p-channel MOSFET and n-channel MOSFET.

When a threshold electrode (or work function electrode) made of metal as shown in FIG. 24 is used, a depletion layer is hardly generated and the work function of the gate electrode can be brought close to the valence band or the conduction band. Therefore, it is possible to prevent the increase of the capacitance equivalent film thickness CET and reduce the threshold value of the MOSFET.
“Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOOS) Gate Electrodes on HfO2 Dielectric”, 2005 Symposium on VLSI Technology Digest of Technical Papers, p.50-51. “Effect of the Composition on the Electrical Properties of TaSixNy Metal Gate Electrodes”, IEEE ELECTRON DEVICE LETTERS, VOL.24, 2003, p.429-431.

Almost no depletion layer is generated in the metal gate electrode. That is, if a metal gate electrode is used, an increase in capacitance equalization film thickness can be avoided. Therefore, it is expected that the problems currently faced by MOSFETs (limit of increase in gate capacity per unit area) can be solved by combining high dielectric constant dielectric films such as HfO ₂ and HfSiON with metal gate electrodes. Has been.

  However, unsolved problems remain in the metal gate electrode.

Many candidate materials (TiN, TaSi _x N _y, etc.) for forming the threshold electrode (or work function electrode) have a large specific resistance of several mΩ · cm. Therefore, it is necessary to laminate a wiring metal layer made of a low resistance metal having a specific resistance of about 10 ⁻⁵ Ω · cm on these metal layers. As the wiring metal layer, W and Mo are excellent from the viewpoint of workability and heat resistance.

  A wiring metal layer such as W can be etched into an ideal shape as a gate electrode by reactive ion etching (RIE). FIG. 25 is a cross-sectional perspective view of a ridge 113 formed by etching W (or Mo) 112 by RIE using an elongated rectangular mask. The cross section 114 is a clear rectangle without sagging, and the ridge line 115 of the ridge is a clear straight line without irregularities. That is, the wiring metal layer such as W can be processed into an ideal shape as a gate electrode by RIE. However, the shape of the ridge formed by RIE greatly depends on the crystal grain size and orientation direction of the metal film to be etched.

By the way, the wiring metal layer such as W has a characteristic that it is easily polycrystallized and the crystal grain size and orientation direction are easily changed depending on the base metal and the growth conditions. For this reason, when a wiring metal layer made of W or the like is grown on different threshold electrodes (or work function electrodes) (for example, TaSi _x N _y and Ru), metal films having different crystal grain sizes and orientation directions are formed. End up. In particular, in the metal gate electrode, since the wiring metal layer having excellent workability is formed thicker than the threshold electrode (or work function electrode), this tendency (difference in crystal grain size and the like) becomes obvious.

  As a result, the etching conditions for forming the gate electrode are different if the threshold electrode (or work function electrode) is different, even if the same wiring metal layer is used. In current integrated circuits, n-channel MOSFETs and p-channel MOSFETs are mixed. For example, a typical example is an integrated circuit constituted by a CMOS (complementary MOSFET) in which an n-channel MOSFET and a p-channel MOSFET are connected in series.

  As described above, the gate metal etching conditions differ between the n-channel MOSFET and the p-channel MOSFET. Therefore, if an integrated circuit in which an n-channel MOSFET and a p-channel MOSFET coexist is formed by a metal gate MOSFET, the manufacturing process becomes complicated. In other words, the metal gate electrode of the n-channel MOSFET and the metal gate electrode of the p-channel MOSFET must be etched separately under different conditions.

  Accordingly, an object of the present invention is to provide a MOSFET in which the etching conditions for forming the metal gate electrode are the same even if the materials constituting the threshold electrode (or work function electrode) are different, and a method for manufacturing the same. .

  In order to achieve the above object, the present invention is configured as follows, and has the following operations and effects.

    (First invention) A first invention comprises a first metal layer formed in contact with a gate oxide film, and a first low resistance layer formed on the first metal layer. A second gate comprising: an n-channel MOSFET having a plurality of gate electrodes; a second metal layer formed in contact with the gate oxide film; and a second low-resistance layer formed on the second metal layer In a semiconductor integrated circuit device having a p-channel MOSFET having an electrode, the first metal layer and the second metal layer are made of metals having different work functions, and the first low-resistance layer and the second metal layer The low resistance layer is made of a polycrystal made of the same material, has a first intermediate layer between the first metal layer and the first low resistance layer, and the second metal layer and the second metal layer. A second intermediate layer is provided between the low resistance layers, and the first intermediate layer and the second intermediate layer have a composition, a grain size, a crystal structure, and an orientation. Direction is characterized by comprising the same conductive polycrystalline film.

  According to the first invention, since the gate electrodes made of metals having different threshold electrodes (or work function electrodes) can be formed simultaneously by the same etching, a semiconductor integrated circuit device comprising n-channel and p-channel MOSFETs can be obtained. The metal gate electrode MOSFET can be easily configured.

(Second invention)
According to a second invention, in the first invention, the first metal layer and the first intermediate layer are continuously formed in the same growth apparatus, and the second metal layer and the second intermediate layer are the same. It is characterized by being formed continuously in the growth apparatus.

  According to the second invention, the grain sizes, crystal structures, and orientation directions of the first and second intermediate layers can be made the same.

(Third invention)
According to a third invention, in the first or second invention, the first and second intermediate layers are made of TiN or TaN.

  According to the third invention, the first and second intermediate layers can be easily formed into a conductive polycrystalline film having the same composition, grain size, crystal structure, and orientation direction.

(Fourth invention)
According to a fourth invention, in the first to third inventions, the same material is any one of W, WSi ₂ , Mo, Ru, Ta, and Si.

  According to the fourth invention, the low resistance layer can be made of a material having heat resistance.

(Fifth invention)
An n-channel MOSFET having a first gate electrode composed of a first metal layer formed in contact with the gate oxide film and a first low-resistance layer formed on the first metal layer; A p-channel MOSFET having a second gate electrode comprising a second metal layer formed in contact with the film and a second low-resistance layer formed on the second metal layer; The metal layer and the second metal layer are made of metals having different work functions, the first low resistance layer and the second low resistance layer are made of polycrystals made of the same material, and A first intermediate layer between the first metal layer and the first low-resistance layer, and a second intermediate layer between the second metal layer and the second low-resistance layer; The intermediate layer and the second intermediate layer are made of a conductive polycrystalline film having the same composition, grain size, crystal structure, and orientation direction. In the method, a step of continuously forming a first metal film to be a first metal layer and a second metal film to be a first thin layer in the same growth apparatus; and And a third metal film serving as a metal layer and a fourth metal film serving as a second intermediate layer are continuously formed in the same growth apparatus. Device manufacturing method.

  According to the first invention, since the gate electrodes made of metals having different threshold electrodes (or work function electrodes) can be formed simultaneously by the same etching, a semiconductor integrated circuit device comprising n-channel and p-channel MOSFETs can be obtained. The metal gate electrode MOSFET can be easily manufactured.

  The present invention is characterized in that an intermediate layer such as TiN or TaN is interposed between a threshold electrode (or work function electrode) and a wiring metal layer. When the gate electrode is configured in this way, even if the threshold electrode (or work function electrode) is composed of different metals, the wiring metal layer formed thereon has the same grain size and orientation direction. Therefore, the gate electrodes of the n-channel and p-channel MOSFETs can be formed by a single etching, and a semiconductor integrated circuit including both the n-channel and p-channel MOSFETs can be easily formed by the MOSFET having the metal gate electrode. it can.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.
[Element structure]
(1) Overall Configuration FIG. 1 is a sectional view of a CMOSFET (complementary MOSFET) constituting the semiconductor integrated circuit according to the present embodiment. An n-channel MOSFET 50 and a p-channel MOSFET 51 are formed on the high resistance silicon substrate 1. The n-channel MOSFET 50 and the p-channel MOSFET 51 are insulated by an element isolation region 2 made of STI (Shallow Trench Isolation). This element isolation region 2 is formed by filling a shallow groove of about 400 nm with SiO ₂ .

(2) Configuration of Gate Electrode The threshold electrode (or work function electrode) 52 of the n-channel MOSFET 50 is preferably composed of a metal having a work function in the range of 3.9 to 4.4 eV. Specifically, any of Ta, TaN, TaSi, TaSi ₂ and TaSi _x N _y is preferable. The work function of TaSi _x N _y varies in the range of 4.2 to 4.4 eV depending on the composition at the time of film formation and the subsequent heat treatment process (Non-patent Document 2). The film thickness of the threshold electrode (or work function electrode) 52 of the n-channel MOSFET 50 is preferably about 1 to 10 nm.

As the intermediate layer 53 of the n-channel MOSFET 50, a polycrystalline TiN or polycrystalline TaN film is preferable. The film thickness is preferably 5 to 20 nm. The wiring layer is preferably a polycrystalline film made of a refractory metal or polycrystalline silicon having heat resistance such as W, WSi ₂ , Mo, Ta, or Ru. The film thickness is preferably about 50 to 100 nm.

The threshold electrode (or work function electrode) 55 of the p-channel MOSFET 51 is preferably made of a metal having a work function in the range of 4.7 to 5.3 eV. Specifically, any one of Ru, RuO ₂ , TiN, and TiSi _x N _y is preferable. The film thickness is preferably about 1 to 10 nm.

As the intermediate layer 56 of the p-channel MOSFET 51, a polycrystalline TiN or polycrystalline TaN film is preferable. The film thickness is preferably 5 to 20 nm. The wiring metal layer 57 of the p-channel MOSFET 51 is preferably a polycrystalline film made of refractory metal or polycrystalline silicon having heat resistance such as W, WSi ₂ , Mo, Ta, and Ru. The film thickness is preferably 50 to 100 nm.

  The threshold electrode (or work function electrode) 52 of the n-channel MOSFET 50 and the threshold electrode (or work function electrode) 55 of the p-channel MOSFET 51 have different work functions. The reason why the threshold electrodes (or work function electrodes) 52 and 55 having different work functions are used is to reduce both the MOSFETs 50 and 51.

(3) Intermediate layer The reason why the intermediate layers 53 and 56 are provided is that both the gate electrode of the n-channel MOSFET 50 and the gate electrode of the p-channel MOSFET 51 are simultaneously formed into a preferable shape as a gate electrode by one etching.

  In order to achieve such an object, the intermediate layers 53 and 56 are preferably composed of conductive polycrystalline films having the same composition, grain size, crystal structure, and orientation direction. If such a condition is satisfied, even if the materials of the threshold electrodes (or work function electrodes) 52 and 55 are different as in the present embodiment, the wiring metal layer 54 formed on the intermediate layers 53 and 56 is different. , 57 have the same grain size and orientation direction. As a result, both the gate electrode of the n-channel MOSFET 50 and the gate electrode of the p-channel MOSFET 51 can be formed into a shape preferable as a gate electrode by one etching at the same time.

  The shape obtained by etching a polycrystalline film usually depends on the crystal grain size and orientation direction. By the way, metals suitable for wiring metal layers such as W and Mo are easily formed as a polycrystalline film, and the crystal grain size and orientation direction are not only the growth conditions but also the composition of the underlying metal layer, the grain size, the crystal structure, and Changes under the influence of the orientation direction. Therefore, in order to form the wiring metal layers 54 and 57 in a preferred shape as a gate electrode simultaneously by one etching, it is preferable that the composition, grain size, crystal structure, and orientation direction of the base metal are the same.

  However, as described above, the threshold electrode (or work function electrode) 52 of the n-channel MOSFET 50 and the threshold electrode (or work function electrode) 55 of the p-channel MOSFET 51 are made of different materials for lowering the threshold. Accordingly, the composition, grain size, crystal structure, and orientation direction are naturally different. For this reason, when the wiring metal layers 54 and 57 are grown directly on the threshold electrodes (or work function electrodes) 52 and 55, the gate electrode occupying most of the size of the wiring metal layers 54 and 57 is formed into a preferable shape. It cannot be formed by one etching at the same time.

  By the way, some metal films have the same grain size, crystal structure, and orientation direction even if the underlying metal layers are different under certain growth conditions. For example, when TiN or TaN is formed by chemical vapor deposition (CVD), under normal growth conditions used for manufacturing semiconductor integrated circuits, a constant grain size, crystal structure, and Grows into a polycrystalline film having an orientation direction.

  Therefore, the intermediate layers 53 and 56 are composed of a conductive film having the same composition, grain size, crystal structure, and orientation direction, for example, (100) oriented rutile TiN or (111) oriented face-centered cubic TaN. In this case, the wiring metal layers 54 and 57 can be formed into a preferable shape as a gate electrode by one etching at the same time. Although the threshold electrodes (or work function electrodes) 52 and 55 are made of different materials, the thickness of the threshold electrodes (or work function electrodes) 52 and 55 is different. The etching shape is hardly affected.

  However, in order to etch the wiring metal layers 54 and 57 into the same shape with good reproducibility, it is preferable that the upper surfaces of the threshold electrodes (or work function electrodes) 52 and 55 in contact with the intermediate layers 53 and 56 are not oxidized. . That is, when the upper surfaces of the threshold electrodes (or work function electrodes) 52 and 55 are oxidized, the wiring metal layers 54 and 57 are formed into a preferable shape as a gate electrode, and simultaneously formed with good reproducibility by one etching. Becomes difficult.

  When TiN or TaN is formed by a chemical vapor deposition method (CVD method), a polycrystalline film having a constant grain size, crystal structure, and orientation direction grows regardless of the type of the underlying metal layer. However, this is the case when the surface of the underlying metal layer is not oxidized. When the surface of the underlying metal layer is oxidized, the grain size and orientation direction of the growth film are likely to be disturbed.

However, TaSi _x N _y and TiSi _x N _y suitable for the threshold electrodes (or work function electrodes) 52 and 55 have a characteristic that they are easily oxidized. Therefore, when the upper surfaces of the threshold electrodes (or work function electrodes) 52 and 55 are exposed to the atmosphere while being exposed, the upper surfaces of the threshold electrodes (or work function electrodes) 52 and 55 are strongly oxidized with oxygen.

  The upper surfaces of the oxidized threshold electrodes (or work function electrodes) 52 and 55 adversely affect the growth of the intermediate layers 53 and 56, causing the crystal grain size and the orientation direction of the intermediate layers 53 and 56 to be not constant. As a result, the crystal grain size and orientation direction of the wiring metal layers 54 and 57 are not constant. Therefore, it becomes difficult to form the wiring metal layers 54 and 57 into a preferable shape as a gate electrode with good reproducibility by one etching at the same time.

  In order to prevent the formation of an oxide layer on the upper surface of the threshold electrode 52 (or work function electrode) of the n-channel MOSFET 50, the threshold electrode (or work function electrode) 52 and the intermediate layer 53 are continuously grown in the same growth apparatus. good. In this way, the upper surface of the threshold electrode (or work function electrode) 52 is not oxidized. Therefore, the wiring metal layer 54 can be etched into the same shape with good reproducibility. The same applies to the upper surface of the threshold electrode (or work function electrode) 55 of the p-channel MOSFET 51. Alternatively, before the intermediate layers 53 and 56 are grown, the upper surfaces of the threshold electrodes (or work function electrodes) 52 and 55 may be carefully cleaned to remove the oxide layer. Whether the upper surfaces of the threshold electrodes (or work function electrodes) 52 and 55 are oxidized can be determined by a surface analysis method such as Auger Electron Spectroscopy.

  In the CMOS of FIG. 1, intermediate layers 53 and 56 made of conductive polycrystalline films having the same composition, grain size, crystal structure, and orientation direction are used as threshold electrodes (or work function electrodes) 52 and 55 and wiring metal layers 54 and 55, respectively. The upper surface of the threshold electrodes (or work function electrodes) 52 and 55 is prevented from being oxidized. Therefore, the gate electrodes of the n-channel MOSFET 50 and the p-channel MOSFET 51 could be processed into a shape suitable for the gate electrode as shown in FIG. 25 by one etching.

  The orientation direction refers to the direction of the specific crystal axis when specific crystal axes of the microcrystals constituting the polycrystalline film are oriented in substantially the same direction. The grain size (and orientation direction) of each microcrystal constituting the polycrystalline film is not constant but distributed around the median value (or the center direction). The same grain size (or orientation direction) means that the average grain size (or average orientation direction) is substantially the same for the two polycrystalline films to be compared. Specifically, the same grain size means that the ratio of the average grain sizes of the two polycrystalline films to be compared is preferably 0.1 or more and 10 or less, more preferably 0.2 or more and 5.0 or less, and most preferably 0.5 or more and 2.0 or less. Say there is. In addition, the same orientation direction is preferably an angle formed by the directions obtained by averaging the orientation directions of the microcrystals in each of the two polycrystalline films to be compared (average orientation direction, so-called orientation direction of the polycrystalline film). Means within 45 degrees (0 degree to 45 degrees, the same applies hereinafter), more preferably within 30 degrees, and most preferably within 10 degrees.

(4) As the gate oxide film and gate oxide film 58 and 59 of the source and drain regions n-channel MOSFET50 and p-channel MOSFET51, HfSi _x O _y N _z film having a thickness 1.5~5nm are preferred. A silicon dioxide film (SiO ₂ film) or a silicon oxynitride film (SiON film) having a thickness of 1 to 3 nm may be used, but it is close to the limit film thickness at which the leakage current increases and does not function as an insulating film. Therefore, when such a SiO ₂ film or a SiON film is used, it is difficult to improve the performance by reducing the thickness.

  The source 20 and the drain 21 of the n-channel MOSFET 50 are formed on the surface of the p-type well region 4 formed in the high resistance silicon substrate 1. The source 20 and the drain 21 are made of a high carrier concentration n-type silicon layer, and a contact electrode 26 made of nickel silicide NiSi is formed on the surface.

  In order to prevent the electric field strength from becoming excessively high near the source 20 or the drain 21, an extension region 17 made of a low carrier concentration n-type silicon layer is disposed in the vicinity immediately below the gate insulating film 58. The sidewall spacer insulating film 14 and the sidewall insulating film 19 are for forming the source 20 or the drain 21 in contact with the extension region 17 by ion implantation.

  The source 23 and the drain 24 of the p-channel MOSFET 51 are formed on the surface of the n-type well region 3 formed in the high resistance silicon substrate 1. The source 23 and the drain 24 are made of a high carrier concentration p-type silicon layer, and a contact electrode 26 made of nickel silicide NiSi is formed on the surface.

  In order to prevent the electric field strength from becoming excessively high near the source 23 or the drain 24, an extension region 15 made of a low carrier concentration p-type silicon layer is disposed in the vicinity immediately below the gate insulating film 59. The side wall spacer insulating film 14 and the side wall insulating film 19 are for forming the source 23 and the drain 24 in contact with the extension region 15 by ion implantation.

[Production method]
2 to 22 show a method of manufacturing the CMOSFET shown in FIG.

(1) Formation of n-type and p-type wells FIG. 2 shows a process of forming an n-well region 3 and a p-well 4 in a high-resistance silicon substrate 1. As shown in FIG. 2A, first, an element isolation region 2 made of STI (Shallow Trench Isolation) is formed on a high resistance silicon substrate 1. A shallow trench having a depth of about 400 nm is formed on the high-resistance silicon substrate 1, and a SiO ₂ film having a thickness of about 600 nm is deposited by a chemical vapor deposition (CVD) method. Thereafter, the SiO ₂ film deposited outside the trench is removed by a CMP (Chemical Mechanical Polishing) method to form an element isolation region 2 filled with an insulator called STI (Shallow Trench Isolation). Next, phosphorus (P) 61 is ion-implanted at 300 kV using the photoresist film 60 as a mask as shown in FIG. Similarly, boron (B) 62 is ion-implanted at 130 kV using the photoresist film 60 as a mask, and by subsequent heat treatment, P is activated to activate n-type well 3 and B is activated to form p-type well 4. (FIG. 2 (c)).

(2) Formation of Gate Insulating Film and Gate Electrode Next, as shown in FIG. 3A, the p-type well region 4 and the n-type well region 3 are formed from the oxide 5 to be the gate insulating films 58 and 59. It is formed on the surface of the high resistance silicon 1. As the gate insulating film, a silicon dioxide film (SiO ₂ film) or a silicon oxynitride film (SiON film) having a thickness of about 1 to ₃ nm may be deposited. However, in this embodiment, an HfSiON film expected to be put to practical use as a high dielectric constant gate insulating film is deposited to a thickness of 1.5 to 5 nm by the CVD method.

  Next, as shown in FIG. 3B, a metal film 6 having a thickness of about 1 to 10 nm is deposited on the oxide 5 to be the gate insulating films 58 and 59. The metal film 6 becomes the threshold electrode (or work function electrode) 52 of the n-channel MOSFET 50. Incidentally, the threshold value of the n-channel MOSFET 50 is determined by the difference between the work function of the metal film 6 and the Fermi level of the p-type well 4. Therefore, in order to lower the threshold value of the n-channel MOSFET 50, the work function range of the metal film 6 is preferably 3.9 to 4.4 eV. Examples of metals that satisfy such conditions include Ta, TaN, TaSi, TaSi2, and TaSixNy.

In the present embodiment, a TaSi _0.5 N ₂ film having a thickness of 5 nm is deposited as the metal film 6. The TaSi _0.5 N ₂ film is deposited by the CVD method using Ta [N (CH ₃ ) ₂ ] ₅ , NH ₃ and Si ₂ H ₆ as raw materials. The growth temperature is 480 ° C. The resulting film is an amorphous film suitable for a threshold electrode (or work function electrode). The work function of TaSi _x N _y varies in the range of 4.2 to 4.4 eV depending on the composition at the time of film formation and the subsequent heat treatment process.

  Next, as shown in FIG. 4A, a metal film 7 to be an intermediate layer 52 of the n-channel MOSFET 50 is deposited. The material constituting the metal film 7 is preferably TiN, TaN, or the like in which the grain size, crystal structure, and orientation direction of the growth film tend to be constant regardless of the underlying metal layer. TiN or TaN is deposited by a CVD method. The obtained deposited film is a polycrystal composed of microcrystals having a diameter of 10 to 20 nm.

In the present embodiment, a TiN film having a thickness of 5 to 20 nm is formed on a metal film 6 made of TaSi _0.5 N _2, that is, a threshold electrode (or work function electrode) 52 by a CVD method using TiCl ₄ and NH ₃ as raw materials. accumulate. The growth temperature is 600-650 ° C. Since TaSixNy is easily oxidized, when exposed to the atmosphere, the grain size and orientation direction of the TiN film grown on the TaSixNy are likely to be disturbed. As a result, the wiring metal layers 54 and 57 grown on the metal film 7 made of a TiN film also have a non-constant crystal grain size and orientation direction (the result is the same even if TaN is used instead of TiN as the metal film 7). .) Therefore, in the present embodiment, the metal film 6 and the metal film 7 are continuously deposited by using a cluster type CVD apparatus in which dedicated growth chambers for growing different metal films are connected. That is, the surface of the threshold electrode (or work function electrode) 52 was prevented from being exposed to the atmosphere.

Next, as shown in FIG. 4B, in order to remove the metal films 6 and 7 deposited on the region to become the p-channel MOSFET 51, a mask film 8 made of SiN is deposited to a thickness of 50 nm by the CVD method. To do. As a material for the mask film 8, SiO ₂ or Si can also be used. Further, the thickness of the mask film 8 is appropriately 20 to 100 nm.

  Next, as shown in FIG. 5A, the mask film 8 formed in the region to be the p-channel MOSFET 51 is removed using a photolithography method and a reactive ion etching method.

  Next, as shown in FIG. 5B, the metal films 6 and 7 formed in the region to be the p-channel MOSFET 51 are removed by chemical etching using the patterned mask film 8 as an etching mask. The reason why chemical etching is used to remove the metal films 6 and 7 is to minimize the process damage to the oxide 5 serving as a gate insulating film. For the chemical etching of the metal films 6 and 7, a mixed solution of ammonia and hydrogen peroxide is used. The ammonia / hydrogen peroxide mixed solution becomes TiN (metal film 7 that becomes the intermediate layer 53) and TaSixNy (threshold electrode (or work function electrode) 53 without damaging HfSiON (oxide 5 that becomes the gate insulating film). The metal film 7) is selectively etched.

Next, as shown in FIG. 6, a metal film 9 having a thickness of about 1 to 10 nm is deposited on the oxide 5. The metal 9 becomes the threshold electrode (or work function electrode) 55 of the p-channel MOSFET. Incidentally, the threshold value of the p-channel MOSFET 51 is determined by the difference between the work function of the metal film 9 and the Fermi level of the n-type well 3. Therefore, in order to lower the threshold value of the p-channel MOSFET, the work function range of the metal film 9 is preferably 4.7 to 5.3 eV. Examples of metals that satisfy such conditions include Ru, RuO ₂ , TiN, and TiSixNy.

In the present embodiment, a TiSi _0.1 N _1.1 film having a thickness of 5 nm is deposited as the metal film 9. The TiSi _0.1 N _1.1 film is deposited by CVD using TiCl ₄ , NH ₃ and N (SiH ₃ ) ₃ as raw materials. The growth temperature is 600-650 ° C. The resulting film is an amorphous film suitable for a threshold electrode (or work function electrode).

  Next, as shown in FIG. 7, a metal film 10 to be an intermediate layer 56 of the p-channel MOSFET 51 is deposited. The material constituting the metal film 10 is preferably TiN or TaN which tends to make the grain size, crystal structure, and orientation direction of the growth film constant regardless of the underlying metal layer. TiN or TaN is deposited by a CVD method. The obtained deposited film is a polycrystal composed of microcrystals having a diameter of 10 to 20 nm.

  The metal layer from the wiring metal layer 54 of the n-channel MOSFET 50 to the threshold electrode (or work function electrode) 52 and the metal layer from the wiring metal layer 57 of the p-channel MOSFET 51 to the threshold electrode (or work function electrode) 55 are simultaneously etched. It is an object of the present invention to process into a shape suitable for the gate electrode as shown in FIG. Therefore, the intermediate layer 56 of the p-channel MOSFET 51 is a conductive polycrystalline film having the same composition, grain size, crystal structure, and orientation direction as the intermediate layer 53 of the n-channel MOSFET 50. The metal layer having the same composition as that of the intermediate layer 53 of the n-channel MOSFET 50 is preferably grown under the same manufacturing method and manufacturing conditions.

Therefore, in this embodiment, a TiN film having a thickness of 5 to 20 nm is formed on a metal film 9 made of TiSi _0.1 N _1.1, that is, a threshold electrode (or work function electrode) 55 using TiCl ₄ and NH ₃ as raw materials, and an n channel. Deposited by the CVD method under the same conditions as the intermediate layer 53 of the MOSFET 50. The growth temperature is 600-650 ° C. However, the grain size and orientation direction of the TiN film and TaN film deposited by the CVD method do not change much even if the growth conditions are changed. Therefore, the growth conditions of these films are not necessarily the same.

  Since TiSixNy is easily oxidized, when exposed to the atmosphere, the grain size and orientation direction of the TiN film grown on the TiSixNy tends to be disturbed. As a result, the wiring metal layers 54 and 57 grown on the metal film 9 made of a TiN film also have a non-constant crystal grain size and orientation direction (the result is the same even when TaN is used as the metal film 9). ). Therefore, in the present embodiment, the metal film 9 and the metal film 10 are continuously deposited using a cluster type CVD apparatus in which dedicated growth chambers for growing different metal films are connected. That is, the surface of the threshold electrode (or work function electrode) 55 was prevented from being exposed to the atmosphere.

Next, as shown in FIG. 8, in order to remove the metal films 9 and 10 deposited on the region to be the n-channel MOSFET 50, a mask film 11 made of SiN is deposited to a thickness of 50 nm by the CVD method. As a material for the mask film 11, SiO ₂ or Si can also be used. The thickness of the mask film 11 is appropriately 20-100 nm.

  Next, as shown in FIG. 9, the mask film 11 formed in the region to become the n-channel MOSFET 50 is removed by using a photolithography method and a reactive ion etching method.

  Next, as shown in FIG. 10, the metal films 9 and 10 formed in the region to be the n-channel MOSFET 50 are removed by chemical etching using the patterned mask film 11 as an etching mask. For the chemical etching of the metal films 9 and 10, a mixed solution of ammonia and hydrogen peroxide is used.

Next, as shown in FIG. 11, the mask films 8 and 11 made of SiN are removed by reactive ion etching. Thereafter, as shown in FIG. 12, the metal film 12 to be the wiring metal layers 54 and 57 of the n-channel MOSFET 50 and the p-channel MOSFET 51 is deposited to a thickness of 50 to 100 nm. As the wiring metal film, W, WSi ₂ , Mo, Ta, Ru or polycrystalline silicon is preferable. Polycrystalline silicon has the advantage of easy processing.

  In the present embodiment, a metal film 12 made of W is deposited by a 50 nm sputtering method. The deposition temperature is room temperature.

Next, on the metal film 12 to be the wiring metal layers 54 and 57, the mask film 13 necessary for forming the gate electrode by processing the metal films 6, 7, 9, 10, and 12 is deposited. The mask film 13 is made of SiN and is deposited by CVD. As a material for the mask film 13, SiO ₂ may be used.

  Next, the mask film 13 is processed into a mask for reactive ion etching using photolithography and reactive ion etching. Using the processed mask film 13 as a mask, the metal films 6, 7, 9, 10, and 12 are etched by reactive ion etching, and the gate electrodes for the n-channel MOSFET 50 and the p-channel MOSFET 51 are simultaneously formed as shown in FIG. Form. The gate electrode processed in this way has an ideal shape as a gate electrode as shown in FIG. 25 in both the n-channel MOSFET 50 and the n-channel MOSFET 51.

  Next, the oxide 5 and the mask in the region except just under the gate electrode are removed with dilute hydrofluoric acid. The gate electrode serves as a mask, and the oxide 5 immediately below the gate electrode is not removed, but becomes gate insulating films 58 and 59 as shown in FIG.

  Next, as shown in FIG. 15, a sidewall spacer insulating film 14 made of SiN is formed using a CVD method and reactive ion etching.

  Next, as shown in FIG. 16, boron 62 is ion-implanted into the n-type well region at 0.4 kV using the patterned photoresist film 16. Thereafter, the resist film 16 is removed.

  Similarly, arsenic 63 is ion-implanted into the p-type well region at 2.0 kV using the patterned photoresist film 18 as shown in FIG. Thereafter, the resist film 18 is removed.

Next, an insulating film 27 made of SiO ₂ is formed by a CVD method as shown in FIG. 18, and processed into a sidewall 19 as shown in FIG. 19 by reactive ion etching.

  Next, as shown in FIG. 20, arsenic 63 is ion-implanted into the p-type well region at 25 kV using the patterned photoresist film 22. Thereafter, the resist film 22 is removed.

  Similarly, boron 62 is ion-implanted into the n-type well region at 2.0 kV using the patterned photoresist film 25 as shown in FIG. Thereafter, the resist film 25 is removed, and boron and arsenic are activated by heat treatment, and the extension region 17 and the source and drain regions 20 and 21 of the n-channel MOSFET 50, the extension region 15 of the p-channel MOSFET 51, and the source and drain regions 23 and 24 Form.

  Finally, Ni is deposited on the source and drain regions 20, 21, 23, 24, and the upper layers of the drain regions 20, 21, 23, 24 are silicided to form silicide electrodes 26 by subsequent heat treatment. A plug electrode is joined to the silicide electrode 26.

  The present invention can be used in the manufacturing industry of semiconductor integrated circuits and the manufacturing industry of electronic devices using semiconductor integrated circuits.

Cross-sectional view of CMOSFET according to the present invention Manufacturing process of CMOSFET according to the present invention (1) Manufacturing process of CMOSFET according to the present invention (2) Manufacturing process of CMOSFET according to the present invention (3) Manufacturing process of CMOSFET according to the present invention (4) Manufacturing process of CMOSFET according to the present invention (5) CMOSFET manufacturing process according to the present invention (6) Manufacturing process of CMOSFET according to the present invention (7) Manufacturing process of CMOSFET according to the present invention (8) Manufacturing process of CMOSFET according to the present invention (9) CMOSFET manufacturing process according to the present invention (10) Manufacturing process of CMOSFET according to the present invention (11) Manufacturing process of CMOSFET according to the present invention (12) Manufacturing process of CMOSFET according to the present invention (13) CMOSFET manufacturing process according to the present invention (14) CMOSFET manufacturing process according to the present invention (15) Manufacturing process of CMOSFET according to the present invention (16) Manufacturing process of CMOSFET according to the present invention (17) CMOSFET manufacturing process according to the present invention (18) CMOSFET manufacturing process according to the present invention (19) CMOSFET manufacturing process according to the present invention (20) CMOSFET manufacturing process according to the present invention (21) Cross section of conventional MOSFET Cross-sectional view of device during conventional metal gate MOSFET manufacturing process Perspective view of metal film etched into preferred shape as gate electrode

Explanation of symbols

1 High resistance silicon substrate 1
2 Element isolation region
3 n-type well region
4 p-type well region
5 Oxide used as gate insulating film
6 Metal film used as threshold electrode (or work function electrode) of n-channel MOSFET
7 Metal film to be the intermediate layer of n-channel MOSFET
8 Mask film for n-channel MOSFET region
9 Metal film used as threshold electrode (or work function electrode) of p-channel MOSFET
10 Metal film to be the intermediate layer of p-channel MOSFET
11 Mask film for p-channel MOSFET region
12 Metal film for wiring metal layer
13 Mask film for processing metal films 6, 7, 9, and 10 to form gate electrodes
14 Sidewall spacer insulating film
15 B ion implantation region to be the p-channel MOSFET extension region
16 B-type photoresist mask for p-channel MOSFET extension region formation
17 As ion implantation region to be the n-channel MOSFET extension region
18 Photomask for As ion implantation to form n-channel MOSFET extension region
19 Side wall insulating film
20 n-channel MOSFET source
21 Drain of n-channel MOSFET
22 Photoresist film used as an ion implantation mask to form the source of n-channel MOSFET
23 Drain of p-channel MOSFET
24 p-channel MOSFET source
25 n Photoresist film used as ion implantation mask to form channel MOSFET source
26 Nickel silicide contact electrode
27 SiO ₂ film used as sidewall insulating film
50 n-channel MOSFET
51 p-channel MOSFET
52 n-channel MOSFET threshold electrode (or work function electrode)
53 n-channel MOSFET interlayer
54 Wiring metal layer of n-channel MOSFET
55 Threshold electrode (or work function electrode) of p-channel MOSFET
56 p-channel MOSFET intermediate layer
57 Wiring metal layer of p-channel MOSFET
58,59 Gate insulation film
60 Photoresist film used as ion implantation mask for well formation
61 P
62 B
63 As

Claims (5)

An n-channel MOSFET having a first gate electrode composed of a first metal layer formed in contact with the gate oxide film and a first low resistance layer formed on the first metal layer;
A semiconductor having a p-channel MOSFET having a second gate electrode comprising a second metal layer formed in contact with the gate oxide film and a second low resistance layer formed on the second metal layer. In an integrated circuit device,
The first metal layer and the second metal layer are composed of metals having different work functions;
The first low resistance layer and the second low resistance layer are made of polycrystals made of the same material,
Having a first intermediate layer between the first metal layer and the first low resistance layer, and having a second intermediate layer between the second metal layer and the second low resistance layer;
A semiconductor integrated circuit device, wherein the first intermediate layer and the second intermediate layer are made of conductive polycrystalline films having the same composition, grain size, crystal structure, and orientation direction. The first metal layer and the first intermediate layer are continuously formed in the same growth apparatus;
2. The semiconductor integrated circuit device according to claim 1, wherein the second metal layer and the second intermediate layer are continuously formed in the same growth apparatus.   3. The semiconductor integrated circuit device according to claim 1, wherein the first and second intermediate layers are made of TiN or TaN. 4. The semiconductor integrated circuit device according to claim 1, wherein the same material is any one of W, WSi ₂ , Mo, Ru, Ta, and Si. An n-channel MOSFET having a first gate electrode composed of a first metal layer formed in contact with the gate oxide film and a first low resistance layer formed on the first metal layer;
A p-channel MOSFET having a second gate electrode composed of a second metal layer formed in contact with the gate oxide film and a second low-resistance layer formed on the second metal layer;
The first metal layer and the second metal layer are composed of metals having different work functions;
The first low resistance layer and the second low resistance layer are made of polycrystals made of the same material,
Having a first intermediate layer between the first metal layer and the first low resistance layer, and having a second intermediate layer between the second metal layer and the second low resistance layer;
In the method for manufacturing a semiconductor integrated circuit device, wherein the first intermediate layer and the second intermediate layer are made of a conductive polycrystalline film having the same composition, grain size, crystal structure, and orientation direction.
A step of continuously forming a first metal film to be a first metal layer and a second metal film to be a first intermediate layer in the same growth apparatus;
And a step of continuously forming a third metal film to be the second metal layer and a fourth metal film to be the second intermediate layer in the same growth apparatus. A method for manufacturing a semiconductor integrated circuit device.

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