JP2004158711A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent cracking due to warpage even when an oxide film material is formed by isolating a trench element in an SOI wafer. <P>SOLUTION: In case when a polycrystalline silicon film 13 to be used as a mask material is formed when a trench 5 is formed in the SOI wafer 1, a polycrystalline silicon film 13a remaining on its backside is removed in the following step. Thus, a recessed warpage on the upper surface of the SOI wafer 1 due to the polycrystalline silicon films 13 and 13a having compressibility is prevented. In addition, a cracking G is prevented from being caused in the trench 5 on a suction stage 21 of the device because of the recessed warpage. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a structure in which an SOI substrate is trench-isolated and an oxide film-based material is embedded in a trench.
[0002]
[Prior art]
In the manufacturing process of an SOI wafer, the wafer may be warped, and if the amount of warpage is large, a problem may occur in a subsequent step. Techniques for preventing such wafer warpage include the following.
[0003]
For example, Patent Document 1 discloses, as a technical problem to be solved, that if a wafer is too strained, it cannot be handled by a manufacturing apparatus such as an alignment chuck. This causes a loss in manufacturing yield and limits the maximum thickness of oxides that can be used (note: BOX of SOI wafer = buried oxide). Therefore, there is a need to reduce the strain caused by stress in the dielectric film of the bonded wafer.
[0004]
There is also a technique in which the warping of the wafer itself is a problem (for example, see Patent Document 2). It is an object of the present invention to prevent a crack generated in an oxide film embedded in a trench due to a warp of a wafer.
[0005]
In these devices, the stress applied to the wafer by the BOX (buried oxide film) or other insulating film of the SOI wafer, and the same type of the above-mentioned type applied to the wafer by the oxide film (or other insulating film) formed on the back surface of the SOI wafer. The wafer warpage is prevented by balancing the stresses.
[0006]
In this case, the means for achieving the balance is different between the two. That is, in the technique disclosed in Patent Document 1, the oxide film (or other insulating film) on the back surface of the wafer is etched in the wafer processing step to reduce the film thickness, thereby preventing the balance from being lost. This is because polysilicon and other films (resist, Si ₃ N ₄ ) Is realized by forming a film.
[0007]
In the technique disclosed in Patent Document 2, a film having a strong stress is formed on the back surface of the wafer in the wafer processing step, thereby preventing the balance from being lost. This is because the Si ₃ N ₄ Is removed at the initial stage of formation.
[0008]
In the above-mentioned Patent Documents 1 and 2, after forming a trench, an oxide film is formed on a trench side wall for element isolation by a thermal oxidation method, and the trench is buried with polysilicon. It describes application to the process. Further, as presumed from the examples, it is considered that the trench element isolation is performed before the element is formed.
[0009]
In addition, polysilicon was initially used as a general material as a burying material for trench element isolation. Oxide film material (SiO ₂ , BPSG, PSG, ASG, etc.) (for example, see Non-Patent Document 1 and Patent Document 3).
[0010]
The above-described problem occurs, for example, in a portion as shown in FIG. That is, FIG. 3A shows the original state of the trench formation portion, and FIG. 3B shows the state in which a crack, which is a defect, has occurred. That is, the SOI wafer 1 has the silicon single crystal layer 4 provided on the support substrate 2 via the buried oxide film (BOX) 3, and the trench 5 is formed in the silicon single crystal layer 4. The trench 5 is formed in a portion where the LOCOS 6 is formed to a depth reaching the buried oxide film 3, and the inside is filled with an oxide film 7. On the surface, an insulating film 8 is formed, and an aluminum electrode 9 and the like are formed.
[0011]
In this configuration, the trench 5 is originally formed as shown in the figure. However, because the SOI wafer 1 is warped in a concave shape, when the SOI wafer 1 is mounted on a manufacturing apparatus, it is moved in a direction indicated by an arrow in the figure. When the straightening force is applied and the state is flat, the stress at that time acts and a crack G is generated as shown in the figure.
[0012]
Looking at the generation state of the crack G, it was found that the fracture surface of the aluminum wiring was clearly seen, and that the generation of the crack G occurred after the etching process of the aluminum electrode 9 was completed. Therefore, when the photoresist removing device is used after the etching process is completed, a structure in which the portion on which the wafer is mounted is fixed by adsorbing the entire back surface of the wafer is employed. The warped SOI wafer 1 is corrected to a flat state.
[0013]
As a result, it is presumed that a tensile stress acts on the oxide film 7 as a buried material inside the trench 5 to cause cracks in the oxide film 7 and disconnect the aluminum electrode 9. In this state, not only a defective product due to the disconnection of the pattern of the aluminum electrode 9 but also a problem that reliability is reduced due to generation of the crack G is caused.
[0014]
FIG. 9 shows an example in which the amount of warpage of the SOI wafer 1 and the state of occurrence of cracks G are examined. For example, in the sample A of FIG. 9A, the amount of warpage is concave and −60 μm (representation of the convex shape as plus). At this time, 16% of the chips in which cracks G occurred around the wafer were generated. is there. Similarly, in Sample B of FIG. 3B, the amount of warpage is concave and is −90 μm, and at this time, 24% of the chips have cracks G around the wafer.
[0015]
From this result, it can be seen that the larger the concave wafer warpage amount, the higher the crack occurrence rate in the peripheral portion, indicating a tendency consistent with the above-mentioned estimated cause. Therefore, it can be seen that it is necessary to reduce the amount of wafer warpage into a concave shape as a countermeasure.
[0016]
Next, a brief description will be given of a manufacturing process in a case where the above-described problem occurs. 10 to 13 show schematic cross sections of the semiconductor device shown according to the manufacturing process. In this manufacturing process, a process in which the trench 5 is formed after semiconductor elements are formed on the SOI wafer 1 is adopted.
[0017]
In the device fabrication process, the CMOS 10 and the bipolar transistor 11 are fabricated on the SOI wafer 1 while being separated by the LOCOS 6 (see FIG. 10A). In this state, an oxide film 12 is formed on the back side of the SOI wafer 1. Subsequently, a polycrystalline silicon film 13 serving as a trench processing mask and an oxide film 14 are stacked (see FIG. 2B). At this time, a polycrystalline silicon film 13a is simultaneously formed on the back surface of the SOI due to the manufacturing process.
[0018]
Next, in order to form the trench 5, a trench mask pattern 15 is formed in the oxide film 14, the polycrystalline silicon 13 and the LOCOS 6 (see FIG. 3C), and thereafter, the silicon single crystal layer 4 is formed by dry etching. A trench 5 is formed (see FIG. 11D).
[0019]
After a thin thermal oxide film 16 is formed on the side wall of the trench 5 (see FIG. 5E), an oxide film-based material 17 as a filling material is formed so as to fill the trench 5 (see FIG. 5F). ). At this time, an oxide film 17a is simultaneously formed on the back surface of the SOI wafer 1 due to the manufacturing process. The oxide film-based materials 17 and 14 are peeled off by an etch-back process using the polycrystalline silicon film 13 as a stopper (see FIG. 12G), and then the polycrystalline silicon film 13 is peeled off by an etching process using the oxide film as a stopper. (See (h) in the figure). As a result, the trench 5 is formed in a state where the oxide film-based material 17 is filled.
[0020]
Thereafter, an interlayer film 18 is formed on the surface (see FIG. 13 (i)), a contact hole 19 is formed (see FIG. 13 (j)), and an aluminum electrode film 20 is formed (see FIG. 13 (k)). Reference) The wafer manufacturing process ends.
[0021]
[Patent Document 1]
Japanese Patent Publication No. Hei 8-501900
[0022]
[Patent Document 2]
JP-A-7-153835
[0023]
[Patent Document 3]
JP-A-61-107738
[0024]
[Non-patent document 1]
Hideki Tsuya, "Super LSI Process Control Engineering," Maruzen, March 1995, p. 44-47
[0025]
[Problems to be solved by the invention]
However, the conventional technique as described above has the following disadvantages. That is, the use of the oxide film-based material 17 as a material for burying the trench 5 is a problem that causes the warpage of the SOI wafer 1 and thereby causes the crack G to occur.
[0026]
The above-described oxide film-based material 17 is generally formed by the CVD method, but an oxide film is formed from both side walls of the trench 5 and the surfaces formed from the both side walls coincide with each other at the center of the trench. When it is closed, the embedding of the groove is completed. The oxide film-based material 17 tends to generate cracks G due to tensile stress applied to the film. In particular, the oxide film-based material 17 formed by a CVD method or the like often has a weak mechanical strength.
[0027]
If the SOI wafer 1 in which the trench 5 is buried with the oxide film-based material 17 is concavely warped with respect to the upper surface, even if the amount of warpage is within a range that can be handled by a manufacturing apparatus such as an alignment chuck, the alignment chuck may be used. When the SOI wafer 1 is stretched flat, a tensile stress is applied to the oxide film-based material 17 buried in the trench 5, and the SOI wafer 1 itself does not crack. At least, cracks G may occur inside trench 5.
[0028]
If the crack G occurs before the formation of the wiring, it is impossible to form the wiring formed in the trench isolation portion (crossing the trench portion). If a crack G occurs after the formation of the wiring, the wiring pattern will be disconnected at that position. Therefore, in any case, it is urgently necessary to take measures to prevent the crack G from occurring.
[0029]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a configuration in which a trench is formed on an SOI wafer to perform element isolation. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing a high-quality semiconductor device by minimizing cracks generated in a manufacturing process.
[0030]
[Means for Solving the Problems]
The present invention employs the following means to solve the above problems. That is, in the method of manufacturing a semiconductor device according to claim 1, a trench isolation region is formed in an SOI substrate having a semiconductor layer formed on a substrate via a buried insulating film, and an oxide film is formed at least in a surface portion in the trench. In a method of manufacturing a semiconductor device in which a material is formed, when a film having compressive stress is formed as a film for forming a trench in a process of forming a trench isolation region, the compressive stress also has on the back surface of the substrate. When a film is formed, a compressive film removing step of removing a compressible film formed on the back surface of the substrate in a subsequent step is provided.
[0031]
Thereby, it is possible to prevent the element forming surface side of the SOI substrate from warping in a concave shape. In this case, when the compressive film removing step is performed, the element formation surface side of the SOI substrate can be maintained in a convex shape. It will be possible to keep them close. As a result, it is possible to prevent the occurrence of cracks even when the wafer is placed on the manufacturing apparatus and sucked.
[0032]
FIG. 1 schematically shows the production method of the present invention. FIG. 1A shows the configuration of the SOI substrate 1. A silicon single crystal layer 4 is provided on a supporting substrate 2 with a buried oxide film 3 interposed therebetween, and an oxide film 12 is formed on the back surface. A polycrystalline silicon film 13 and an oxide film are formed as a processing mask. A polycrystalline silicon film 13a is formed on the back surface.
[0033]
After the trench 5 is formed (see FIG. 4B), the compressed film removing step of the present invention is performed to remove the back-side polycrystalline silicon film 13a acting as the compressed film, and an oxide film 17 is formed in the trench 5. An embedding process is performed (see FIG. 3C). In this case, since the polycrystalline silicon film 13a has been removed, the SOI substrate 1 is suppressed from warping concavely toward the upper surface. Thereafter, even when the substrate is placed on the suction stage 21 of the manufacturing apparatus for processing such as electrode formation, it is possible to prevent cracks from being generated in the trench 5 due to warpage.
[0034]
On the other hand, in the prior art, as shown in FIG. 1E, the stress of the polycrystalline silicon film 13a remaining on the back surface of the SOI substrate 1 acts, so that the oxide film 17 is formed in the trench 5. When the step of embedding is carried out, there is a high tendency to be concavely warped with respect to the upper surface. If the amount of the warpage is large, cracks G are generated in the oxide film 17 that fills the trench 5 by being corrected to a flat shape when placed on the suction stage 21 of the manufacturing apparatus.
[0035]
This is because, as described above, even if the warpage of the SOI substrate 1 is within the range that can be mounted on the suction stage 21, that is, the warpage is such that a crack is not formed in a normal wafer, This results in the crack G being generated. The present inventor has identified a polycrystalline silicon film formed on the back surface which causes such a phenomenon in order to suppress cracks G generated due to concave warping, and this compressive stress is reduced. The problem is solved by finding that it has a concave shape due to having it, and providing a step of removing this in advance. Also, in investigating the cause, the idea of removing the film having compressive stress was conceived, and conversely, by forming the film having tensile stress, it was found that the same operation and effect could be brought about. is there.
[0036]
According to the fifth aspect of the present invention, a trench isolation region is formed in an SOI substrate having a semiconductor layer formed on a substrate via a buried insulating film, and an oxide film material is buried in at least a surface portion in the trench. In the method for manufacturing a semiconductor device, when a film having compressive stress is formed as a film for forming a trench in the process of forming the trench isolation region, a film having the compressive stress is also formed on the back surface of the substrate. Then, in a subsequent step, a tensile film forming step of forming a tensile film on the back surface of the substrate so as to obtain a stress balance is performed.
[0037]
Thus, similarly to the first aspect of the present invention, it is possible to prevent the element forming surface side of the SOI substrate from warping in a concave shape. In this case, when the tensile film forming step is performed, the stress can be positively balanced, whereby the element forming surface side of the SOI substrate can be maintained in a convex shape and the concave shape can be maintained. Thus, the tendency to crack can be suppressed to prevent the occurrence of cracks.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Note that, in the following description, the same parts as those in the related art are denoted by the same reference numerals. FIG. 2 schematically shows each step of forming a trench isolation region in an SOI wafer 1 which is an SOI substrate. FIGS. 3 to 6 show schematic cross sections of the SOI wafer 1 corresponding to the respective steps. Hereinafter, description will be made in the order of steps.
[0039]
FIG. 3A shows a state in which semiconductor elements have been formed on the front side of the SOI wafer 1 which is an SOI substrate. In this step, through a bipolar, CMOS, power (DMOS) element diffusion layer and gate electrode forming step P1, for example, the COM 10 and the bipolar transistor 11 are formed in the illustrated state.
[0040]
In the CMOS 10, the source and drain regions are formed in each of the regions where the p-type and n-type wells are formed in the silicon single crystal layer 4, and a gate oxide film and a gate electrode are formed. In the bipolar transistor 11, a base diffusion region and an emitter diffusion region are formed, and each region is separated by a LOCOS 6 formed on the front surface side. In this state, the oxide film 12 is formed on the back surface. Then, the SOI wafer 1 is in a warped state such that the central portion on the front surface side is convex.
[0041]
Next, in a trench processing mask forming step P2, a polycrystalline silicon film 13 which is a film having a compressive stress is formed on the surface side, and an oxide film 14 serving as a trench etching mask is formed ( FIG. In this step, a polycrystalline silicon (PolySi) film having a thickness of 300 to 800 nm is formed by LP-CVD as an element protection mask at the time of SiO2 etching at the time of anisotropic etch-back processing required in a later step. are doing. At this time, a polycrystalline silicon film 13a having the same thickness is also formed on the back surface side of the SOI wafer 1.
[0042]
The polycrystalline silicon film 13a formed on the back side is not necessary for the structure of the element, but may be formed on the back side if this does not adversely affect the element structure. It was not particularly necessary to remove them or prevent them from being formed. That is, in the range of the related art, the polycrystalline silicon film 13a formed on the rear surface side does not need to be considered at all.
[0043]
Subsequently, an oxide film (SiO 2) 14 that functions as an etching mask when forming the trench is formed. As a forming method, for example, a film is formed to a thickness of about 0.5 to 1.0 μm by a plasma CVD method using TEOS as a main component gas. In the state where the two-layer mask is formed on the front surface side of the SOI wafer 1 as described above, the SOI wafer 1 is warped in a convex shape as described above.
[0044]
Next, in the backside polysilicon removal step P3, which is a compressible film removal step in the present invention, the remaining polysilicon film 13a formed on the backside as a film having a compressive stress is removed by etching. FIG. (C). In this case, there are two removal methods.
[0045]
One is a method in which a photoresist is applied only to the front surface side of the SOI wafer 1 and used as an etching mask (application only may be performed), and the back surface is etched away by wet etching using a mixed solution of HF and HNO3. . The other is a method in which a photoresist is similarly applied to the front side and used as a mask, and the back side is removed by dry etching. In the dry etching process, O2 and CF4 gases are used, and a dry etching apparatus having a structure in which the back surface of the wafer is exposed, such as a cylindrical plasma etching apparatus in which a wafer is loaded on a boat, is used.
[0046]
When this step is completed, SOI wafer 1 is in a state where polycrystalline silicon film 13 and oxide film 14 are formed on the surface side. Then, the back surface side has the polycrystalline silicon film 13a removed, and is in the state at the time of the process P1. In this state, the SOI wafer 1 is warped convexly toward the front surface side, and the amount of warpage is larger than that after the trench processing mask forming step P2.
[0047]
Subsequently, the process proceeds to a trench etching pattern forming step P4. Here, an etching pattern 15 at the time of trench etching is formed on the oxide film 14, the polycrystalline silicon film 13, and the LOCOS 6 as the mask material formed in the previous step P2 (see FIG. 4D).
[0048]
In the pattern formation process, after performing a photolithography process to form a pattern using a photoresist, an etching process is continuously performed by a dry etching process. By changing the gas conditions in the middle, three layers of films made of different materials can be sequentially and continuously etched. Thereafter, the photoresist is removed, and the process is completed.
[0049]
Next, in a trench forming step P5, a trench 5 is formed in the silicon single crystal layer 4 by dry etching using the mask pattern 15 (see FIG. 4E). At this time, the upper oxide film 14 functions as an etching mask. After the formation of the trench 5, in order to obtain a vertical trench shape, the etching protection film formed on the side wall of the trench 5 during dry etching is removed by HF (hydrogen fluoride) cleaning.
[0050]
Subsequently, in a trench side wall oxidation step P6, the thermal oxidation film 16 is formed by oxidizing the silicon 4 on the side walls of the trench 5 in a diffusion furnace (see FIG. 4F). The conditions of the oxidation treatment are such that a thermal oxide film 16 having a thickness of about 100 to 200 nm grows at a temperature of 900 ° C. or less.
[0051]
Thereafter, a film forming process P7 of an oxide film-based burying material in the trench is performed. As shown in FIG. 5G, this is a processing step of burying an oxide film-based material 17 inside the trench 5. The oxide film material 17 is formed using an oxide film (SiO 2) formed by LP-CVD using TEOS as a main component gas.
[0052]
Here, the material to be buried in the trench 5 may be an oxide film-based material. In addition, BPSG, PSG, or the like can be used. The burying material is formed on the entire front surface of the SOI wafer 1. In order to close the trench 5, it is necessary to form a film having a thickness at least half the width of the opening.
[0053]
After the completion of the film formation, the amount of the current oxide film-based material 17 is accumulated on the oxide film 14 used as a mask on the surface of the SOI wafer 1. On the back side, the oxide film-based material 17a is formed on the oxide film 12 under the same conditions as the oxide film-based material 17 on the front surface.
[0054]
Next, a step P8 of removing the oxide film-based material 17 formed in a portion other than the trench 5 is performed (see FIG. 3H). As a specific process, an etch-back process is performed by dry etching. The etch-back process is a process in which an etching process is performed without forming a film such as a photoresist by a photolithography process.
[0055]
Here, the etching is performed by a magnetron RIE etching apparatus using CHF3, CF4, and Ar gas. In this step, in addition to the burying material, the oxide film 14 on the polycrystalline silicon film 13 functioning as a mask when forming the trench 5 is also removed. The polycrystalline silicon film 13 functions to protect an already formed region of the semiconductor element during the etch-back process.
[0056]
Subsequently, a step P9 of removing the polycrystalline silicon film 13 functioning as a protective film at the time of the etch-back process is performed (see FIG. 1I). For example, an isotropic dry etching process using CF4 and O2 gas is performed. This completes the trench element isolation processing. In this state, on the front side of the SOI wafer 1, all the films deposited in the process P2 and thereafter are removed, and the state returns to the state shown in FIG. Also, on the back side of SOI wafer 1, oxide films 12 and 17a remain.
[0057]
After the trench element isolation process is completed, a process P10 for forming the interlayer insulating film 18 is performed (see FIG. 6 (j)). Here, the interlayer insulating film 18 is formed by forming a BPSG film having a P (phosphorus) concentration of about 5 w% and a B (boron) concentration of about 3 w% by a CVD method under normal pressure. After the film formation, an annealing process (reflow process) at 800 to 1000 ° C. is performed to improve the shape of the step film of the BPSG. Here, no film is formed on the back side due to the configuration of the apparatus.
[0058]
Next, in a step P11 of forming a contact hole in the interlayer insulating film 18, a contact hole 19 is formed (see FIG. 9 (k)). The contact hole 19 is subjected to a general photolithography process using a photoresist, and the etching is performed by a dry etching process to remove the photoresist. Also in this case, since the back surface is not etched due to the structure of the apparatus, the film structure on the back surface does not change.
[0059]
Finally, a wiring forming step P12 is performed (see FIG. 1 (l)). Here, an aluminum alloy (AlSi, AlSiCu, or the like) is formed over the entire surface by about 0.4 to 1.0 μm by a sputtering method. Then, an aluminum electrode 20 is formed by forming an electrode pattern by dry etching by photolithography. After the dry etching process, the photoresist is removed. Thus, the wafer manufacturing process is completed.
[0060]
Next, a description will be given of the contents verified by experiments that the problems in the conventional technology have been solved by adopting the above manufacturing process.
In each of the above steps, the amount of warpage of the SOI wafer 1 is measured. FIG. 7 shows the data, and also shows data in the prior art for comparison. The vertical axis indicates the amount of warpage of the SOI wafer 1, and the horizontal axis indicates changes in time series in the order of processes. As for the amount of warpage, an upper part from the broken line is shown as a convex warp state, and a lower part is shown as a concave warp state.
[0061]
In the drawing, in the data of the present embodiment, the average data is indicated by a circle, and the upper and lower limits of sample variation are indicated by error bars. The transition of each process is shown connected by a solid line. Further, in the data of the related art, the difference is that the mark indicates average data and the transition is indicated by a broken line.
[0062]
In the present embodiment (hereinafter, referred to as the product of the present invention) and the conventional technology (hereinafter, referred to as the conventional product), in the manufacturing process, the present embodiment has a backside polysilicon removing process P3, whereas the conventional technology does not have this. However, it is a difference. Then, this difference becomes a large difference in the final state, that is, at the time when the wiring forming step P12 is completed, and the effect of the present embodiment that cracks do not occur appears.
[0063]
First, up to the process P2, since the product of the present invention and the conventional product have the same structure in the same process, the data transition is the same. In the product of the present invention, the amount of warpage increases in the convex direction after the process P3, and the amount of warpage tends to decrease as the process passes. Eventually, after the process P12, a convex warpage remains. On the other hand, in the conventional product, the amount of convex warpage tends to decrease slightly after the process P2 and before the process P9, but after the process P9, the amount of the concave warpage sharply occurs. , The state is reversed. Further, the variation at this time is quite large, and the state is unstable. This concave warpage does not recover and continues to the final step.
[0064]
As a result, in this embodiment, since the amount of convex warpage remains in the wiring forming step P12, the SOI wafer 1 is embedded in the trench 5 when the SOI wafer 1 is mounted on the suction stage 21 of the manufacturing apparatus. The oxide film-based material 17 does not generate cracks G.
[0065]
Further, since the polycrystalline silicon film 13a and the oxide film 14 are formed as a trench processing mask in the process P2 and the polycrystalline silicon film 13a and the oxide film 14 are continuously removed, the polycrystalline silicon film 13a is removed. The residual stress due to the film 13a can be reduced as much as possible, and the occurrence of concave warpage of the SOI wafer 1 can be suppressed.
[0066]
The present invention is not limited to the above embodiment, but can be modified or expanded as follows.
In the above embodiment, the compressive film removing step is provided to prevent the SOI wafer 1 from warping in a concave shape. However, instead of removing the compressible film, the SOI wafer 1 may be replaced with a tensile film. A similar effect can be obtained by forming the same on the back surface of the first member. In this case, it is effective to use, for example, a silicon nitride film (SiN) as the film having a tensile stress. Alternatively, any film other than the silicon nitride film may be used as long as it has a tensile stress.
[0067]
In this case, the thickness of the silicon nitride film to be formed is set to an appropriate condition in consideration of the amount of warpage of the SOI wafer 1 and the stress balance between the film having compressibility and the SOI wafer at the time when the final process is completed. 1 can be made to have a convex shape and an appropriate amount of warpage.
[0068]
In the above embodiment, the polycrystalline silicon film 13a formed on the back surface side as the compressive stress film is performed after the process P2, but may be performed later. The effect of the present invention can be obtained by providing somewhere in the process before the process P9.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view for schematically explaining the present invention.
FIG. 2 is a schematic flow chart of a manufacturing process showing an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing each stage of a manufacturing process (part 1).
FIG. 4 is a schematic cross-sectional view showing each stage of a manufacturing process (part 2).
FIG. 5 is a schematic cross-sectional view showing each stage of the manufacturing process (part 3).
FIG. 6 is a schematic cross-sectional view showing each stage of the manufacturing process (part 4).
FIG. 7 is a transition diagram of data on the amount of warpage of the SOI wafer measured at each stage of the manufacturing process.
FIG. 8 is a schematic cross-sectional view of a trench and a diagram showing a crack formation state for explaining a conventional technique.
FIG. 9 is a measurement result showing the tendency of cracks and aluminum breaks on SOI wafers.
FIG. 10 is a schematic cross-sectional view showing each stage of a conventional manufacturing process (part 1).
FIG. 11 is a schematic cross-sectional view showing each stage of a conventional manufacturing process (part 2).
FIG. 12 is a schematic cross-sectional view showing each stage of a manufacturing process of the related art (part 3).
FIG. 13 is a schematic cross-sectional view showing each stage of a manufacturing process of the related art (part 4).
[Explanation of symbols]
1 is an SOI wafer (SOI substrate), 2 is a support substrate, 3 is a built-in oxide film, 4 is a silicon single crystal layer, 5 is a trench, 6 is a LOCOS, 10 is a CMOS, 11 is a bipolar transistor, 12 is an oxide film, 13 is a polycrystalline silicon film, 13a is a polycrystalline silicon film (compressible film), 14 is an oxide film, 15 is a trench pattern, 16 is a thermal oxide film, 17 is an oxide film material, and 21 is an adsorption stage.

Claims (9)

A method of manufacturing a semiconductor device, wherein a trench isolation region is formed in an SOI substrate having a semiconductor layer formed on a substrate via a buried insulating film, and an oxide film-based material is formed on at least a surface portion in the trench.
In the process of forming the trench isolation region, when a film having compressive stress is also formed on the back surface of the substrate when a film having compressive stress is formed as a film for forming a trench, the film is formed in a subsequent step. A method for manufacturing a semiconductor device, comprising a compressible film removing step of removing the compressible film formed on a back surface of a substrate. The method for manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the step of removing the compressive film is performed subsequent to a step of forming a film having compressive stress on the back surface of the substrate. The method for manufacturing a semiconductor device according to claim 1, wherein
In the case where the trench isolation region of the semiconductor device is embedded with an oxide film-based material,
In the step of forming the trench isolation region, a polycrystalline silicon film formed as a film having compressibility is removed in the compressible film removing step in a configuration of a film formed as a processing mask when forming the trench. A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein
In the case of a configuration in which the trench isolation region of the semiconductor device is embedded with polycrystalline silicon via an oxide-based material,
In the method of manufacturing a semiconductor device, in the step of forming the trench isolation region, the one in which the polycrystalline silicon film used for the filling is simultaneously formed on the back surface is removed in the compressible film removing step. A method of manufacturing a semiconductor device, wherein a trench isolation region is formed in an SOI substrate having a semiconductor layer formed on a substrate via a buried insulating film, and an oxide film material is buried at least in a surface portion of the trench.
In the process of forming the trench isolation region, when a film having compressive stress is also formed on the back surface of the substrate when a film having compressive stress is formed as a film for forming a trench, the film is formed in a subsequent step. A method for manufacturing a semiconductor device, comprising: performing a tensile film forming step of forming a film having a tensile property on a back surface of a substrate so as to obtain a stress balance. The method for manufacturing a semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the film having a tensile stress formed in the tensile film forming step is a silicon nitride film. The method for manufacturing a semiconductor device according to claim 5, wherein
The method of manufacturing a semiconductor device, wherein the step of forming a tensile film is performed subsequent to a step of forming a film having a compressive stress on the back surface of the substrate. The method of manufacturing a semiconductor device according to claim 5,
In the case where the trench isolation region of the semiconductor device is embedded with an oxide film-based material,
In the step of forming the trench isolation region, the tensile film forming step is performed after a polycrystalline silicon film formed as a film having compressibility is formed with a structure of a film formed as a processing mask when forming the trench. A method of manufacturing a semiconductor device, wherein a stress balance is achieved by performing the following. The method of manufacturing a semiconductor device according to claim 5,
In the case of a configuration in which the trench isolation region of the semiconductor device is embedded with polycrystalline silicon via an oxide-based material,
In the method of manufacturing a semiconductor device, in the step of forming the trench isolation region, the step of forming the tensile film is performed after the polycrystalline silicon film used for the filling is simultaneously formed on the back surface.

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