JP2004158603A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having a simple structure and capable of sufficiently suppressing a change in device characteristics is provided.
A semiconductor element includes a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer 48 is formed above the semiconductor layer 24 and includes a termination material that terminates dangling bonds at the interface of the semiconductor layer 24. The second insulating layer 50 is formed on the upper side of the first insulating layer 48, and suppresses the termination material included in the first insulating layer 48 from being diffused above the second insulating layer 50, and the second insulating layer 50 has a second insulating layer 50. This prevents a substance causing a change in device characteristics existing above the layer 50 from reaching the vicinity of the interface of the semiconductor layer 24.
[Selection diagram] Fig. 1

Description

[0001]
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
(Prior Art 1) Patent Literature 1 discloses a MIS element having a metal-insulator-semiconductor (MIS) structure, and a layer formed above the MIS element and supplying hydrogen to a gate insulating film of the MIS element. A semiconductor device having a hydrogen-containing film and a diffusion prevention film formed above the hydrogen-containing film for suppressing outward diffusion of hydrogen contained in the hydrogen-containing film is shown.
When hydrogen is supplied from the hydrogen-containing film to the gate insulating film, dangling bonds at the interface between the gate insulating film and the semiconductor layer are terminated by the hydrogen, and the interface state can be reduced. Therefore, in the technique of Patent Document 1, by providing a diffusion prevention film that suppresses outward diffusion of hydrogen contained in the hydrogen-containing film, hydrogen is efficiently supplied to the gate insulating film of the MIS element. I have. Thus, dangling bonds at the interface between the gate insulating film and the semiconductor layer can be efficiently terminated by hydrogen, and the interface state can be reduced. As a result, fluctuations in element characteristics can be suppressed.
[0003]
[Patent Document 1]
JP-A-2002-16249
[0004]
(Prior art 2) In addition, mobile ions (for example, Na ⁺ As a result of the ions reaching the interface of the semiconductor layer, electric charges are induced on the surface of the semiconductor layer, causing a problem that the element characteristics fluctuate. In order to cope with this problem, a silicon nitride layer (P-SiN layer) formed by a plasma CVD (Chemical Vapor Deposition) method is formed above the semiconductor layer so that mobile ions and the like reach the interface of the semiconductor layer. There is a structure to prevent it.
[0005]
(Prior Art 3) Furthermore, as a result of mobile ions (eg, hydrogen ions) in the layers constituting the semiconductor element itself, such as hydrogen in the P-SiN layer, reaching the interface of the semiconductor layer, the element characteristics fluctuate. There is a problem. In order to address this problem, a layer capable of gettering mobile ions such as BPSG or PSG is provided between the semiconductor layer and the P-SiN film or the like, so that the mobile ions or the like reach the interface of the semiconductor layer. There is a structure to prevent it.
[0006]
[Problems to be solved by the invention]
The structure of the prior art 1 has a function of efficiently terminating dangling bonds at the interface of the semiconductor layer and reducing the interface state. By adopting this structure, it is intended to suppress a change in element characteristics.
The structures of prior arts 2 and 3 have a function of preventing movable ions and the like from reaching the interface of the semiconductor layer. By adopting this structure, it is intended to suppress a change in element characteristics.
Both of these functions (a function of efficiently terminating dangling bonds at the interface of the semiconductor layer to reduce the interface state and a function of preventing mobile ions and the like from reaching the interface of the semiconductor layer) are provided. According to the semiconductor element, variation in element characteristics can be suppressed more sufficiently than a semiconductor element having only one of these functions. Furthermore, if these functions can be realized with a simplified structure as compared with the structure of the related art 1 and the structures of the related arts 2 and 3 separately adopted, the semiconductor device can be simplified, and the cost can be reduced. The advantages such as the improvement in reliability can be obtained.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of sufficiently suppressing a change in device characteristics with a simple structure.
[0008]
Means, actions and effects for solving the problem
A semiconductor device embodying the present invention includes a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is formed above the semiconductor layer and includes a termination material that terminates a dangling bond near an interface of the semiconductor layer. The second insulating layer is formed above the first insulating layer, and suppresses a termination material included in the first insulating layer from diffusing above the second insulating layer, and is formed above the second insulating layer. Of the device characteristics existing in the semiconductor layer is prevented from reaching the vicinity of the interface of the semiconductor layer.
Another semiconductor device embodying the present invention also includes a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is formed above the semiconductor layer and contains at least one of hydrogen (H), deuterium (D), and fluorine (F). The second insulating layer is formed above the first insulating layer, and the second insulating layer is formed of SiN, AlN, WN, Al _x O _y , TiO _x , MgO _x , ZrO _x , Ta ₅ O ₃ , CeO ₂ , IrO _x , RuO _x , ReO _x , Al _x Si _y O _z , MgTiO _x , SrRuO ₃ Is formed by at least one of the following.
Here, the semiconductor layer and the first insulating layer, or the first insulating layer and the second insulating layer may not be in direct contact with each other, and the semiconductor layer and the first insulating layer, or the first insulating layer and the second insulating layer may not be in direct contact with each other. Another layer may be interposed between them. Examples of the “substance causing change in device characteristics” include mobile ions, moisture, hydrogen, impurities, and the like.
[0009]
These semiconductor elements have a function of suppressing the termination material contained in the first insulating layer from diffusing above the second insulating layer, and a function of preventing a substance causing a change in element characteristics from reaching the vicinity of the interface between the semiconductor layers. One of the features is that a single layer (second insulating layer) has the function of performing As described above, by giving the two functions described above to one layer (second insulating layer), the structure is simpler than the structure where the above-described two functions are provided to separate layers. Fluctuations can be sufficiently suppressed.
[0010]
The first insulating layer preferably contains at least one of deuterium (D) and fluorine (F). It is preferable to further include an insulating protective layer formed above the second insulating layer. It is preferable that the semiconductor device further includes an oxide insulating layer formed between the semiconductor layer and the first insulating layer. The semiconductor layer preferably has an element peripheral portion including a guard ring region, and the first insulating layer and the second insulating layer are preferably formed above the element peripheral portion. A semiconductor further comprising a gate insulating film and a gate electrode sequentially formed on the semiconductor layer, wherein a channel is formed on a surface portion of the semiconductor layer facing the gate electrode with the gate insulating film interposed therebetween; It is preferable that a first insulating layer and a second insulating layer are formed above the surface of the layer.
A method of manufacturing a semiconductor device embodying the present invention is the above-described method of manufacturing a semiconductor device, and includes a step of performing a heat treatment after forming a first insulating layer and a second insulating layer above a semiconductor layer.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
First Embodiment FIG. 1 is a schematic sectional view of an insulated gate bipolar transistor (hereinafter, referred to as “IGBT”) according to a first embodiment of the present invention. This schematic cross-sectional view shows an element operation section A in which operation as an IGBT is performed, and an element peripheral section (also referred to as an element outside section or a withstand voltage holding section) B formed outside the element operation section A. FIG. 2 is an enlarged sectional view of a portion surrounded by a dashed line C in FIG.
As shown in FIG. 1, the semiconductor layer (silicon layer in this embodiment) 24 of the IGBT is formed of p ⁺ Type collector region 26 and n in contact therewith ⁺ Mold buffer region 28 and n adjacent thereto ⁻ Type drift region 30, ap type body region 38 in contact therewith, and an n ⁺ A mold emitter region 40 is provided. Further, the semiconductor layer 24 has p ⁺ Type guard ring regions 42 and 44 and p ⁺ A mold channel stopper region 32 is provided. The p-type guard ring region 44 is formed not only in two as shown in FIG. 1 but also in a large number as shown in FIG. Note that these guard ring regions 42 and 44 may be referred to as field limiting ring (FLR) regions. These regions 42, 44 and 32 shown in FIG. ⁻ In contact with the mold drift region 30 (n ⁻ Mold drift region 30).
[0012]
The semiconductor layer 24 has a predetermined depth from the surface (in this embodiment, n ⁻ A plurality of trenches 33 reaching the upper part of the mold drift region 30) are formed. Gate electrodes 36 are buried in these trenches 33 with a gate insulating film 34 interposed therebetween. The gate electrode 36 has n ⁻ Type drift region 30 and n ⁺ Adjacent to the region 38a of the p-type body region 38 located between the mold emitter regions 40. When the IGBT is turned on, an n-type channel is formed in the region 38a of the p-type body region 38 adjacent to the gate electrode 36. As described above, the IGBT of the present embodiment is a so-called trench gate type IGBT. The semiconductor layer 24 may be composed entirely of one semiconductor substrate, may be composed of a semiconductor substrate and one or more epitaxial layers laminated thereon, or may have another configuration. Is also good.
[0013]
On the semiconductor layer 24, a layer structure 45 and electrode layers (also referred to as wiring layers) 54, 58, and 60 are formed. The layer structure 45 is basically formed over the entire surface of the semiconductor layer 24, but partially has a plurality of contact holes. A part of the electrode layers 54, 58, 60 enters into the contact holes. The electrode layer 54 is connected to the channel stopper region 32. The electrode layer 58 is made of p ⁺ It is connected to the mold guard ring region 44. The electrode layer (emitter electrode) 60 is composed of n ⁺ It is connected to the type emitter region 40 and the p-type body region 38. A protective layer 56 is formed on the layer structure 45 and the electrode layers 54, 58, 60. On the back surface of the semiconductor layer 24, a collector electrode 22 is formed. Note that the electrode layers 54, 58, and 60 may have a multilayer structure.
[0014]
The layer structure 45 has a laminated structure in which a lower insulating layer 46, a first insulating layer 48, a second insulating layer 50, and an upper insulating layer 52 are sequentially stacked.
The lower insulating layer 46 may be formed of an insulating material. Preferably, the lower insulating layer 46 includes a silicon oxide film formed by oxidizing the silicon layer 24 by a thermal oxidation method, a silicon oxide film formed by a CVD method, and an oxide film such as BPSG, PSG, or SOG as a main constituent material. It is preferable that this is an oxide insulating layer. Further, a combination of these materials may be used.
[0015]
In general, the oxide insulating layer has good insulating properties and a small proportion of a substance (particularly, hydrogen) that causes a change in element characteristics. Therefore, when the lower insulating layer 46 formed between the semiconductor layer 24 and the first insulating layer 48 is formed of an oxide insulating layer, the insulating properties of the element can be maintained well. On the other hand, even when the oxide insulating layer 46 is formed between the semiconductor layer 24 and the first insulating layer 48, the ratio of a substance causing a change in element characteristics (particularly, hydrogen) to reach the vicinity of the interface of the semiconductor layer 24 is small. Almost no change in device characteristics occurs. In the present embodiment, the lower insulating layer 46 is formed of a silicon oxide film by a thermal oxidation method. In this case, the lower insulating layer 46 may be called a field oxide film.
Similarly, the upper insulating layer 52 may be formed of an insulating material. The upper insulating layer 52 may be an oxide insulating layer like the lower insulating layer 46, a nitride insulating layer mainly including a nitride film, or an insulating material such as TEOS. There may be. In the present embodiment, the upper insulating layer 52 is formed of a silicon oxide film by a CVD method. The upper insulating layer 52 can be said to be an insulating protective layer formed above the second insulating layer 50.
[0016]
The first insulating layer 48 includes a termination material that terminates dangling bonds near the interface of the semiconductor layer 24. Therefore, the first insulating layer 48 can be said to be a termination material containing layer. The termination material is hydrogen (H ₂ ), Deuterium (D) and fluorine (F). Among these, at least one of deuterium and fluorine is particularly preferred.
The first insulating layer 48 is preferably formed by a nitride film formed by a CVD method (plasma CVD method) containing these terminal materials. The nitride film formed by the CVD method can easily contain a large amount of the above-mentioned termination material.
[0017]
As a method of manufacturing a silicon nitride film containing deuterium (D) or fluorine (F) by a CVD method, which is preferable as a material of the first insulating layer 48, for example, the following method can be mentioned.
(1) Silicon tetrafluoride (SiF ₄ ) And ammonia (NH ₃ Or ND ₃ The film is formed by a plasma CVD method in a gas atmosphere including (1).
(2) Monosilane (SiD ₄ ) And ammonia (NH ₃ Or ND ₃ The film is formed by a plasma CVD method in a gas atmosphere including (1).
(3) Dichlorosilane (SiH ₂ Cl ₂ Or SiD ₂ Cl ₂ ) And ammonia (NH ₃ Or ND ₃ The film is formed by a low pressure CVD method in a gas atmosphere containing ()).
(4) Monosilane (SiD ₄ ) And plasma excited nitrogen (N ^* Is formed by a CVD method utilizing a plasma excitation reaction in a gas atmosphere containing
In addition, any chemical reaction other than the above may be a reaction in which hydrogen (H) is replaced with deuterium (D) in a chemical reaction by a normal CVD method.
[0018]
The second insulating layer 50 has a function of suppressing the termination material included in the first insulating layer 48 from diffusing above the second insulating layer 50. The second insulating layer 50 also has a function of preventing an element characteristic variation factor substance present above the second insulating layer 50 from reaching the vicinity of the interface of the semiconductor layer 24. Therefore, the second insulating layer 50 can be said to be a barrier layer.
The second insulating layer 50 is made of SiN, AlN, WN, Al _x O _y (Al ₂ O ₃ Etc.), TiO _x (TiO ₂ Etc.), MgO _x , ZrO _x (ZrO ₂ Etc.), Ta ₅ O ₃ , CeO ₂ , IrO _x , RuO _x , ReO _x , Al _x Si _y O _z , MgTiO _x , SrRuO ₃ Is preferably formed of at least one of the following. When the second insulating layer 50 is formed of these materials, the two functions described above can be effectively exerted.
[0019]
The second insulating layer 50 is more preferably formed of a silicon nitride film (LP-SiN) by the low pressure CVD method among the above materials. Since LP-SiN is generally formed at a high temperature of 700 to 800 ° C., the film quality is dense and the hydrogen content is very small. It is also excellent in water resistance.
The second insulating layer 50 is made of MgO from the viewpoint of high resistance or cost among the above materials. _x , Al _x O _y , ZrO _x , And SiN.
[0020]
As a material of the protective layer 56, various insulating materials such as an oxide film and a nitride film can be used. These materials may be laminated. In the case of a laminated structure, a metal, a metal oxide film, or the like may be inserted therebetween or formed at the top.
For example, the protective layer 56 is made of polyimide or a silicon oxide film (P-SiO ₂ ).
Polyimide or P-SiO ₂ Is soft, and has an advantage that stress applied to the protective layer 56 can be effectively reduced. For this reason, stress generated due to a difference in thermal expansion coefficient between the protective layer, other insulating layers, electrode layers, and semiconductor layers can be effectively reduced. This merit is particularly useful for a high-voltage power device having a large temperature difference between a high temperature and a low temperature. On the other hand, polyimide or P-SiO ₂ Is inferior in water resistance.
Further, the protective layer 56 may be formed by a silicon nitride film (P-SiN) formed by a plasma CVD method. P-SiN has the advantage of being excellent in water resistance. On the other hand, since P-SiN is formed at a low temperature, a large amount of Si-H having a small binding energy is present and contains a large amount (about 20 to 25 atomic%) of hydrogen. When the hydrogen reaches the interface of the semiconductor layer 24, an interface state is generated, which may cause a change in device characteristics.
[0021]
FIG. 3 is a cross-sectional view showing a part of the layer structure 45 and the semiconductor layer 24. When heat treatment is performed after forming the first insulating layer 48 and the second insulating layer 50 above the semiconductor layer 24, the termination material (hydrogen, deuterium, fluorine, and the like) included in the first insulating layer 46 is diffused. 3 is supplied near the interface between the semiconductor layer 24 and the lower insulating layer 46, as schematically shown by an arrow K1 in FIG. Then, dangling bonds near the interface between the semiconductor layer 24 and the lower insulating layer 46 are terminated.
In particular, when deuterium is supplied as a terminating material from the first insulating layer 46, since deuterium has twice the mass of light hydrogen, the vibration of the bonding species when electrons collide is slowed down, and Dissociation is unlikely to occur.
In particular, when fluorine is supplied as a termination material from the first insulating layer 46 and a dangling bond is terminated by a Si-F bond, the energy of the Si-H bond is 3.3 eV, whereas the energy of the Si-H bond is 3.3 eV. Since the energy of the -F bond is as high as 5.8 eV, dissociation due to hot carriers does not easily occur.
As described above, when deuterium or fluorine is supplied from the first insulating layer 46, the bond can be strengthened as compared with the case where normal hydrogen (light hydrogen) is supplied, and thus a stress voltage is applied. Even in the state, the interface state is hardly generated. For this reason, the fluctuation of the element characteristics can be suppressed more sufficiently.
[0022]
In a conventional semiconductor element, a heat treatment (sintering treatment) is performed in an atmosphere containing light hydrogen and nitrogen in order to improve the contact properties of the electrodes and terminate dangling bonds at the interface of the semiconductor layer with light hydrogen. However, in the case of the semiconductor device of the present embodiment, if the heat treatment after forming the first insulating layer 48 and the second insulating layer 50 described above is performed, the purpose of the sintering process can be achieved. Step need not be performed. Therefore, the use of the structure of the present embodiment does not increase the load of the heat treatment step. Even if sintering is performed to improve the contact properties of the electrodes, it is not necessary to include light hydrogen in the atmosphere.
[0023]
The second insulating layer 50 has a function of suppressing the termination material included in the first insulating layer 48 from diffusing above the second insulating layer 50, as schematically shown by an arrow K2 in FIG. Since the second insulating layer 50 is formed in the IGBT of this embodiment, the termination material of the first insulating layer 48 can be efficiently supplied to the vicinity of the interface of the semiconductor layer 24 when the heat treatment is performed. Therefore, dangling bonds near the interface of the semiconductor layer 24 can be efficiently terminated. Therefore, the interface state can be effectively reduced. As a result, fluctuations in element characteristics can be suppressed.
In addition, as schematically shown by an arrow K3 in FIG. 3, the second insulating layer 50 has a device characteristic variation factor present above the second insulating layer 50 near the interface of the semiconductor layer 24 (for example, the insulating layer 50). 46). Accordingly, it is possible to suppress the charge from being induced on the surface of the semiconductor layer 24 due to the vicinity of the interface of the semiconductor layer 24 (in this example, the lower portion of the insulating layer 46) of the element causing the element characteristic fluctuation. For this reason, it is possible to suppress a change in element characteristics. Here, examples of the “variable substance of element characteristics existing above the second insulating layer 50” include mobile ions, moisture, hydrogen, and impurities. More specifically, examples include mobile ions, moisture, impurities, and the like from outside the semiconductor element, and hydrogen in the protective layer 56 (see FIG. 1) constituting the semiconductor element itself.
[0024]
When such a second insulating layer 50 is provided, even if a substance (variable such as hydrogen) causing variation in element characteristics is contained in the protective layer 56 as shown in FIG. It is possible to prevent a substance causing a change in element characteristics therein from reaching the vicinity of the interface of the semiconductor layer 24. Therefore, a change in element characteristics can be suppressed. Therefore, it is possible to sufficiently form the protective layer 56 using a material containing a substance causing a change in element characteristics. Therefore, the degree of freedom in selecting the material of the protective layer 56 can be improved.
For example, even if P-SiN having a high hydrogen content is used as described above without using polyimide having a low hydrogen content as the protective layer 56, hydrogen is blocked by the second insulating layer 50. Therefore, there is basically no change in element characteristics. When polyimide is not used, contamination (dirt) due to a carbon compound attached to the electrodes 54, 58, 60 due to the polyimide can be eliminated. As a result, the effect that the reliability of the tensile strength when wire bonding is performed to the electrodes 54, 58, and 60 can be improved.
In addition, even if a silicon oxide film having low water resistance is used as the protective layer 56, the moisture is blocked by the second insulating layer 50, so that the element characteristics do not basically change.
[0025]
As in the present embodiment, when the semiconductor layer 24 has the element peripheral portion B in which the guard ring region 44 is formed, if the impurity concentration distribution or the electric field distribution of the element peripheral portion B fluctuates, the fluctuation becomes: The variation (decrease) in the breakdown voltage held in the element peripheral portion B including the guard ring region 44 is sensitively reflected. That is, even if the fluctuation amount of the impurity concentration distribution or the electric field distribution in the element peripheral portion B is small, the fluctuation amount (decrease amount) of the breakdown voltage becomes large.
On the other hand, according to the structure in which the first insulating layer 48 and the second insulating layer 50 are formed above the element peripheral portion B as in the present embodiment, dangling bonds near the interface of the element peripheral portion B can be efficiently formed. When mobile ions or the like reach the vicinity of the interface of the element peripheral portion B (the lower insulating layer 46 in this example), it is possible to suppress the induction of electric charges on the surface of the element peripheral portion B. Therefore, fluctuations in the impurity concentration distribution, electric field distribution, and the like in the peripheral portion B of the element can be sufficiently suppressed. Therefore, a very useful effect that fluctuation (decrease) of the withstand voltage can be sufficiently suppressed can be obtained.
As a result, an extra withstand voltage design margin in anticipation of fluctuations in element withstand voltage can be reduced. Accordingly, the on-resistance, which has a trade-off relationship with the withstand voltage, can be reduced by the reduction of the withstand voltage design margin. Further, the size of the element (chip) can be reduced as much as the ON resistance can be reduced, and the cost can be reduced.
[0026]
As described above, according to the IGBT of the present embodiment, fluctuations in element characteristics can be sufficiently suppressed. For example, even when the element is energized for a long time, fluctuation in element characteristics can be suppressed. Therefore, the reliability of the element can be improved. In addition, the life of the element can be extended.
[0027]
Second Embodiment FIG. 4 is a schematic cross-sectional view of an IGBT according to a second embodiment of the present invention. This schematic cross-sectional view shows an element operation section A and an element peripheral section B formed outside the element operation section A, as in the first embodiment. However, the positions of the element operation part A and the element peripheral part B are opposite to those of the first embodiment. In the following, description of the configuration, operation, and effect substantially similar to those of the first embodiment will be omitted in principle.
The difference is that the IGBT of the first embodiment is a so-called trench gate type, whereas the IGBT of the second embodiment is a so-called planar gate type. Specifically, in the IGBT of the second embodiment, a thin gate insulating film (silicon oxide film) 134 and a gate electrode 136 are sequentially stacked on the semiconductor layer 124. The IGBT has a structure in which an n-type channel is formed in a surface portion (region 138 a of p-type body region 138) of semiconductor layer 124 facing gate electrode 136 via gate insulating film 134. Region 138a of p-type body region 138 has n ⁺ Type emitter region 140 and n ⁻ This is a region sandwiched between the mold drift regions 130 and adjacent to the gate insulating film 134.
[0028]
In this IGBT, a first insulating layer 148 and a second insulating layer 150 are formed above a surface portion (region 138a of p-type body region 138) of semiconductor layer 124 where a channel is formed. In the present embodiment, the first insulating layer 148 and the second insulating layer 150 are formed on the thick field oxide film 143 at an intermediate portion between the interlayer insulating films 146 and 152. A first protective layer 156 is formed on interlayer insulating film 152 so as to cover electrodes 158 and 160. On the first protective layer 156, a second protective layer 157 is formed. The electrode 158 is connected to the guard ring region 144. The electrode (emitter electrode) 160 is n ⁺ It is connected to the type emitter region 140 and the p-type body region 138.
The first insulating layer 148 and the second insulating layer 150 may be formed of the same material as the first insulating layer 48 and the second insulating layer 50 of the first embodiment, respectively. The first protective layer 156 and the second protective layer 157 may be formed of the same material as the protective layer 56 of the first embodiment.
[0029]
When a change occurs in the impurity concentration distribution or electric field distribution in the vicinity of the channel 138a, the change is sensitively reflected by a change in a gate threshold voltage (a voltage applied to the gate electrode 136 to turn on the element). . That is, even if the fluctuation amount of the impurity concentration distribution and the electric field distribution near the channel 138a is small, the fluctuation amount of the gate threshold voltage is large.
On the other hand, according to the structure in which the first insulating layer 148 and the second insulating layer 150 are formed above the surface of the semiconductor layer 124 where the channel 138a is formed as in this embodiment, the impurity concentration near the channel 138a is increased. Fluctuations in distribution, electric field distribution, and the like can be sufficiently suppressed. Therefore, a very useful effect that fluctuation of the gate threshold voltage can be sufficiently suppressed can be obtained.
[0030]
As mentioned above, although the specific example of this invention was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above.
(1) In the above embodiment, an IGBT is described as an example of a semiconductor element. However, the present invention can be applied to a bipolar semiconductor element such as a normal bipolar transistor and a MOS type semiconductor element such as a MOSFET. .
(2) For example, the first embodiment has a structure in which the first insulating layer 48 and the second insulating layer 50 are in contact with each other, but another layer intervenes between the first insulating layer 48 and the second insulating layer 50. May be. Further, for example, in the first embodiment, the lower insulating layer 46 is interposed between the first insulating layer 48 and the semiconductor layer 24, but the first insulating layer 48 and the semiconductor layer 24 are in direct contact with each other. Is also good.
[0031]
In addition, the technical elements described in the present specification or the drawings exert technical utility singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technology exemplified in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of an insulated gate bipolar transistor (IGBT) according to a first embodiment of the present invention.
FIG. 2 is an enlarged sectional view of a portion surrounded by a dashed line C in FIG.
FIG. 3 is a cross-sectional view illustrating a layer structure and a part of a semiconductor layer.
FIG. 4 is a schematic sectional view of an insulated gate bipolar transistor (IGBT) according to a second embodiment of the present invention.
[Explanation of symbols]
24: Semiconductor layer
42, 44: guard ring area
45: Layer structure
46: Lower insulating layer
48: First insulating layer
50: Second insulating layer
52: Upper insulating layer
54, 58, 60: electrode layer
56: protective layer

Claims (8)

A semiconductor layer, a first insulating layer, and a second insulating layer,
The first insulating layer is formed above the semiconductor layer, and includes a termination material that terminates a dangling bond near an interface of the semiconductor layer,
The second insulating layer is formed above the first insulating layer, and suppresses a termination material included in the first insulating layer from diffusing above the second insulating layer, and is formed above the second insulating layer. A semiconductor element for preventing a substance causing a change in element characteristics existing in a semiconductor layer from reaching the vicinity of an interface of a semiconductor layer. A semiconductor layer, a first insulating layer, and a second insulating layer,
The first insulating layer is formed above the semiconductor layer and includes at least one of hydrogen (H), deuterium (D), and fluorine (F);
The second insulating layer is formed above the first insulating layer, the second insulating _{layer, SiN, AlN, WN, Al} x O y, TiO x, MgO x, ZrO x, Ta 5 O 3, CeO 2 , IrO _x , RuO _x , ReO _x , Al _x Si _y O _z , MgTiO _x , and a semiconductor element formed of at least one of SrRuO ₃ . The semiconductor device according to claim 1, wherein the first insulating layer includes at least one of deuterium (D) and fluorine (F). The semiconductor device according to claim 1, further comprising an insulating protective layer formed above the second insulating layer. The semiconductor device according to claim 1, further comprising an oxide insulating layer formed between the semiconductor layer and the first insulating layer. The semiconductor layer has a device peripheral portion including a guard ring region,
The semiconductor device according to claim 1, wherein a first insulating layer and a second insulating layer are formed above a peripheral portion of the device. The semiconductor device further includes a gate insulating film and a gate electrode sequentially formed on the semiconductor layer, wherein a channel is formed on a surface portion of the semiconductor layer facing the gate electrode with the gate insulating film interposed therebetween.
The semiconductor device according to claim 1, wherein a first insulating layer and a second insulating layer are formed above a surface portion of the semiconductor layer where the channel is formed. A method for manufacturing a semiconductor device according to any one of claims 1 to 7,
A method for manufacturing a semiconductor element, comprising a step of performing a heat treatment after forming a first insulating layer and a second insulating layer above a semiconductor layer.

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