JP2020021881A - Semiconductor device - Google Patents

Abstract

To provide a technique for suppressing threshold fluctuation of an insulating gate due to the movement of hydrogen included in a filling insulating film to a channel region.SOLUTION: A semiconductor device includes a semiconductor substrate, a filling insulating film that is filled in a groove in one main surface of the semiconductor substrate, and a gate electrode provided on the filling insulating film, and the semiconductor substrate includes a channel region disposed within a range of the gate electrode when viewed from a direction orthogonal to the one main surface of the semiconductor substrate, and the filling insulating film includes a buried insulating film including hydrogen, and an embedded hydrogen barrier film that is provided between the buried insulating film and the channel region, and is disposed so as to overlap the entire range of the channel region when viewed from a direction orthogonal to the one main surface of the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a semiconductor device.

  A semiconductor device driven by a high gate voltage may be required. In order to realize such a semiconductor device, a technique of employing a thick gate insulating film is known. Patent Literature 1 and Patent Literature 2 disclose a technique using an STI (Shallow Trench Isolation) structure as a thick gate insulating film.

JP 2010-165894 A JP-A-2006-058541

  Such a gate insulating film is formed by forming a groove on one main surface of a semiconductor substrate and then filling the groove with an insulating film. A CVD (Chemical Vapor Deposition) technique is used to fill the trench with an insulating film.

  The insulating film filled by using the CVD technique contains hydrogen derived from a source gas. Hydrogen contained in the insulating film moves to a channel region during a process of manufacturing a semiconductor device, and may change an interface state of the channel region. The amount of change in the interface state in the channel region greatly changes according to manufacturing variations of the semiconductor device. Since the threshold voltage of the insulating gate is affected by the interface state of the channel region, when hydrogen contained in the insulating film moves to the channel region, the threshold voltage of the insulating gate changes. There is a need for a technique for suppressing such fluctuations in the threshold voltage of the insulated gate.

One embodiment of a semiconductor device disclosed in this specification is a semiconductor substrate, a filling insulating film filling a groove in one main surface of the semiconductor substrate, and a gate provided on the filling insulating film. And an electrode. The semiconductor substrate may have a channel region disposed within a range of the gate electrode when viewed from a direction orthogonal to the one main surface of the semiconductor substrate. The filling insulating film is a buried insulating film containing hydrogen, provided between the buried insulating film and the channel region, and when viewed from a direction orthogonal to the one main surface of the semiconductor substrate, A buried hydrogen barrier film disposed so as to overlap the entire range of the channel region. Wherein the material of the semiconductor substrate silicon (Si), a compound semiconductor (SiC, GaN, etc.), an oxide semiconductor (ZnO, TiO _2, SnO _2, etc.), can be used diamond (C) or the like, a variety of materials . The filling insulating film may have an STI (Shallow Trench Isolation) structure. As the material of the buried hydrogen barrier film, a material having a sufficiently small diffusion coefficient for hydrogen is used, and a material capable of suppressing the passage of hydrogen is used. As the material of the buried hydrogen blocking film, a material having a diffusion coefficient for hydrogen smaller than that of the buried insulating film is used. The buried hydrogen barrier film may be, for example, a nitride film, typically a silicon nitride film. Instead of this example, the material of the buried hydrogen barrier film may be amorphous silicon nitride. In the semiconductor device of the above embodiment, since the buried hydrogen blocking film is provided, the movement of hydrogen contained in the buried insulating film to the channel region is suppressed. Thus, in the semiconductor device of the above embodiment, the fluctuation of the interface state of the channel region is suppressed, and the fluctuation of the threshold voltage of the insulated gate is suppressed.

  In the semiconductor device of the above embodiment, the buried hydrogen blocking film may be provided so as to cover the entire bottom surface of the buried insulating film. According to such an embodiment, the movement of hydrogen contained in the buried insulating film to the channel region is more reliably suppressed.

1 is a schematic cross-sectional view of a main part of a semiconductor device. FIG. 3 is a schematic cross-sectional view of a main part of a manufacturing process of the semiconductor device. FIG. 3 is a schematic cross-sectional view of a main part of a manufacturing process of the semiconductor device. FIG. 3 is a schematic cross-sectional view of a main part of a manufacturing process of the semiconductor device. FIG. 3 is a schematic cross-sectional view of a main part of a manufacturing process of the semiconductor device. FIG. 3 is a schematic cross-sectional view of a main part of a manufacturing process of the semiconductor device. FIG. 3 is a schematic cross-sectional view of a main part of a manufacturing process of the semiconductor device. FIG. 14 schematically shows a cross-sectional view of a principal part of a semiconductor device of a modification.

  As shown in FIG. 1, the semiconductor device 1 is a type of semiconductor device called an LDMOS (Lateral Diffusion MOSFET), and includes a semiconductor substrate 10, a drain electrode 22, a source electrode 24, a gate electrode 26, and a filling insulating film 30. , A surface hydrogen blocking film 40 and an interlayer insulating film 50.

  The semiconductor substrate 10 is a single crystal silicon and has a drain region 11, a drift region 12, a low concentration region 13, a body region 14, and a source region 15.

The drain region 11 includes an n ⁺⁺ type high concentration drain region 11a and an n type low concentration drain region 11b. The high concentration drain region 11 a is provided so as to be in contact with the side surface of the filling insulating film 30 and to be exposed on the surface of the semiconductor substrate 10. The high-concentration drain region 11a is in ohmic contact with the drain electrode 22 provided on the surface of the semiconductor substrate 10. The low-concentration drain region 11b surrounds the high-concentration drain region 11a, contacts the side surface and the bottom surface of the filling insulating film 30, and is provided between the high-concentration drain region 11a and the drift region 12.

  Drift region 12 is an n-type region having a lower impurity concentration than drain region 11 and a higher impurity concentration than low concentration region 13. Drift region 12 is provided so as to be in contact with the bottom surface of filling insulating film 30.

  The low-concentration region 13 is a remaining portion where various semiconductor regions are formed in the semiconductor substrate 10. In this example, although the low concentration region 13 is provided between the drift region 12 and the body region 14, the drift region 12 and the body region 14 may be in direct contact with each other.

  The body region 14 is a p-type region, surrounds the source region 15, and is provided so as to be in contact with the bottom surface of the filling insulating film 30. A portion of the body region 14 that contacts the bottom surface of the filling insulating film 30 is particularly called a channel region CH. The channel region CH is disposed between the drift region 12 and the source region 15, and is further disposed between the low-concentration region 13 and the source region 15 in this example. The channel region CH is included in the range of the gate electrode 26 when viewed from a direction orthogonal to the surface of the semiconductor substrate 10 (hereinafter, referred to as “when viewed in a plan view”), and at least one of the gate electrodes 26 is included. It is arranged so as to overlap the range of the part. The channel region CH is a region where an inversion channel is formed when a gate-on voltage is applied to the gate electrode 26.

The source region 15 includes an n ⁺⁺ type high concentration source region 15a and an n ⁺ type low concentration source region 15b. The high-concentration source region 15 a is provided so as to be in contact with the side surface of the filling insulating film 30 and to be exposed on the surface of the semiconductor substrate 10. The high concentration source region 15a is in ohmic contact with the source electrode 24 provided on the surface of the semiconductor substrate 10. The low-concentration source region 15b surrounds the high-concentration source region 15a, is in contact with the side and bottom surfaces of the filling insulating film 30, and is provided between the high-concentration source region 15a and the body region 14. The portion where the low-concentration source region 15b is in contact with the bottom surface of the filling insulating film 30 is arranged so as to overlap at least a part of the gate electrode 26 in plan view.

  The filling insulating film 30 is disposed between the drain electrode 22 and the source electrode 24, and is provided so as to fill a shallow trench ST formed on the surface of the semiconductor substrate 10. The filling insulating film 30 includes a thermal oxide film 32, a buried hydrogen blocking film 34, and a buried insulating film 36. The filling insulating film 30 is provided between the gate electrode 26 and the channel region CH, and functions as a gate insulating film of an insulating gate. Although not shown, the filling insulating film 30 is also provided between elements formed in other regions of the semiconductor substrate 10 and functions as an STI structure for element isolation.

  The thermal oxide film 32 covers the inner wall of the shallow trench ST, and is formed by thermally oxidizing the inner wall of the shallow trench ST. Thermal oxide film 32 is formed to reduce etching damage when forming shallow trench ST.

  The buried hydrogen barrier film 34 is provided between the thermal oxide film 32 and the buried insulating film 36. The buried hydrogen barrier film 34 is disposed so as to overlap the entire range of the channel region CH when viewed in plan. More preferably, the buried hydrogen barrier film 34 is arranged so as to overlap the entire range of the gate electrode 26 when viewed in plan. In this example, the buried hydrogen blocking film 34 is provided so as to cover the entire range of the side surface and the bottom surface of the buried insulating film 36, and is provided in the entire range between the buried insulating film 36 and the inner wall of the shallow trench ST. I have. The material of the buried hydrogen barrier film 34 is a material having a smaller diffusion coefficient for hydrogen than the buried insulating film 36, and in this example, a silicon nitride film is used. The buried hydrogen barrier film 34 is formed by using, for example, a CVD technique.

  The buried insulating film 36 is provided on the surface of the buried hydrogen barrier film 34. The buried insulating film 36 is formed by using, for example, a CVD technique.

  The surface hydrogen blocking film 40 has a first surface hydrogen blocking film 42 and a second surface hydrogen blocking film 44. The first surface hydrogen blocking film 42 is provided on the filling insulating film 30 and between the filling insulating film 30 and the gate electrode 26. The second surface hydrogen blocking film 44 is provided on the filling insulating film 30 so as to cover the surface of the gate electrode 26.

  The first surface hydrogen blocking film 42 is disposed so as to overlap the entire range of the gate electrode 26 when viewed in plan. In this example, the first surface hydrogen blocking film 42 is provided so as to cover the entire surface of the filling insulating film 30. Thus, the buried insulating film 36 is completely surrounded by the first surface hydrogen blocking film 42 and the buried hydrogen blocking film 34. The material of the first surface hydrogen blocking film 42 is a material having a smaller diffusion coefficient for hydrogen than the buried insulating film 36, and in this example, a silicon nitride film is used. The first surface hydrogen blocking film 42 is formed using, for example, a CVD technique.

  The second surface hydrogen barrier film 44 is disposed so as to overlap the entire range of the gate electrode 26 when viewed in plan. In this example, the second surface hydrogen blocking film 44 is provided so as to face and cover the entire surface of the filling insulating film 30 in addition to the surface of the gate electrode 26. The material of the second surface hydrogen blocking film 44 is a material having a smaller diffusion coefficient for hydrogen than the buried insulating film 36. In this example, a silicon nitride film is used. The second surface hydrogen blocking film 44 is formed using, for example, a CVD technique.

  The interlayer insulating film 50 covers the semiconductor substrate 10. Although not shown, wiring connected to each electrode is provided in the interlayer insulating film 50.

  The semiconductor device 1 is used with the drain electrode 22 connected to the high voltage side terminal and the source electrode 24 connected to the low voltage (for example, ground voltage) side terminal. When a voltage (ON voltage) equal to or higher than the threshold voltage is applied to the gate electrode 26 in this state, an inversion channel is formed in the channel region CH of the body region 14, and the drain electrode 22 and the source electrode 24 are connected via the inversion channel. Conduct. On the other hand, when a voltage lower than the threshold voltage (for example, a ground voltage) is applied to the gate electrode 26, the inversion channel of the channel region CH of the body region 14 disappears, and the drain electrode 22 and the source electrode 24 are insulated. Thus, the semiconductor device 1 operates as a switching element.

  The buried insulating film 36 of the filling insulating film 30 is formed using a CVD technique. Since a silane-based gas (for example, monosilane gas) is used as a source gas, hydrogen remains in the buried insulating film 36. Here, it is assumed that the embedded hydrogen barrier film 34 and the surface hydrogen barrier film 40 are not provided. In this case, the hydrogen contained in the buried insulating film 36 moves to the channel region CH of the body region 14 during the process of manufacturing the semiconductor device, and is bonded to the Si dangling bond on the surface of the channel region CH to form Si—H. It is conceivable to form a bond. Accordingly, the interface state of the channel region CH changes, and the threshold voltage of the insulating gate changes. Alternatively, it is conceivable that hydrogen contained in the buried insulating film 36 escapes from the buried insulating film 36 by outward diffusion during a process of manufacturing a semiconductor device. On the other hand, during the process of manufacturing the semiconductor device, it is conceivable that hydrogen enters the buried insulating film 36 from the outside air. Thus, the amount of hydrogen contained in the buried insulating film 36 changes, and the threshold voltage of the insulating gate changes. Such a change in the threshold voltage is sensitive to manufacturing variations and depends on manufacturing variations.

  In the semiconductor device 1, the buried hydrogen blocking film 34 is provided between the buried insulating film 36 and the channel region CH. For this reason, since the movement of hydrogen contained in the buried insulating film 36 to the channel region CH is suppressed, formation of a Si—H bond on the surface of the channel region CH is suppressed. Thereby, in the semiconductor device 1, the surface state of the channel region CH is stable against the manufacturing variation, and the fluctuation of the threshold voltage of the insulating gate is suppressed. The buried hydrogen barrier film 34 may be provided at least between the buried insulating film 36 and the channel region CH. However, if provided on the entire bottom surface of the buried insulating film 36 as in this example, The movement of hydrogen contained in the insulating film 36 to the channel region CH is reliably suppressed.

  In the semiconductor device 1, the surface hydrogen blocking film 40 is provided on the buried insulating film 36. For this reason, it is possible to suppress the hydrogen contained in the buried insulating film 36 from escaping from the buried insulating film 36 due to outward diffusion, and further, to prevent hydrogen from entering the buried insulating film 36 from outside air. As a result, in the semiconductor device 1, the amount of hydrogen contained in the buried insulating film 36 is stable against the manufacturing variation, and the fluctuation of the threshold voltage of the insulating gate is suppressed. In this example, the surface hydrogen blocking film 40 is composed of a combination of the first surface hydrogen blocking film 42 and the second surface hydrogen blocking film 44. If at least one of the first surface hydrogen blocking film 42 and the second surface hydrogen blocking film 44 is provided, hydrogen contained in the buried insulating film 36 escapes from the buried insulating film 36 by outward diffusion. Intrusion of hydrogen from the outside air into the buried insulating film 36 is suppressed. Further, since the amount of hydrogen in at least the buried insulating film 36 below the gate electrode 26 only needs to be stable, the surface hydrogen blocking film 40 is located at a position overlapping at least the entire range of the gate electrode 26 in plan view. It is sufficient if they are arranged. If the surface hydrogen blocking film 40 is provided so as to cover the entire area of the filling insulating film 30 as in this example, the amount of hydrogen in the buried insulating film 36 can be more reliably stabilized.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 2A to 2F. First, as shown in FIG. 2A, a semiconductor substrate 10 is prepared. Next, using a lithography technique, a mask (not shown) having an opening is formed on the surface of the semiconductor substrate 10, and the surface layer portion of the semiconductor substrate 10 exposed from the opening is dry-etched to form a shallow trench ST. I do.

Next, as shown in FIG. 2B, the surface of the semiconductor substrate 10 (including the inner wall of the shallow trench ST) is thermally oxidized to form a thermal oxide film 32. Next, a buried hydrogen barrier film 34 is formed on the surface of the thermal oxide film 32 by using the CVD technique. As the source gas, SiH ₄ —N ₂ , SiH ₄ —NH ₃ , and SiH ₄ —NH ₃ —N ₂ are used. Next, a buried insulating film 36 is formed on the surface of the buried hydrogen barrier film 34 by using the CVD technique. Monosilane is used as a source gas.

  Next, as shown in FIG. 2C, the embedded insulating film 36 formed on the semiconductor substrate 10 is polished to flatten the surface of the semiconductor substrate 10. In this example, the surface is flattened until the surface of the semiconductor substrate 10 is exposed. However, if necessary, the thermal oxide film 32 may remain on the surface of the semiconductor substrate 10, and the thermal oxide film 32 and the embedded hydrogen Both of the films 34 may remain.

Next, as shown in FIG. 2D, a first surface hydrogen blocking film 42 is formed on the surfaces of the semiconductor substrate 10 and the filling insulating film 30 by using the CVD technique. As the source gas, SiH ₄ —N ₂ , SiH ₄ —NH ₃ , and SiH ₄ —NH ₃ —N ₂ are used.

  Next, as shown in FIG. 2E, the gate electrode 26 is formed on the filling insulating film 30 and on a part of the surface of the first surface hydrogen blocking film 42. The gate electrode 26 is polysilicon containing impurities at a high concentration. After forming the gate electrode 26, a thermal oxidation process may be performed to form a thermal oxide film on the surface of the gate electrode 26.

Next, as shown in FIG. 2F, a second surface hydrogen barrier film 44 is formed on the surface of the gate electrode 26 and the surface of the first surface hydrogen barrier film 42 by using the CVD technique. As the source gas, SiH ₄ —N ₂ , SiH ₄ —NH ₃ , and SiH ₄ —NH ₃ —N ₂ are used.

  Finally, various semiconductor regions are formed in the semiconductor substrate 10 using the ion implantation technique, whereby the semiconductor device 1 shown in FIG. 1 is completed.

  FIG. 3 shows a semiconductor device 2 of a modified example. The semiconductor device 2 is characterized in that the first surface hydrogen blocking film 42 is not provided, as compared with the semiconductor device 1 of FIG. Also in this semiconductor device 2, since the second surface hydrogen blocking film 44 is provided on the buried insulating film 36, hydrogen contained in the buried insulating film 36 escapes from the buried insulating film 36 by outward diffusion, and Thus, the intrusion of hydrogen into the buried insulating film 36 can be suppressed. Thereby, also in the semiconductor device 2, the amount of hydrogen contained in the buried insulating film 36 is stabilized against the manufacturing variation, and the fluctuation of the threshold voltage of the insulating gate is suppressed. Also in this semiconductor device 2, since the embedded hydrogen blocking film 34 is provided, the movement of hydrogen contained in the embedded insulating film 36 to the channel region CH is suppressed. Thereby, also in the semiconductor device 2, the surface state of the channel region CH is stable against the manufacturing variation, and the fluctuation of the threshold voltage of the insulating gate is suppressed.

  As described above, the specific examples of the present invention have been described in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical utility singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.

1: semiconductor device, 10: semiconductor substrate, 11: drain region, 11a: high-concentration drain region, 11b: low-concentration drain region, 12: drift region, 13: low-concentration region, 14: body region, 15: source region, 15a: High concentration source region, 15b: Low concentration source region, 22: Drain electrode, 24: Source electrode, 26: Gate electrode, 30: Filled insulating film, 32: Thermal oxide film, 34: Embedded hydrogen barrier film, 36: Embedded insulating film, 40: surface hydrogen blocking film, 42: first surface hydrogen blocking film, 44: second surface hydrogen blocking film, 50: interlayer insulating film

Claims (5)

A semiconductor substrate;
A filling insulating film filling a groove in one main surface of the semiconductor substrate,
A gate electrode provided on the filling insulating film,
The semiconductor substrate,
And a channel region disposed within a range of the gate electrode when viewed from a direction orthogonal to the one main surface of the semiconductor substrate,
The filling insulating film,
A buried insulating film containing hydrogen,
The semiconductor device is provided between the buried insulating film and the channel region, and is disposed so as to overlap the entire range of the channel region when viewed from a direction orthogonal to the one main surface of the semiconductor substrate. And a buried hydrogen barrier film.   2. The semiconductor device according to claim 1, wherein said buried hydrogen blocking film is provided so as to cover the entire bottom surface of said buried insulating film.   3. The semiconductor device according to claim 1, wherein the buried hydrogen barrier film is a nitride film.   4. The semiconductor device according to claim 3, wherein said buried hydrogen barrier film is a silicon nitride film. The semiconductor device according to claim 1, wherein the filling insulator has an STI structure.

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