JP2004146806A5 - - Google Patents
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- JP2004146806A5 JP2004146806A5 JP2003324337A JP2003324337A JP2004146806A5 JP 2004146806 A5 JP2004146806 A5 JP 2004146806A5 JP 2003324337 A JP2003324337 A JP 2003324337A JP 2003324337 A JP2003324337 A JP 2003324337A JP 2004146806 A5 JP2004146806 A5 JP 2004146806A5
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- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- terminal
- circuit according
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Claims (9)
前記半導体集積回路は、
前記液晶表示パネル内に前記液晶駆動電圧を出力するための第１端子と、
外部装置から電源電位あるいは基準電位が供給される第２端子と、
前記半導体集積回路内の配線層によって前記第２端子と接続される第３端子と、
前記半導体集積回路の動作中に、前記電源電位あるいは前記基準電位に固定される第４端子とを有し、
前記第３端子と前記第４端子の距離は、前記第２端子と前記第４端子の距離よりも近く、
前記第４端子は、前記第４端子に印可される電圧が前記電源電位であるか前記基準電位であるかによって、前記半導体集積回路でビット数の異なる動作モードを選択するための端子であることを特徴とする半導体集積回路。 A semiconductor integrated circuit for driving and controlling a liquid crystal driving voltage output in a liquid crystal display panel,
The semiconductor integrated circuit is:
A first terminal for outputting the liquid crystal driving voltage in the liquid crystal display panel;
A second terminal to which a power supply potential or a reference potential is supplied from an external device;
A third terminal connected to the second terminal by a wiring layer in the semiconductor integrated circuit;
A fourth terminal fixed to the power supply potential or the reference potential during the operation of the semiconductor integrated circuit ;
The distance between the third terminal and the fourth terminal is closer than the distance between the second terminal and the fourth terminal,
The fourth terminal is a terminal for selecting an operation mode having a different number of bits in the semiconductor integrated circuit depending on whether a voltage applied to the fourth terminal is the power supply potential or the reference potential. A semiconductor integrated circuit.
前記第３端子と前記第４端子は隣接して配置されていることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit, wherein the third terminal and the fourth terminal are arranged adjacent to each other .
前記第４端子は複数個備えられていることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to claim 1 or 2 ,
A semiconductor integrated circuit comprising a plurality of the fourth terminals .
前記複数の第４端子の間に、前記第３端子が配置されていることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to claim 3,
The semiconductor integrated circuit , wherein the third terminal is disposed between the plurality of fourth terminals .
前記ビット数の異なる動作モードは、シリアルインターフェイスモードと、前記シリアルインターフェイスモードよりもビット数の多いバスインターフェイスモードであることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to any one of claims 1 to 4,
The semiconductor integrated circuit according to claim 1, wherein the operation modes having different bit numbers are a serial interface mode and a bus interface mode having a larger number of bits than the serial interface mode .
前記半導体集積回路が前記液晶表示パネルと接続するための基板に搭載された際に、前記第４端子は、前記基板上に形成された配線パターンを介して、前記第３端子と接続されることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to any one of claims 1 to 5,
When the semiconductor integrated circuit is mounted on a substrate for connecting to the liquid crystal display panel, the fourth terminal is connected to the third terminal via a wiring pattern formed on the substrate. A semiconductor integrated circuit.
前記第１、第２、第３および第４端子は、それぞれ第１、第２、第３および第４バンプ電極を有し、
前記第３および第４バンプ電極は、前記配線パターンに接続されることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to claim 6,
The first, second, third and fourth terminals have first, second, third and fourth bump electrodes, respectively;
The semiconductor integrated circuit, wherein the third and fourth bump electrodes are connected to the wiring pattern .
前記第１、第２、第３および第４バンプ電極は、金を含む材料で形成されていることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to claim 7,
The first, second, third, and fourth bump electrodes are formed of a material containing gold .
前記基板は、ガラス基板であることを特徴とする半導体集積回路。 The semiconductor integrated circuit according to any one of claims 6 to 8 ,
The semiconductor integrated circuit , wherein the substrate is a glass substrate .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003324337A JP4267416B2 (en) | 2003-09-17 | 2003-09-17 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003324337A JP4267416B2 (en) | 2003-09-17 | 2003-09-17 | Semiconductor integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51448498A Division JP3980066B2 (en) | 1996-09-20 | 1996-09-20 | Manufacturing method of liquid crystal display device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004146806A JP2004146806A (en) | 2004-05-20 |
| JP2004146806A5 true JP2004146806A5 (en) | 2006-12-28 |
| JP4267416B2 JP4267416B2 (en) | 2009-05-27 |
Family
ID=32463757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003324337A Expired - Lifetime JP4267416B2 (en) | 2003-09-17 | 2003-09-17 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4267416B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4810935B2 (en) * | 2005-06-30 | 2011-11-09 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP4552776B2 (en) | 2005-06-30 | 2010-09-29 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP4951902B2 (en) * | 2005-06-30 | 2012-06-13 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| US7411861B2 (en) | 2005-06-30 | 2008-08-12 | Seiko Epson Corporation | Integrated circuit device and electronic instrument |
| US7411804B2 (en) | 2005-06-30 | 2008-08-12 | Seiko Epson Corporation | Integrated circuit device and electronic instrument |
| JP4665677B2 (en) | 2005-09-09 | 2011-04-06 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP4613761B2 (en) * | 2005-09-09 | 2011-01-19 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP5022783B2 (en) | 2007-06-07 | 2012-09-12 | オンセミコンダクター・トレーディング・リミテッド | Data output circuit |
| KR101298156B1 (en) * | 2010-04-13 | 2013-08-20 | 주식회사 실리콘웍스 | Driver IC chip |
-
2003
- 2003-09-17 JP JP2003324337A patent/JP4267416B2/en not_active Expired - Lifetime
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