JP2004146669A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method capable of almost removing watermarks left on the surface after chemical and mechanical polishing. <P>SOLUTION: An insulating film is formed on the surface of a semiconductor substrate. A recess is formed on the insulating film. A metallic film is formed on the insulating film so as to embed the recess. The metallic film is chemically and mechanically polished until the surface of the insulating film is exposed. The surface exposed by the chemical and mechanical polishing process is dipped into a preprocessing solution containing amine or ammonia. After being dipped into the preprocessing solution, the surface is cleaned by an acid cleaning solution. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a step of depositing a metal film on an insulating film having a concave portion formed on the surface and chemically mechanically polishing the metal film to leave a part of the metal film in the concave portion. The present invention relates to a method for manufacturing a semiconductor device having:
[0002]
[Prior art]
In recent years, as the speed of a semiconductor integrated circuit device (LSI) increases, the delay of an electric signal propagating through a wiring connecting electronic circuits in a chip has been an obstacle to further increasing the speed of the LSI. Improving the reliability of wiring is also an important issue, and copper (Cu) has attracted attention as a wiring material replacing conventional aluminum (Al).
[0003]
When copper is used as a wiring material, a damascene method is adopted because it is difficult to etch a copper film.
Further, with the miniaturization of semiconductor integrated circuit devices, it is desired to lower the dielectric constant of insulating films disposed between layers and between wirings. Attention has been paid to SiOC as one of insulating materials having a dielectric constant lower than that of conventionally used SiO ₂ .
[0004]
With reference to FIG. 5, a description will be given of a conventional method for forming a copper wiring employing the damascene method.
As shown in FIG. 5A, a wiring groove 101 is formed in an interlayer insulating film 100 on a semiconductor substrate. The inner surface of the wiring groove 101 and the upper surface of the interlayer insulating film 100 are covered with a barrier metal layer 102. A copper seed layer is formed on the surface of the barrier metal layer 102, and copper is plated to form a copper film 103.
[0005]
As shown in FIG. 5B, the copper film 103 and the barrier metal layer 102 are chemically and mechanically polished (CMP) to remove the excess copper film 103 and the barrier metal layer 102, and the wiring 103 a is formed in the wiring groove 101. Leave. The remaining wiring 103a includes many crystal grains of copper, and a grain boundary 104 exists in the wiring 103a.
[0006]
[Patent Document 1]
JP 2001-332527 A [Patent Document 2]
Japanese Patent Application Publication No. 2001-521285 [Patent Document 3]
JP 2001-156029 A
[Problems to be solved by the invention]
When copper is formed by a damascene method using copper as the wiring material and SiOC as the material of the interlayer insulating film 100, the copper film is chemically and mechanically polished, the surface is cleaned, and then a watermark (water stain, Traces of oxidation of copper wiring, etc.) are likely to remain.
[0008]
An object of the present invention is to provide a method for manufacturing a semiconductor device in which a watermark is less likely to remain on a surface after chemical mechanical polishing.
When a copper wiring is formed by a damascene method, the copper film is chemically and mechanically polished as shown in FIG. 5B, and then the surface is cleaned and a plasma treatment using ammonia or hydrogen is performed. Reduce the surface. At this time, the substrate temperature is heated to about 100 to 200 ° C. If a corrosive substance remains on the copper surface after chemical mechanical polishing and cleaning, a grain boundary portion having a low atomic density is corroded, and grooving 105 is generated as shown in FIG. 5C.
[0009]
As shown in FIG. 5D, when the insulating film 108 is formed over the wiring 103a, the coverage of a portion where the grooving 105 has occurred is reduced, and a void 106 is generated. For this reason, the wiring resistance increases. If the cavity 106 is large, the wire may be disconnected.
[0010]
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing the occurrence of grooving and voids.
[0011]
[Means for Solving the Problems]
According to one aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a recess in the insulating film, and forming a metal film on the insulating film so as to fill the recess. And a step of subjecting the metal film to chemical mechanical polishing until the surface of the insulating film is exposed; and exposing the surface exposed in the chemical mechanical polishing step to a pretreatment liquid containing amine or ammonia. Cleaning the surface with an acidic cleaning liquid after being exposed to the pretreatment liquid.
[0012]
By exposing the substrate surface to the pretreatment liquid before performing the surface cleaning, it is possible to prevent the watermark from remaining after the cleaning.
When the metal film is formed of copper or a copper alloy and the corrosion inhibitor for copper is added to the pretreatment liquid, the corrosion inhibitor containing no sulfur as a constituent element is added to the surface of the metal film. Can be suppressed from occurring.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
1 and 2 are cross-sectional views of a semiconductor device in the course of manufacturing according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.
[0014]
As shown in FIG. 1A, an active region is defined by an element isolation insulating film 2 formed on a surface of a semiconductor substrate 1 made of silicon. On the surface of the active region, a MOS transistor 3 having a source region 3S, a drain region 3D, and a gate electrode 3G is formed.
[0015]
Via layer insulating film 4 made of phosphosilicate glass (PSG) is formed on semiconductor substrate 1 so as to cover MOS transistor 3. The via layer insulating film 4 is obtained by depositing a 1.5 μm thick PSG film by chemical vapor deposition (CVD) at a substrate temperature of 600 ° C., and then planarizing the surface by chemical mechanical polishing (CMP). is there.
[0016]
On the via layer insulating film 4, a protective film 5 made of silicon nitride and having a thickness of 50 nm is formed. A via hole 6 penetrating the protective film 5 and the via layer insulating film 4 and reaching the surface of the drain region 3D is formed. The bottom and side surfaces of the via hole 6 are covered with a barrier metal layer 7 such as TiN, and the via hole 6 is filled with a conductive plug 8 such as tungsten (W).
[0017]
A wiring layer insulating film 10 of SiOC having a thickness of about 100 to 2000 nm is formed on the protective film 5 by CVD using an organic siloxane or the like as a source gas. A wiring groove is formed in the wiring layer insulating film to reach the surface of the protective film. The upper surface of the conductive plug 8 appears on the bottom surface of the wiring groove 11.
[0018]
A barrier metal layer 14 made of TaN or Ta and having a thickness of 5 to 50 nm is formed on the inner surface of the wiring groove 11 and the upper surface of the wiring layer insulating film 10 by sputtering. A copper seed layer is formed on the surface of the barrier metal layer 14 by sputtering, and copper is electrolytically plated to form a metal film 15 made of copper or a copper alloy. The inside of the wiring groove 11 is filled with the metal film 15.
[0019]
As shown in FIG. 1B, the metal film 15 and the barrier metal layer 14 shown in FIG. 1A are chemically and mechanically polished until the wiring layer insulating film 10 is exposed. The barrier metal layer 14A remains on the inner surface of the wiring groove 11, and the copper main wiring member 15A embedded in the wiring groove 11 remains.
[0020]
After the chemical mechanical polishing, the substrate on which the surfaces of the wiring layer insulating film 10 and the main wiring member 15A are exposed is immersed in a pretreatment liquid for 50 seconds. Immersion in the pretreatment liquid is referred to as “pretreatment”. The pretreatment liquid is an aqueous solution containing benzotriazole (BTA) and tetramethylammonium hydroxide (TMAH). The concentration of BTA is 0.05% by volume and the concentration of TMAH is 0.2% by volume. BTA is a corrosion inhibitor for preventing corrosion of copper. In addition, the TMAH concentration of the pretreatment liquid may be set to 0.01 to 1.2% by volume. Further, the BTA concentration may be set to 0.001 to 1.0% by volume. Further, the ultrasonic treatment may be performed in a state where the substrate is immersed in the pretreatment liquid.
[0021]
After the pretreatment, the surface of the substrate is brush-cleaned with a cleaning liquid. The cleaning liquid is an acidic chemical containing organic acids such as oxalic acid and citric acid. After the brush cleaning, the substrate is dried with a spin rinse dryer.
[0022]
After the substrate is dried, the surface of the main wiring member 15A is reduced using ammonia plasma or hydrogen plasma. When copper oxide is formed on the surface, the copper oxide is removed by this plasma treatment.
[0023]
As shown in FIG. 2, an etching stopper film (diffusion preventing film) 20 of silicon nitride having a thickness of 50 nm and an interlayer insulating film 21 of SiOC having a thickness of about 100 to 2000 nm are formed on the wiring layer insulating film 10. They are formed in order by CVD. A well-known dual damascene method is used to form a wiring groove 22 that reaches halfway in the thickness direction of the interlayer insulating film 21 and, at a part of the bottom surface of the wiring groove 22, a via hole 23 that reaches the upper surface of the lower main wiring member 15A. I do.
[0024]
A barrier metal layer 24 made of TaN or Ta covering the bottom and side surfaces of the via hole 23 and the bottom and side surfaces of the wiring groove 22, and a main wiring member 25 embedded in the via hole 23 and the wiring groove 22 are formed. The barrier metal layer 24 and the main wiring member 25 are formed by a method similar to the method of forming the barrier metal layer 14A and the main wiring member 15A of the first wiring layer.
[0025]
Next, with reference to FIG. 3, the effect of the preprocessing of the method according to the above embodiment will be described. FIG. 3A shows a sketch of a micrograph of the surface of the substrate that has been subjected to pretreatment by the method according to the above-described embodiment and then cleaned. Line and space wiring patterns are formed in the regions 30 and 31. Since the pitches of the wirings formed in the two regions 30 and 31 are different from each other, in the micrograph, the two regions 30 and 31 are observed as a difference in shading. Therefore, the boundary between the two regions 30 and 31 is clearly identified.
[0026]
FIG. 3B shows a sketch of a micrograph of the surface of the sample whose surface has been cleaned without performing pretreatment after chemical mechanical polishing. A watermark 32 appears from the boundary between the regions 30 and 31 into the region 31. The watermark 32 shown in FIG. 3B includes a semicircular portion having a diameter of about 300 μm and a tongue-shaped portion extending inward from a portion thereof. 5000 to 10000 such watermarks were observed in an 8-inch wafer. The water mark 32 did not disappear even after further brush cleaning with dilute hydrofluoric acid.
[0027]
When pretreatment was performed between chemical mechanical polishing and surface cleaning as in the above example, no watermark was observed. It can be seen that performing the pre-processing of the above embodiment leads to prevention of generation of watermark. In the above embodiment, the immersion was performed in the pretreatment liquid for 50 seconds, but the immersion time may be about 5 to 300 seconds.
[0028]
In the above embodiment, the pretreatment was performed at room temperature, but the pretreatment may be performed by heating the pretreatment liquid to about 40 ° C. By heating the pretreatment liquid, the pretreatment time could be reduced. In the above embodiment, the substrate is immersed in the pretreatment liquid. However, the pretreatment liquid may be sprayed from a nozzle in a spray form to spray the pretreatment liquid on the surface of the substrate.
[0029]
In the above embodiment, the case where the copper wiring is buried in the interlayer insulating film made of SiOC has been described as an example. However, even when the metal wiring is buried in the interlayer insulating film made of a hydrophobic compound other than SiOC, a watermark remains. There are cases. In such a case, by inserting a pretreatment between the CMP and the surface cleaning as in the above embodiment, the remaining of the watermark can be prevented.
[0030]
For example, when SiO ₂ or SiC was used as the material of the interlayer insulating film, no watermark remained even without performing the above pretreatment. When a material having a higher hydrophobicity than SiC is used as the interlayer insulating film material, the effect of the pretreatment can be expected. For example, when an insulating material containing Si, O, and C is used, the effect of the pretreatment can be expected.
[0031]
Further, in the above embodiment, TMAH is contained in the pretreatment liquid, but a quaternary amine or ammonia other than TMAH may be contained instead of TMAH. For example, 0.2% by volume of ammonia water having a concentration of 28% may be contained. In addition, you may make it contain 0.01-1 volume%. Further, the pretreatment liquid may be heated to about 40 ° C., or may be sprayed on the substrate surface.
[0032]
When the pretreatment and the surface cleaning are performed by the method according to the above-described embodiment, and the brush cleaning is performed with dilute hydrofluoric acid before the substrate is dried, a watermark may be observed. When the pretreatment liquid is heated to 40 ° C., when the pretreatment liquid contains ammonia water instead of TMAH, when the pretreatment liquid containing ammonia is heated to 40 ° C., it is immersed in the pretreatment liquid. Alternatively, even when the pretreatment liquid was sprayed on the sample surface, the watermark was sometimes observed when the brush cleaning was performed with dilute hydrofluoric acid. This seems to be due to the slight etching of the interlayer insulating film by the diluted hydrofluoric acid. Therefore, it is preferable to wash the surface after the pretreatment with an acidic chemical solution other than hydrofluoric acid. For example, it is preferable to perform surface cleaning with an acidic chemical solution containing an organic acid such as oxalic acid or citric acid. Inorganic acids such as hydrochloric acid, sulfuric acid and nitric acid violently corrode copper, and are therefore not preferred as a surface cleaning solution.
[0033]
The effect of the embodiment has been described above by focusing on the watermark that can be generated after the substrate is washed. Next, the effect of the embodiment will be described, focusing on grooving that may occur on the surface of the copper wiring.
[0034]
As shown in FIG. 1B, after the metal film 15 made of copper is subjected to CMP to leave the main wiring member 15A in the wiring groove 11, a plurality of conditions are changed by changing the pretreatment conditions and the conditions of the reduction treatment by plasma. Were prepared, and the state of void generation in each sample was observed. As a pretreatment liquid, one containing TMAH and 2-benzothiazole thiol (2-mercaptobenzothiazole) (C ₇ H ₅ NS ₂ ) (Pretreatment liquid 1), or one containing TMAH and benzotriazole (pretreatment) Liquid 2) was used. 2-benzothiazole thiol and benzotriazole are copper corrosion inhibitors.
[0035]
After performing the pretreatment for 50 seconds, all the samples were subjected to surface cleaning using citric acid. After the surface cleaning, the substrate was dried with a spin rinse dryer, and the surface of the main wiring member 15A was subjected to a reduction treatment with NH ₄ plasma (plasma condition 1) or H ₂ plasma (plasma condition 2).
[0036]
After the reduction treatment, a 30 to 70 nm thick SiC film was formed by CVD so as to cover the entire surface of the substrate. The substrate temperature at the time of forming the SiC film was 200 to 300 ° C.
[0037]
FIG. 4 shows the results of measuring the occurrence of voids in the evaluation sample. The horizontal axis corresponds to the evaluation sample, and the vertical axis represents the void occupation area ratio in the unit “%”. In the figure, the shaded area on the lower left indicates the void occupation area ratio after the SiC film is formed, and the shaded area on the lower right indicates the void occupation area ratio after the heat treatment at 400 ° C. The void occupation area ratio was determined by observing the substrate surface with a scanning electron microscope (SEM). In the pretreatment step, many voids were observed in the sample using the pretreatment liquid 1, and almost no void was observed in the sample using the pretreatment liquid 2. Further, the sample subjected to the reduction treatment under the plasma condition 1 generated less voids than the sample subjected to the reduction treatment under the plasma condition 2, but a large difference was observed as when the pretreatment liquid was changed. Did not.
[0038]
The corrosion inhibitor added to the pretreatment liquid 1 contains sulfur as a constituent element. It is considered that after the pretreatment, sulfur remained on the copper surface, sulfuric acid and the like were generated, and the grain boundary portion of the main wiring member 15A was corroded, so that voids were generated. The corrosion inhibitor added to the pretreatment liquid 2 does not contain sulfur as a constituent element. It is considered that the generation of voids was suppressed because no residue corroding copper remained on the copper surface.
[0039]
As can be seen from the evaluation results shown in FIG. 4, in order to suppress generation of voids, it is preferable to use a corrosion inhibitor containing no sulfur as a constituent element. Examples of such a corrosion inhibitor include benzimidazole in addition to benzotriazole.
[0040]
Water marks after CMP tended to occur when the interlayer insulating film was formed of a hydrophobic insulating material. However, the frequency of grooving and void generation on the surface of the copper wiring does not depend on the material of the interlayer insulating film. Therefore, even when a material other than SiOC, for example, SiO ₂ , SiN, SiON, or SiC is used as the material of the interlayer insulating film, the occurrence of grooving and voids can be suppressed.
[0041]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0042]
From the above embodiments, the inventions described in the following supplementary notes are derived.
(Supplementary Note 1) a step of forming an insulating film on the semiconductor substrate;
Forming a recess in the insulating film;
Forming a metal film on the insulating film so as to fill the recess.
A step of chemically and mechanically polishing the metal film until the surface of the insulating film is exposed;
Exposing the surface exposed in the chemical mechanical polishing step to a pretreatment liquid containing amine or ammonia,
Cleaning the surface with an acidic cleaning liquid after being exposed to the pretreatment liquid.
[0043]
(Supplementary Note 2) After cleaning the surface of the semiconductor substrate, a diffusion prevention film for preventing diffusion of metal atoms in the metal film is formed on the insulating film and the metal film remaining in the recess. The method for manufacturing a semiconductor device according to supplementary note 1 including a step.
[0044]
(Supplementary Note 3) The method for manufacturing a semiconductor device according to Supplementary Note 1 or 2, wherein the insulating film is formed of a hydrophobic compound.
(Supplementary Note 4) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the insulating film is formed of an insulating material containing Si, O, and C.
[0045]
(Supplementary Note 5) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the insulating film is formed of SiOC.
(Supplementary Note 6) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the amine contained in the pretreatment liquid is a quaternary amine.
[0046]
(Supplementary Note 7) The method of Supplementary Note 6, wherein the quaternary amine is tetramethylammonium hydroxide.
(Supplementary Note 8) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the metal film is formed of copper or a copper alloy, and the pretreatment liquid contains a copper corrosion inhibitor.
[0047]
(Supplementary note 9) The method for manufacturing a semiconductor device according to supplementary note 8, wherein the copper corrosion inhibitor does not contain sulfur as a constituent element.
(Supplementary Note 10) The method for manufacturing a semiconductor device according to supplementary note 8, wherein the copper corrosion inhibitor is benzotriazole or benzimidazole.
[0048]
(Supplementary Note 11) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 10, wherein the semiconductor substrate is immersed in the pretreatment liquid in the step of exposing to the pretreatment liquid.
[0049]
【The invention's effect】
As described above, according to the present invention, after a metal film formed on a hydrophobic insulating film having a concave portion is subjected to chemical mechanical polishing to leave a metal member in the concave portion, and before performing surface cleaning, Pretreatment with a chemical solution containing an amine or ammonia can prevent generation of a watermark or the like.
[0050]
In addition, when a metal corrosion inhibitor is added to the pretreatment liquid, grooving can be suppressed by using a sulfur-free component.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a device in the process of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 (A) is a sketch drawing of a micrograph of the surface of a sample which has been subjected to pretreatment and surface cleaning by a method according to an embodiment of the present invention, and FIG. 3 (B) shows the surface without pretreatment. It is the figure which sketched the micrograph of the surface of the washed sample.
FIG. 4 is a graph showing a void occupation area ratio of a sample manufactured under different pretreatment conditions and plasma treatment conditions.
FIG. 5 is a cross-sectional view of a substrate for explaining a method of manufacturing a copper wiring by a conventional damascene method.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulating film 3 MOS transistor 4 via layer insulating film 5 protective film 6, 23 via hole 7, 14, 14A, 24 barrier metal layer 8 conductive plug 10 wiring layer insulating film 11, 22 wiring groove 15 metal film 15A, 25 Main wiring member 20 Etching stopper film 21 Interlayer insulating film 30, 31 Region 32 Water mark

Claims (10)

Forming an insulating film on the semiconductor substrate;
Forming a recess in the insulating film;
Forming a metal film on the insulating film so as to fill the recess.
A step of chemically and mechanically polishing the metal film until the surface of the insulating film is exposed;
Exposing the surface exposed in the chemical mechanical polishing step to a pretreatment liquid containing amine or ammonia,
Cleaning the surface with an acidic cleaning liquid after being exposed to the pretreatment liquid. After cleaning the surface of the semiconductor substrate, a step of forming a diffusion prevention film for preventing diffusion of metal atoms in the metal film on the insulating film and the metal film remaining in the recess. Item 2. A method for manufacturing a semiconductor device according to item 1. 3. The method according to claim 1, wherein the insulating film is formed of a hydrophobic compound. 4. The method according to claim 1, wherein the insulating film is formed of an insulating material containing Si, O, and C. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the amine contained in the pretreatment liquid is a quaternary amine. The method according to claim 5, wherein the quaternary amine is tetramethylammonium hydroxide. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is formed of copper or a copper alloy, and the pretreatment liquid contains a copper corrosion inhibitor. The method for manufacturing a semiconductor device according to claim 7, wherein the copper corrosion inhibitor does not contain sulfur as a constituent element. The method according to claim 7, wherein the copper corrosion inhibitor is benzotriazole or benzimidazole. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of exposing to the pretreatment liquid, the semiconductor substrate is immersed in the pretreatment liquid.

Images