JP2004146445A - Method of manufacturing connector substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a connector substrate which is applicable in manufacturing an interposer equipped with a passive device formed of high dielectric material, such as BST or the like that requires a high-temperature process. <P>SOLUTION: First of all, a capacitor 15 using BST as a dielectric material is formed on a silicon wafer 10. Then, an SiO<SB>2</SB>film 18 is formed on all the surface of the wafer 10 after a groove 10a is cut in the wafer 10. Thereafter, the groove 10a is filled with polybutane as a filling material 19a, and a resist film 20 is formed so as to protect the filling material 19a. Then, the SiO<SB>2</SB>film 18 is etched through the resist film 20 as a mask, and the SiO<SB>2</SB>film 18 is left only in the groove 10a. Thereafter, the filling material 19a inside the groove 10a is gasified by heating the wafer 10 after the resist film 20 is removed. Then, the groove 10a is filled with a conductor, and the conductor is exposed by polishing it from the backside of the wafer 10. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a connector substrate having a through hole for electrically connecting an electrode provided on one surface and an electrode provided on the other surface, and in particular, to BST (barium strontium titanate). The present invention relates to a method for manufacturing a connector substrate applicable to manufacturing an interposer including a capacitor using a high dielectric material requiring a high-temperature process such as the above.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, system LSIs in which functions such as a memory, a CPU, and a logic circuit are integrated on a single semiconductor chip have been widely used. However, system LSIs have problems in terms of cost and development period. In view of this, a system-in-package has been developed in which individually manufactured components are housed in one package to realize performance close to that of a system LSI.
[0003]
In the system-in-package, a connector board called an interposer is used. As the interposer, a ceramic substrate is usually used because of its excellent insulation and heat resistance. A component such as a semiconductor chip is joined to an electrode provided on one surface of the interposer, and an electrode provided on the other surface is joined to an electrode of a motherboard. The interposer is provided with a through hole (via) penetrating from one surface to the other surface, and the electrode on one surface and the electrode on the other surface are connected via a conductor embedded in the through hole. It is electrically connected. In addition, passive components such as a capacitor, an inductor, and a resistor that constitute a circuit for protecting a semiconductor chip and reducing noise are usually formed in the interposer.
[0004]
[Patent Document 1]
JP-A-8-335634 (FIG. 1)
[Patent Document 2]
JP-A-9-116006 (FIG. 5)
[Patent Document 3]
JP-A-2000-195555 (FIG. 3)
[Patent Document 4]
JP-A-2002-116556 (FIG. 1)
[0005]
[Problems to be solved by the invention]
By the way, in recent years, a high dielectric material such as BST has been used as a dielectric film of a capacitor. When BST is used as a dielectric film of a capacitor, it is necessary to perform heat treatment at a high temperature of about 700 to 800 ° C. after film formation.
[0006]
The ceramic substrate is usually formed by forming a through hole in a clay plate and firing it. When a BST thin film is formed on a ceramic substrate having through holes (or irregularities) in this way, cracks are likely to occur starting from around the through holes (or irregularities) at the time of heat treatment, and the manufacturing yield is reduced. Therefore, there is a demand for a method of manufacturing a connector substrate that can manufacture an interposer having a high dielectric capacitor with high yield.
[0007]
In view of the above, an object of the present invention is to provide a method of manufacturing a connector board which can be applied to manufacture of an interposer including a passive element using a high-dielectric material requiring a high-temperature process such as BST.
[0008]
[Means for Solving the Problems]
The above-described problem is caused by a first step of forming a groove on a first surface side of a flat substrate and a first step of forming a first insulating film on the first surface of the substrate and on a wall surface of the groove. Step 2, a third step of filling the groove with a filler made of a substance of which all components are gasified by heating, and a fourth step of forming a resist film for protecting the filler in the groove A fifth step of removing the first insulating film on the first surface using the resist film as a mask, a sixth step of removing the resist film, and heating the substrate to form the groove. A seventh step of removing a filler in the inside, an eighth step of filling a conductor in the groove, and shaving the substrate from a second surface side opposite to the first surface, and A ninth step of exposing the conductor, and an opening exposing the conductor portion on the second surface of the substrate. Solved by the manufacturing method of the connector substrate; and a tenth step of forming a second insulating film.
[0009]
In the present invention, first, a passive element formed of a thin film such as a high dielectric capacitor is formed on a flat substrate having no unevenness. Then, after forming a groove in this substrate, a first insulating film covering the wall surface of the groove is formed by a CVD (Chemical Vapor Deposition) method or the like. At this time, the first insulating film is necessarily formed also on the substrate.
[0010]
After that, the groove is filled with a filler, and the groove is protected with a resist film. In the present invention, as the filler, a substance such as polybutane, paraffin wax and camphor, in which all components are gasified by heating and no residual carbon or the like remains, is used.
[0011]
Next, the first insulating film on the substrate is etched using the resist film as a mask to leave the first insulating film only in the groove. Then, after removing the resist film, the filler in the groove is removed. In this case, after the filler in the groove is removed using, for example, an organic solvent, the substrate is further heated to gasify the filler remaining in the groove. As described above, in the present invention, since a substance in which all components are gasified by heating is used as the filler, the filler in the groove can be completely removed by heating the substrate.
[0012]
Thereafter, a conductor is buried in the groove, and the substrate is polished from the back side to expose the conductor. In this way, a connector board having a through hole (via) penetrating from the back side to the front side of the board and having the conductor embedded therein is completed.
[0013]
As described above, in the present invention, a passive element formed of a thin film such as a high-dielectric capacitor is formed on a flat substrate without unevenness, so that the occurrence of cracks in the thin film due to unevenness of the substrate is avoided, The production yield is improved. In particular, when a semiconductor substrate (wafer) is used as the substrate, the flatness of the surface is extremely excellent, so that the occurrence of cracks in the thin film can be more reliably avoided.
[0014]
Further, in the present invention, since there is no step of treating the substrate at a high temperature after the conductor is embedded in the groove, oxidation of the conductor in the groove is prevented. Further, in the present invention, since the conductor is filled after completely removing the filler embedded in the groove, the occurrence of insulation failure due to the residue of the filler is prevented.
[0015]
In Japanese Patent Application Laid-Open Nos. 8-335634, 9-116006 and 2000-195959, an organic material such as a novolak resin is filled in a contact hole connecting an upper wiring and a lower wiring. It is described that a shape change of a contact hole is prevented. Organic substances in the contact holes are removed by an etchant in a later step.
[0016]
Japanese Patent Application Laid-Open No. 2002-116556 discloses that a polyimide precursor film or a water-soluble organic film is formed on the surface of a semiconductor substrate having a large step to planarize the surface in order to accurately form a fine resist pattern. It is described that a photoresist film is formed thereon. The polyimide precursor film or the water-soluble organic film filled in the concave portions is removed by a photoresist film developer.
[0017]
However, each of these techniques embeds resin in a contact hole between an upper wiring and a lower wiring on a semiconductor substrate, and has a depth of several tens to several hundreds of nm. On the other hand, in the present invention, a filler is buried in a groove serving as a through hole of the interposer. Therefore, the depth of the groove is substantially equal to the thickness of the interposer, for example, 100 μm or more. As described above, in the present invention, since the groove has a large depth and a large aspect ratio, when a novolak resin or the like is used as a filler, it is difficult to completely remove the filler in the groove only by a solvent or etching. is there.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0019]
1 to 4 are sectional views showing a method of manufacturing a connector board (interposer) according to an embodiment of the present invention in the order of steps.
[0020]
First, as shown in FIG. 1A, a silicon wafer 10 having a 1 μm-thick oxide film 11 on its surface is prepared. The thickness of the silicon wafer 10 is, for example, 625 μm. Then, desired passive elements are formed on the silicon wafer 10.
[0021]
In this embodiment mode, a capacitor is formed as a passive element. In this case, Pt (platinum) is sputtered on the oxide film 11 to form a first conductive film 12 to be a lower electrode of the capacitor. Thereafter, a BST-based sol-gel is applied on the first conductive film 12 by spin coating to form a BST film, and the BST film is heat-treated at a temperature of 800 ° C. in an O ₂ atmosphere to form a dielectric film. It is assumed to be 13. Thereafter, Pt is sputtered on the dielectric film 13 to form a second conductive film 14 which will be an upper electrode of the capacitor.
[0022]
Next, as shown in FIG. 1B, the second conductive film 14, the dielectric film 13, and the first conductive film 12 are sequentially patterned into a predetermined shape to form a capacitor 15. Thereafter, an insulating film 16 made of, for example, polyimide is formed on the entire upper surface of the silicon wafer 10, and the capacitor 15 is covered with the insulating film 16. Then, contact holes communicating with the lower electrode and the upper electrode of the capacitor 15 are formed in the insulating film 16 by photolithography.
[0023]
Next, Cr (chromium) is sputtered on the entire upper surface of the silicon wafer 10, and Cu (copper) is sputtered thereon to form a seed film. Then, Cu is electrolytically plated using the seed film as a cathode to form a metal film electrically connected to the lower electrode and the upper electrode of the capacitor 15. Thereafter, the metal film is patterned by photolithography to form a wiring 17a electrically connected to the upper electrode of the capacitor 15, a wiring 17b electrically connected to the lower electrode of the capacitor 15, and other wiring 17c. .
[0024]
Next, as shown in FIG. 1C, using a mask (not shown) having a predetermined pattern, dry etching is performed for 60 minutes by an ICP (Inductively Coupled Plasma) apparatus, so that the silicon wafer 10 has a depth of Is about 150 μm and a groove 10 a having a diameter of 50 μm is formed. After that, the mask is removed.
[0025]
Next, an SiO ₂ film 18 covering the wall surface of the trench 10a is formed by a CVD method using a TEOS source. At this time, the SiO ₂ film 18 is necessarily formed on the silicon wafer 10. In this embodiment, the SiO ₂ film 18 is formed as an insulating film covering the wall surface of the groove 10a. However, an insulating film of SiO ₂ , SiN, TaN, TiN, or the like, or two or more of these insulating films are stacked. It may be formed of an insulating film.
[0026]
Next, as shown in FIG. 2 (a), by screen printing a polybutane on the SiO ₂ film 18 in a vacuum, to form a polybutane film 19 on the SiO ₂ film 18. As a result, the inside of the groove 10a is filled with polybutane as the filler 19a.
[0027]
Thereafter, as shown in FIG. 2B, the polybutane film 19 is removed by ashing by the RIE (Reactive Ion Etching) method. However, the polybutane filler 19a in the groove 10a is left without being removed.
[0028]
Next, as shown in FIG. 2C, after applying a liquid photoresist on the entire upper surface of the silicon wafer 10, exposure and development are performed to protect the polybutane filler 19a in the groove 10a. A film 20 is formed. The resist film 20 may be formed using a film-like photoresist film (dry film).
[0029]
Thereafter, the portion of the SiO ₂ film 18 that is not covered with the resist film 20 is removed by etching with buffered hydrofluoric acid. Thereby, the wirings 17a, 17b, 17c are exposed. The removal of the SiO ₂ film 18 may be performed by dry etching.
[0030]
Next, as shown in FIG. 3A, the resist film 20 on the polybutane filler 19a is removed. Then, as shown in FIG. 3 (b), the polybutane filler 19a in the groove 10a is removed by ultrasonic cleaning in hexane, and further kept at a temperature of 300 ° C. for one hour. The polybutane in the groove 10a is almost completely removed by dissolving in hexane by ultrasonic cleaning. However, even if the polybutane remains in the groove 10a, since the silicon wafer 10 is maintained at a high temperature in the present embodiment as described above, the polybutane is decomposed into a gas and can be completely removed from the groove 10a. .
[0031]
Thereafter, a Cr film (not shown) serving as a barrier metal is formed on the entire upper surface of the silicon wafer 10 by a sputtering method, and then Cu is sputtered on the Cr film to form a conductive seed film 21. Then, on the seed film 21, a resist film 22 having the trench 10a and an opening exposing the periphery thereof is formed.
[0032]
Next, as shown in FIG. 3C, Cu is electrolytically plated using the seed film 21 as a cathode. Thereby, Cu is buried in the groove 10a, and the conductor portion 23 is formed. After that, the resist film 22 is removed.
[0033]
Next, as shown in FIG. 4A, the seed film 21 is etched until the insulating film 16 is exposed, and the wirings 17a, 17b, 17c are electrically separated. In the present embodiment, as shown in FIG. 4A, the conductor portion 23 in the groove 10a and the wiring 17b are electrically connected.
[0034]
Next, the rear surface of the silicon wafer 10 is mechanically polished, and the polishing is completed at a position about 20 to 30 μm before the bottom of the groove 10a. Thereafter, as shown in FIG. 4B, the back surface side of the silicon wafer 10 is wet-etched to expose the SiO ₂ film 18 at the bottom of the groove 10a, and the SiO ₂ film 18 is plasma-etched to form the inside of the groove 10a. Is exposed. Thereafter, polyimide is printed on the back surface of the silicon wafer 10 to form a polyimide film 24 covering the back surface of the silicon wafer 10. In this case, it is important to prevent the polyimide from adhering to the conductor portion 23. Instead of forming the polyimide film by printing, an insulating sheet may be attached to the back surface of the silicon wafer 10. Thus, the interposer is completed.
[0035]
As described above, in the present embodiment, the trench 10a is formed after the capacitor 15 having the BST thin film as the dielectric film is formed on the silicon wafer 10. If the silicon wafer 10 has grooves or irregularities when forming the BST thin film, cracks occur in the BST thin film starting from the grooves or irregularities during the heat treatment, and the capacitor 15 cannot be formed. However, in the present embodiment, since the capacitor 15 is formed on the silicon wafer 10 before the formation of the groove 10a, the occurrence of a defect of the capacitor 15 is avoided. As a result, the production yield of the interposer is improved, and the product cost is reduced.
[0036]
In the present embodiment, the resist film 20 is formed after filling the trench 10a with polybutane as the filler 19a, and the SiO ₂ film 18 on the silicon wafer 10 is removed. For example, it is conceivable to fill the groove 10a with a photoresist instead of polybutane. However, since the depth of the groove 10a is large, if the photoresist is filled in the groove 10a, it is difficult to completely remove the photoresist filled in the groove 10a in a later process, and the resist residue remaining in the groove 10a It is conceivable that a connection failure may occur due to a residue of the resist stripping solution (eg, Na ₂ CO ₃ or NaOH).
[0037]
It is also conceivable to seal the groove 10a with a film-like photoresist film (dry film) without filling the groove 10a with a filler. However, in this case, since the bonding area between the photoresist film and the silicon wafer 10 is small, when the SiO ₂ film 18 is wet-etched, the photoresist film is peeled off, and the SiO ₂ film 18 in the groove is etched. Sometimes. It is conceivable to remove the SiO ₂ film 18 by dry etching in order to prevent the photoresist film from peeling off. However, in that case, since the pressure in the etching chamber is low, the pressure in the air sealed in the groove 10a is reduced. The photoresist film is torn.
[0038]
Therefore, as described in the embodiment, as the filler 19a to be filled in the groove 10a, a substance that does not remain in the groove 10a after being gasified by heat treatment, such as the above-mentioned polybutane, may be used. is necessary. Instead of polybutane, polyethylene, polypropylene, polynorbornene, paraffin wax or camphor may be used as the filler.
[0039]
Further, in the present embodiment, the back surface of the silicon wafer 10 is insulated by a polyimide film. For example, it is conceivable to thermally oxidize the back surface side of the silicon wafer 10 to form an insulating film (SiO ₂ film). However, in that case, the conductor portion 23 is oxidized by heat. It is also conceivable that stress is generated due to a difference in thermal expansion coefficient between Cu buried in the groove 10a and the silicon wafer 10, and cracks are generated in the dielectric film of the capacitor 15 formed near the groove 10a. . Therefore, as in the above embodiment, it is preferable that the insulating film on the back surface side of the silicon wafer 10 be formed by applying an insulating resin or attaching an insulating sheet.
[0040]
In the above embodiment, the case where a silicon wafer is used as a substrate has been described. However, in the present invention, a substrate other than a silicon wafer may be used. For example, an iron substrate, an aluminum substrate, a ceramic substrate, an aluminum nitride substrate, a resin substrate, or a glass substrate can be used. However, in order to form a BST film without cracks, flatness is required for the substrate. Therefore, it is preferable to use a substrate whose surface is mirror-finished.
[0041]
(Supplementary Note 1) A first step of forming a groove on the first surface side of a flat substrate, and a second step of forming a first insulating film on the first surface of the substrate and a wall surface of the groove A third step of filling the groove with a filler made of a substance whose components are gasified by heating, and a fourth step of forming a resist film for protecting the filler in the groove. A fifth step of removing the first insulating film on the first surface using the resist film as a mask; a sixth step of removing the resist film; A step of removing a filler, an eighth step of filling a conductor in the groove, and shaving the substrate from a second surface side opposite to the first surface, and A ninth step of exposing the conductor, and a second step having an opening on the second surface of the substrate where the conductor is exposed. Method for producing a connector board, characterized in that it comprises a tenth step of forming a Enmaku.
[0042]
(Supplementary note 2) The method for manufacturing a connector board according to Supplementary note 1, wherein a semiconductor substrate is used as the substrate.
[0043]
(Supplementary note 3) The method for manufacturing a connector board according to supplementary note 1, further comprising a step of forming a passive element formed of a thin film on the substrate before the first step.
[0044]
(Supplementary Note 4) The method for manufacturing a connector board according to Supplementary Note 3, wherein the passive element is a capacitor using a BST (barium strontium titanate) film as a dielectric film.
[0045]
(Supplementary note 5) The connector substrate according to Supplementary note 1, wherein any one selected from the group consisting of polybutane, polyethylene, polypropylene, polynorbornene, paraffin wax, and camphor is used as the filler. Manufacturing method.
[0046]
(Supplementary note 6) The method for manufacturing a connector board according to Supplementary note 1, further comprising a step of removing a filler in the groove with an organic solvent between the sixth step and the seventh step. .
[0047]
(Supplementary note 7) The method for manufacturing a connector board according to Supplementary note 1, wherein the first insulating film is formed of at least one selected from the group consisting of SiO ₂ , SiN, TaN, and TiN.
[0048]
(Supplementary Note 8) The method for manufacturing a connector board according to supplementary note 1, wherein in the tenth step, the second insulating film is formed of a resin.
[0049]
(Supplementary note 9) The method for manufacturing a connector board according to supplementary note 8, wherein the second insulating film is formed by printing.
[0050]
(Supplementary Note 10) The method for manufacturing a connector board according to Supplementary Note 8, wherein the second insulating film is formed by attaching a sheet-like resin.
[0051]
(Supplementary note 11) The manufacturing of the connector board according to Supplementary note 1, wherein in the ninth step, the second surface of the substrate is ground by mechanical polishing, and then the second surface of the substrate is ground by etching. Method.
[0052]
【The invention's effect】
As described above, according to the method for manufacturing a connector board of the present invention, a passive element composed of a thin film such as a high-dielectric capacitor is formed on a flat substrate without unevenness, so that a crack occurs in the thin film. Is avoided. In the present invention, a groove is formed in the substrate, an insulating film is formed on the wall surface of the groove, and then a filler is filled in the groove, and the filler is protected by a resist film. Thereby, when removing the insulating film on the substrate, the insulating film formed on the groove wall surface can be reliably protected. Furthermore, since a substance such as polybutane, in which all components are gasified by heat, is used as the filler, the filler can be completely removed from the groove, and the occurrence of poor connection due to the residue in the groove can be reduced. Can be avoided.
[0053]
Therefore, according to the present invention, the production yield of the connector board such as the interposer is improved, and the product cost is reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view (part 1) illustrating a method of manufacturing a connector board according to an embodiment of the present invention.
FIG. 2 is a sectional view (part 2) illustrating the method of manufacturing the connector board according to the embodiment of the present invention.
FIG. 3 is a cross-sectional view (part 3) illustrating the method of manufacturing the connector board according to the embodiment of the present invention.
FIG. 4 is a sectional view (part 4) illustrating the method for manufacturing the connector board according to the embodiment of the present invention.
[Explanation of symbols]
10 ... silicon wafer,
10a ... groove,
11 ... oxide film,
12: first conductive film,
13 ... dielectric film,
14 ... second conductive film,
15 ... Capacitor,
16 ... insulating film,
17a, 17b, 17c ... wiring,
18 ... SiO ₂ film,
19: Polybutane film,
19a: polybutane filler,
20, 22 ... resist film,
21 ... Seed film,
23 ... conductor part,
24 ... polyimide film.

Claims (5)

A first step of forming a groove on the first surface side of the flat substrate;
A second step of forming a first insulating film on the first surface of the substrate and on a wall surface of the groove;
A third step of filling the groove with a filler made of a substance whose components are gasified by heating;
A fourth step of forming a resist film for protecting the filler in the groove;
A fifth step of removing the first insulating film on the first surface using the resist film as a mask;
A sixth step of removing the resist film;
A seventh step of heating the substrate to remove the filler in the groove;
An eighth step of burying a conductor in the groove;
A ninth step of shaving the substrate from a second surface side opposite to the first surface to expose the conductor in the groove;
Forming a second insulating film having an opening through which the conductor portion is exposed on the second surface of the substrate. The method according to claim 1, wherein a semiconductor substrate is used as the substrate. 2. The method according to claim 1, further comprising a step of forming a passive element formed of a thin film on the substrate before the first step. 2. The method of claim 1, wherein the filler is selected from the group consisting of polybutane, polyethylene, polypropylene, polynorbornene, paraffin wax, and camphor. 3. . 2. The method according to claim 1, wherein, in the tenth step, the second insulating film is formed of a resin.

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