JP2004140223A - Transcribing and exposing method in semiconductor process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transcribing method for transcribing identical patterns under an uniform exposure condition when an exposure axis is set in the center of a mask and each of patterns of a semiconductor device containing a plurality of the identical patterns is transcribed to a wafer with focus leveling information obtained by a separate optical system. <P>SOLUTION: A first mask 2 and a second mask 3 are prepared. In the fist mask 2, the identical patterns within chip patterns 1 of the semiconductor device are arranged/formed on the mask as single representative patterns, while, in the second mask 3, the representative patterns are arranged in locations symmetrical relative to a point in relation to the mask center. When each of forming regions of the identical patterns D1 to D5 aligns adjacently on the wafer, the first and the second masks 2, 3 are used selectively so that the mask centers are located within the forming regions. The focus leveling information of the transcribing patterns can be obtained from the forming regions of the identical patterns, resulting in enabling the transcription under the uniform exposure condition. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transfer exposure method in a semiconductor process, particularly when transferring a chip of a semiconductor device including a plurality of identical patterns onto a wafer by photolithography, in order to equalize exposure conditions when transferring each pattern, In addition, the present invention relates to an improvement for increasing the number of chips.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor device applied to a CCD scanner, a liquid crystal image display device, or the like has a large number of identical patterns continuously and repeatedly arranged in a circuit configuration thereof.
In general, such a semiconductor device is a large-area chip, so that it is impossible to fit the entire chip in a single mask.
[0003]
Therefore, conventionally, when a semiconductor device as described above is manufactured by photolithography, a circuit that is repeated as the same pattern is formed on a mask as a single representative pattern. A method is adopted in which a mask is collectively disposed and formed, and a pattern is repeatedly exposed and transferred efficiently using the mask.
Various proposals have been made in the following Patent Documents 1 and 2 for a method of manufacturing a semiconductor device based on the method.
[0004]
In the above-described exposure transfer method, for example, one chip of a semiconductor device formed on a wafer is a chip pattern 1 composed of a combination of circuit patterns as shown in FIG. When B1 to B10 and C1 and C2 and D1 to D5 are the same patterns A, B, C and D, respectively, the patterns A, B, C and D are collectively arranged as shown in FIG. Use one formed mask 2.
In FIG. 13B, reference numeral 20 denotes the center of the mask 2.
[0005]
As an exposure apparatus, an apparatus of a reduction projection exposure system as shown in FIG. 14 is often used, and in this case, the mask 2 is a reticle mask.
In the figure, reference numeral 31 denotes an exposure light source, and light emitted from the exposure light source irradiates the mask 2 via a fly-an lens 32, an aperture 33, a condenser lens 34, a mirror 35, and a condenser lens 36.
The optical axis 10 of the exposure light beam emitted from the mirror 35 to the mask 2 through the condenser lens 36 is set so as to pass through the center 20 of the mask 2 fixed to the installation table.
A blind 37 is provided on the upper side of the mask 2, and a region other than the pattern to be transferred among the patterns A, B, C, and D of the mask 2 is shielded by the blind driving unit 38. ing.
[0006]
The light transmitted through the pattern of the mask 2 that is open to the blind 37 is condensed on the wafer 41 placed on the upper surface of the leveling stage 40 via the projection lens 39, whereby the pattern of the mask 2 is Is projected and transferred.
The leveling stage 40 is mounted on a Z stage 42, and the Z stage 42 is mounted on an XY stage 43.
A two-system optical system composed of LEDs 44 and 45, collimating lenses 46 and 47, condensing lenses 48 and 49, and photodetectors 50 and 51 is used to refer to the intersection of the wafer 41 and the optical axis 10, respectively. Leveling information and focus information relating to a certain area on 41 are obtained, and the information detected by the photodetectors 50 and 51 is input to a main control unit 52, and the main control unit 52 performs the processing based on the information. By controlling the leveling drive unit 53 and the Z drive unit 54, the tilt angle of the wafer 41 and the position in the optical axis direction (focus position) are adjusted so that proper transfer exposure is always performed.
[0007]
In addition, the main control unit 52 performs operations created based on the arrangement conditions of the patterns A, B, C, and D of the chip pattern 1 and the mask 2 of the semiconductor device, and the arrangement conditions of the chip pattern 1 on the wafer 41. The program is set in advance.
Then, the main control unit 52 reads the program and controls the XY drive unit 55 to move the XY stage 43 in the horizontal direction, control the shielding state of the blind 37, and perform the leveling / focusing. While controlling the leveling stage 40 and the Z stage 42 based on the information, each of the patterns A, B, C, and D of the mask 2 is selectively transferred to the set position of the wafer 41, and finally a large number of chip patterns are formed on the wafer 41. 1 is formed.
[0008]
[Patent Document 1]
JP-A-06-323389
[Patent Document 2]
JP 2000-323389 A
[0009]
[Problems to be solved by the invention]
By the way, in the above-described exposure apparatus, the mask 2 is installed so that its center 20 is located on the optical axis 10 of the exposure light beam, and the patterns A, B, and B of the mask 2 shown in FIG. According to the arrangement conditions of C and D, the optical axis 10 of the light beam for exposure passes through the pattern C of the mask 2, but the other patterns A, B, and D are always at positions shifted from the optical axis 10.
On the other hand, in the above-described exposure apparatus, leveling / focus information is obtained based on the intersection between the optical axis 10 of the exposure light beam and the wafer 41.
[0010]
Therefore, when transferring the patterns A, B, and D onto the wafer 41, leveling is performed based on leveling / focus information obtained from an area on the wafer 41 shifted from an area where the patterns A, B, and D are to be transferred. The stage 40 and the Z stage 42 are adjusted and controlled.
In that case, it is still better if leveling focus information is obtained from an area where the same pattern as the pattern to be transferred is to be formed, but if the information is obtained from an area where a different pattern is to be formed, A plurality of identical patterns repeatedly transferred are transferred under different exposure conditions.
[0011]
For example, as shown in FIG. 15, when the pattern D of the mask 2 is transferred to the pattern D1 in the chip pattern 1, the optical axis 10 becomes a position passing through the pattern C1 in the chip pattern 1, and The focus information is obtained from the pattern C1 side, and the pattern D1 is transferred onto the wafer 41 in a state where the tilt angle of the wafer 41 and the position in the optical axis direction are adjusted based on the information.
On the other hand, at the stage where the XY stage 43 is moved and the patterns D2 to D5 in the chip pattern 1 are sequentially transferred, the optical axis 10 sequentially shifts to the patterns D1 to D4, so that the same pattern is formed. The transfer is performed while obtaining the leveling / focus information in the area to be transferred.
Then, only the pattern D1 of the chip pattern 1 has been transferred based on the leveling / focus information of the different pattern C1, and when the pattern D is such as to constitute a pixel circuit, the pixels of the pattern D1 The seam between the pixels of the pattern D2 is different from the seam between the pixels of the other patterns D2 to D5, which causes a problem that the display quality of an image is reduced.
[0012]
As another problem, assuming that the chip pattern 1 disposed near the edge of the wafer 41 is transferred by each of the patterns A, B, C, and D of the mask 2, FIG. As described above, the area in the chip pattern 1 where the pattern A4 is to be formed is closest to the edge 41a of the wafer 41. In this case, the optical axis 10 is located outside the wafer 41. Leveling focus information cannot be obtained.
Therefore, if the transfer is performed as it is, a short circuit of the pattern due to defocusing occurs, and such a transfer may be impossible depending on the exposure apparatus. As a result, the chip pattern 1 is formed in a region near the edge 41a. It becomes impossible to do so, which leads to a decrease in the number of chips obtained.
[0013]
In view of the above, the present invention provides a mask used when transferring a plurality of semiconductor device chips including the same pattern onto a wafer, so that exposure and transfer can rationally solve the above-described problems. It was created to provide a method.
[0014]
[Means for Solving the Problems]
According to a first aspect, an optical axis of an exposure light beam is set to pass through the center of a mask, and based on focus / leveling information obtained by a separate optical system with reference to an intersection point between the optical axis and the wafer. A semiconductor device including a plurality of different patterns each using an exposure apparatus that transfers each pattern of the semiconductor device formed on the mask onto the wafer while controlling the position and angle of the wafer in the optical axis direction; A transfer exposure method for transferring a chip onto a wafer, wherein a first mask in which a plurality of identical patterns for different patterns in the semiconductor device are respectively arranged and formed on a mask as a single representative pattern; and A second mask in which the arrangement area of each of the representative patterns is set at a point-symmetric position with respect to the center of the mask in relation to one mask When the formation regions of the same pattern of the semiconductor device to be formed on the wafer are aligned adjacently, the center of the mask is formed on the wafer when viewed from the optical axis direction. The present invention relates to a transfer exposure method in a semiconductor process, wherein transfer is performed by selectively using the first mask or the second mask so as to be located in the same pattern formation region of the semiconductor device to be formed.
[0015]
According to the present invention, when the formation regions of the same pattern of the semiconductor device to be formed on the wafer are arranged adjacent to each other, the first mask or the first mask is used when these patterns are repeatedly transferred. By selectively using two masks, focus / leveling information can always be obtained from an area where the same pattern is to be formed, and adjacent same patterns can be transferred under more uniform exposure conditions.
Therefore, in the case where the same pattern is related to pixels, it is possible to prevent such a problem that a joint between consecutive pixels is conspicuous.
[0016]
The second invention is a transfer exposure method for transferring a plurality of semiconductor device chips including the same pattern onto a wafer by using the same exposure apparatus as the first invention, and is similar to the first invention. A first mask and a second mask having the following relationship are prepared. When the plurality of the same patterns are repeatedly transferred onto the wafer, the optical axis of the first mask and the second mask is set within the first mask and the second mask. When viewed from the direction, the transfer is performed by selectively using a mask in which the distance between the center of the mask and the center of the chip pattern disposition region of the semiconductor device to be formed on the wafer is shorter. And a transfer exposure method in a semiconductor process.
[0017]
According to the present invention, when a plurality of identical patterns in a semiconductor device are transferred and exposed on a wafer by using a representative pattern of a mask, the first mask and the second mask are selectively used so that the focus leveling information can be obtained from the semiconductor device as much as possible. It becomes possible to obtain the same pattern from an area close to the center of the arrangement area, and it becomes possible to transfer the same pattern under more uniform exposure conditions.
[0018]
A third invention is a transfer exposure method for transferring a semiconductor device chip including a plurality of identical patterns onto a wafer by using the same exposure apparatus as the first invention, wherein the transfer exposure method is to be formed on the wafer. When a formation region of the same pattern of the semiconductor device is near the edge of the wafer, a representative pattern relating to the pattern is arranged and formed near the corners of the first mask and the second mask, The present invention relates to a transfer exposure method in a semiconductor process, wherein transfer is performed by selectively using the first mask or the second mask so that the center of the mask is located within the wafer.
[0019]
According to the present invention, by selectively using the first mask and the second mask, it is possible to obtain focus / leveling information on a pattern in a region near the edge of the wafer as compared with the case where transfer is performed using a single mask. Since transfer can be performed in many cases, more chip patterns of normal semiconductor devices can be formed in a region near the edge of the wafer, and the number of chips that can be removed from the wafer can be increased.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the “transfer exposure method in a semiconductor process” of the present invention will be described in detail with reference to FIGS.
However, also in this embodiment, a case where a large number of the chip patterns 1 shown in FIG. 13A are transferred onto the wafer 41 using the exposure apparatus shown in FIG. 14 will be described as an example.
First, FIGS. 1A and 1B are plan views of two masks used in this embodiment, and the mask of FIG. 1A corresponds to the mask 2 of FIG. 13B described in the related art. , (B), the arrangement area of the patterns A, B, C, and D is set at a point-symmetric position with respect to the center 20 of the mask 2 in relation to the mask 2 described above.
[0021]
Now, assuming that patterns D1 to D5 in the chip pattern 1 in FIG. 13A are transferred using the masks 2 and 3, when the mask 2 is used for transferring the pattern D1, FIG. As described above, when the wafer 41 is moved so that the pattern D of the mask 2 corresponds to the pattern D1 of the chip pattern 1, the optical axis 10 is located in the area of the pattern C1 of the chip pattern 1, and the area of the pattern C1 Only the leveling focus information based on the information was obtained.
[0022]
In order to solve this problem, in this embodiment, two masks 2 and 3 created based on the symmetry condition are prepared, and the mask 3 is applied when transferring the pattern D1.
FIG. 2 shows the optical positional relationship between the chip pattern 1 and the mask 2 in the exposure apparatus in this case. When the pattern D of the mask 2 corresponds to the pattern D1 of the chip pattern 1, the center 20 of the mask 2 (that is, the exposure Since the position of the optical axis 10 of the device is located in the area where the pattern D2 of the chip pattern 1 is formed, the leveling / focus information is obtained from the area where the same pattern is to be formed.
[0023]
Next, in this embodiment, the mask 3 is also applied when the pattern D2 of the chip pattern 1 is transferred.
The optical positional relationship between the chip pattern 1 and the mask 2 in that case is shown in FIG. 3. When the pattern D of the mask 2 is made to correspond to the pattern D2 of the chip pattern 1, the optical axis 10 of the exposure apparatus becomes the pattern of the chip pattern 1. It is located in the formation area of D3, and the leveling / focus information is also obtained from the area where the same pattern is to be formed.
[0024]
On the other hand, when transferring the patterns D3 to D5 of the chip pattern 1, the mask 2 is applied.
The optical positional relationship between the chip pattern 1 and the mask 2 in those cases is shown in FIGS. 4 to 6, and the optical axis 10 of the exposure apparatus is different in each case in the area where the patterns D2, D3, and D4 of the chip pattern 1 are formed. As described above, the leveling / focus information is obtained from the area where the same pattern is to be formed.
Here, if it is assumed that the mask 2 is applied at the time of transferring the pattern D5 of the chip pattern 1, the position of the optical axis 10 in that case is the pattern C2 of the chip pattern 1, which is a symmetrical relationship with the case of FIG. As a result, leveling / focus information is obtained from the area of the pattern C2 different from the patterns D1 to D5.
[0025]
Therefore, according to this embodiment, by using the two masks 2 and 3 selectively, the same patterns D1 to D5 in the chip pattern 1 can be leveled by setting a reference in the formation area of those patterns. A case in which the patterns D1 to D5 can be transferred based on the focus information, and the patterns D1 to D5 are transfer patterns under uniform exposure conditions, so that the patterns D1 to D5 are repetitive patterns of circuits constituting pixels. In this case, it is possible to prevent such a problem that a joint of pixels becomes conspicuous.
[0026]
In transferring the patterns D2, D3, and D4 of the chip pattern 1, the optical axis 10 can be positioned in the same pattern formation region using any of the masks 2 and 3, as shown in FIG. The pattern D2 is transferred by the pattern D of the mask 3, and the patterns D3 and D4 are transferred by the pattern D of the mask 2. The optical axis 10 is set as close to the center of the chip pattern 1 as possible. This is due to the considerations.
[0027]
Next, a case where the patterns B1 to B10 in the chip pattern 1 are transferred using the masks 2 and 3 will be described.
Generally, in a semiconductor process, a chip pattern of a semiconductor device is transferred to a wafer while being arranged in a matrix.
Regarding the above-mentioned chip pattern 1, as shown in FIG. 7, the chip pattern 1 is repeated in a vertically and horizontally close manner.
In this case, as shown in the figure, regarding the conditions when transferring the pattern B1 of the chip pattern 1 using the pattern B of the mask 2, the position of the optical axis 10 corresponding to the center 20 of the mask 2 is adjacent to the upper side. In the area where the pattern B7 of the chip pattern 1 is formed, the leveling / focus information is obtained from the same pattern formation area of the adjacent chip pattern 1.
Although the transfer of the pattern B1 is illustrated in FIG. 7, the patterns B1 to B10 can be selectively used as appropriate from the same pattern formation region in the adjacent chip pattern 1 by selectively using the mask 2 or the mask 3 to obtain leveling / focus information. While transferring.
[0028]
In this embodiment, since the pattern B on the masks 2 and 3 has the arrangement condition as shown in FIGS. 1A and 1B, the exposure condition based on the leveling / focus information as described above is obtained. However, such a condition is not always obtained depending on the configuration of the chip pattern, and the leveling / focus information obtained above is information based on the same pattern formation region of the adjacent chip pattern. This is not information obtained from the same pattern relating to the chip pattern 1 to be actually transferred.
[0029]
On the other hand, in the case where the patterns B1 to B10 are not circuits constituting pixels, it is often the case that it is better to make the exposure conditions uniform within the chip pattern 1 to be actually transferred.
Therefore, in this embodiment, when selecting the two masks 2 and 3, the center of the chip pattern 1 including the respective patterns B1 to B10 currently to be transferred and the center 20 of the mask 2 or the mask 3 (the position of the optical axis 10). A description will be given of a case where a method of selecting and transferring a mask having a shorter distance from the direction of the optical axis 10 is adopted.
[0030]
First, FIG. 8A shows a case where the pattern B1 of the chip pattern 1 is transferred using the pattern B of the mask 2, and FIG. 8B shows a case where the pattern B1 of the mask 3 is transferred using the pattern B of the mask 3.
In each case, a comparison of the linear distances L1 and L2 between the center 20 of the masks 2 and 3 and the center 25 of the chip pattern 1 shows that L1 <L2.
Therefore, in transferring the pattern B1 in this case, the mask 2 is selected, and the pattern B1 of the chip pattern 1 is transferred using the pattern B of the mask 2.
[0031]
On the other hand, FIGS. 9 and 10 show the case where the patterns B2 and B5 of the chip pattern 1 are transferred based on the same reference.
In the transfer of the patterns B2 to B5 of the chip pattern 1, the straight line distance between the center 20 of the masks 2 and 3 and the center 25 of the chip pattern 1 is shorter when the mask 3 is used than when the mask 2 is used. Therefore, the mask 3 is applied.
Although the transfer of the patterns B6 to B10 is not shown, one of the masks 2 and 3 is selected and the pattern B is transferred according to the above-mentioned standard.
[0032]
As described above, the method of selecting the mask in which the linear distance between the center 20 of the masks 2 and 3 and the center 25 of the chip pattern 1 as viewed from the direction of the optical axis 10 is shorter is related to the transfer of the patterns B1 to B10. Leveling / focus information can be obtained as information based on a position as close as possible to the center 25 of the chip pattern 1 including those patterns B1 to B10, and transferred while setting a more uniform exposure condition for each chip pattern. You can do it.
[0033]
Next, a case where the patterns A1 to A4 of the chip pattern 1 are transferred will be described.
The patterns A1 to A4 are dispersedly arranged at the corners of the chip pattern 1, and have different conditions from the patterns D1 to D5 and the patterns B1 to B10.
The problem with the patterns A1 to A4 is that, when the chip patterns 1 are arranged in a matrix on the wafer 41 as described with reference to FIG. 16, a chip to be formed near the edge 41a of the wafer 41 The patterns A1 to A4 of the pattern 1 are extremely close to the edge 41a, so that leveling / focus information cannot be obtained and a pattern short-circuit or the like due to defocus occurs, resulting in a decrease in the number of chips to be obtained.
[0034]
Regarding this problem, in this embodiment, as shown in FIG. 1, two masks 2, 3 in which the formation areas of the patterns A, B, C, D are arranged in a point-symmetric relationship with respect to the center 20 of the mask. Is prepared, and the pattern A is arranged and formed near the corner of each of the masks 2 and 3, so that it can be rationally solved by appropriately selecting the masks 2 and 3.
That is, in FIG. 16, since the mask 2 is used, the center 20 (the position of the optical axis 10) of the mask 2 is shifted to the center of the wafer 41 when transferring the pattern A4 of the chip pattern 1 near the edge 41 a of the wafer 41. Although it was out of the range and the leveling / focus information could not be obtained, if the pattern A4 was transferred using the mask 3 as shown in FIG. Can be transferred by obtaining leveling / focus information.
[0035]
Further, as shown in FIG. 12, the pattern A1 of the chip pattern 1 which is diagonally positioned on the wafer 41 with respect to the chip pattern 1 in FIG. As described above, the position of the optical axis 10 is within the range of the wafer 41, and the transfer can be performed in a state where the leveling / focus information is obtained.
Although FIGS. 11 and 12 have described the chip patterns 1 disposed at the lower right and upper left corners of the wafer 41, respectively, the patterns A2 and A3 of the chip patterns 1 disposed at the upper right and lower left corners are described. Although the optical axis 10 slightly approaches the edge 41a, the optical axis 10 can be kept within the range of the wafer 41 by using any of the masks 2 and 3, and the transfer can be performed while obtaining the leveling / focus information.
[0036]
Finally, when examining the transfer of the patterns C1 and C2 of the chip pattern 1, the pattern C is arranged at the center in the masks 2 and 3, and the center 20 of the masks 2 and 3 is in the pattern C.
Therefore, the optical axis 10 is located in the formation area of the patterns C1 and C2 regardless of which of the masks 2 and 3 is used, and is directly transferred based on the leveling / focus information obtained based on the center of the formation area. Therefore, in this case, the problems related to the other patterns D1 to D5, B1 to B10, and A1 to A4 do not occur.
[0037]
As described above, according to the transfer exposure method of this embodiment, each problem of the related art can be rationally solved. However, as the exposure method of the exposure apparatus, a reduced projection exposure method as shown in FIG. The invention is not limited thereto, and may be a mirror projection system of 1: 1 transfer, or a projection exposure system of directly transferring a pattern without interposing an optical system between the mask and the wafer.
[0038]
【The invention's effect】
The “transfer exposure method in a semiconductor process” of the present invention has the following effects due to the above configuration.
According to the first aspect of the present invention, the formation areas of the same pattern of the semiconductor device to be formed on the wafer are arranged adjacent to each other, and when these patterns are repeatedly transferred, the focus / leveling information is always stored. The same pattern can be transferred while being acquired from a region where the same pattern is to be formed, so that the same pattern can be transferred under uniform exposure conditions.
In particular, it is optimal when the same pattern is related to a pixel circuit, and has an advantage that a problem that a joint of continuous pixels is conspicuous can be prevented.
According to the second aspect of the present invention, the focus leveling information can be obtained from an area as close to the center of the arrangement area of the semiconductor device as possible, so that the same pattern included in the chip pattern for each semiconductor device can be obtained. It enables transfer under uniform exposure conditions.
The invention according to claim 3 enables focus / leveling information to be obtained from the wafer surface even for a pattern formed near the edge of the wafer. It enables proper transfer of chip patterns and increases the number of chips that can be obtained.
[Brief description of the drawings]
FIG. 1 is a plan view of two masks used in an embodiment of a “transfer exposure method in a semiconductor process” of the present invention.
FIG. 2 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern D1 in the chip pattern is transferred using the mask of FIG.
FIG. 3 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern D2 in the chip pattern is transferred using the mask of FIG.
FIG. 4 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern D3 in the chip pattern is transferred using the mask of FIG.
FIG. 5 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern D4 in the chip pattern is transferred using the mask of FIG.
FIG. 6 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern D5 in the chip pattern is transferred using the mask of FIG.
FIG. 7 is a diagram showing the mutual relationship between chip patterns arranged in a matrix on a wafer, and the mask and optical characteristics of each chip pattern when a pattern B1 in the chip pattern is transferred using the mask of FIG. It is a top view which shows a positional relationship.
8A illustrates a case where a pattern B1 in a chip pattern is transferred using the mask of FIG. 1A, and FIG. 8B illustrates a case where the pattern B1 in the chip pattern is transferred using the mask of FIG. FIG. 4 is a plan view showing the optical positional relationship between a mask and a chip pattern in each case when transferring.
FIG. 9 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern B2 in the chip pattern is transferred using the mask of FIG.
FIG. 10 is a plan view illustrating an optical positional relationship between the mask and the chip pattern when a pattern B5 in the chip pattern is transferred using the mask of FIG.
FIG. 11 is a diagram showing the relationship between the mask, the chip pattern, and the edge of the wafer when the pattern A4 (the pattern closest to the edge of the wafer) in the chip pattern disposed at the lower right corner of the wafer is transferred using the mask of FIG. It is a top view which shows an optical positional relationship.
FIG. 12 shows a pattern A1 (a pattern closest to the edge of the wafer) in a chip pattern disposed at the upper left corner of the wafer transferred by the mask shown in FIG. It is a top view which shows an optical positional relationship.
13A is a plan view of a chip pattern, and FIG. 13B is a diagram showing the same patterns A1 to A4, B1 to B10, C1 and C2, D1 to D5 in the chip pattern as representative patterns A, B, It is a top view of the mask arrange | positioned and formed in one mask as C and D.
FIG. 14 is a system configuration diagram of an exposure apparatus.
FIG. 15 is a plan view showing an optical positional relationship between the mask and the chip pattern when a pattern D1 in the chip pattern of FIG. 13A is transferred using the mask of FIG. 13B.
FIG. 16 shows the optical positional relationship between the mask and the chip pattern when pattern A1 (the pattern closest to the edge of the wafer) in the chip pattern provided at the lower right corner of the wafer is transferred using the mask of FIG. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Chip pattern, 2, 3 ... Mask, 10 ... Optical axis, 20 ... Center of mask, 25 ... Center of chip pattern, 31 ... Exposure light source, 32 ... Fly-an lens, 33 ... Aperture, 34, 36 condenser lens, 35 mirror, 37 blind, 38 blind drive, 39 projection lens, 40 leveling stage, 41 wafer, 41a wafer edge, 42 Z stage, 43 XY stage, 44 45 LED, 46, 47: Collimating lens, 48, 49: Condensing lens, 50, 51: Photodetector, 52: Main control unit, 53: Leveling drive unit, 54: Z drive unit, 55: XY drive unit , A, B, C, D... Patterns (representative patterns) arranged and formed on the mask, A1 to A4, B1 to B10, C1 and C2, D1 to D5. Same pattern, L1, L2 ... distance of the center of the mask when viewed in the optical axis direction (the position of the optical axis) with the center of the chip patterns.

Claims (3)

The optical axis of the exposure light beam is set so as to pass through the center of the mask, and the optical axis of the wafer is determined by a separate optical system based on focus / leveling information obtained with reference to the intersection between the optical axis and the wafer. While controlling the position and angle of the direction, using an exposure apparatus that transfers each pattern of the semiconductor device formed on the mask to the wafer, a semiconductor device chip including a plurality of different patterns is placed on the wafer. In the transfer exposure method when transferring,
A first mask in which a plurality of identical patterns for different patterns in the semiconductor device are arranged and formed on a mask as a single representative pattern, respectively;
In relation to the first mask, a second mask in which the arrangement area of each of the representative patterns is set at a point-symmetric position with respect to the center of the mask is prepared.
When the respective formation regions of the same pattern of the semiconductor device to be formed on the wafer are aligned adjacently, the semiconductor device to be formed on the wafer with the center of the mask viewed from the optical axis direction A transfer exposure method in a semiconductor process, wherein the transfer is performed by selectively using the first mask or the second mask so as to be located within the same pattern formation region. The optical axis of the exposure light beam is set so as to pass through the center of the mask, and the optical axis of the wafer is determined by a separate optical system based on focus / leveling information obtained with reference to the intersection between the optical axis and the wafer. While controlling the position and angle of the direction, using an exposure apparatus that transfers each pattern of the semiconductor device formed on the mask to the wafer, a semiconductor device chip including a plurality of different patterns is placed on the wafer. In the transfer exposure method when transferring,
A first mask in which a plurality of identical patterns for different patterns in the semiconductor device are arranged and formed on a mask as a single representative pattern, respectively;
In relation to the first mask, a second mask in which the arrangement area of each of the representative patterns is set at a point-symmetric position with respect to the center of the mask is prepared.
When the plurality of identical patterns are repeatedly transferred onto the wafer, the first mask and the second mask should be formed on the center of the mask and the wafer when viewed from the optical axis direction. A transfer exposure method in a semiconductor process, wherein transfer is performed by selectively using a mask having a shorter distance from the center of a chip pattern disposition region of the semiconductor device. The optical axis of the exposure light beam is set so as to pass through the center of the mask, and the optical axis of the wafer is determined by a separate optical system based on focus / leveling information obtained with reference to the intersection between the optical axis and the wafer. While controlling the position and angle of the direction, using an exposure apparatus that transfers each pattern of the semiconductor device formed on the mask to the wafer, a semiconductor device chip including a plurality of different patterns is placed on the wafer. In the transfer exposure method when transferring,
A first mask in which a plurality of identical patterns for different patterns in the semiconductor device are arranged and formed on a mask as a single representative pattern, respectively;
In relation to the first mask, a second mask in which the arrangement area of each of the representative patterns is set at a point-symmetric position with respect to the center of the mask is prepared.
When a formation region of the same pattern of the semiconductor device to be formed on the wafer is near an edge of the wafer, a representative pattern related to the pattern is arranged near a corner of the first mask and the second mask. Forming the first mask or the second mask selectively so that the center of the mask is located within the wafer when viewed from the optical axis direction, among the first mask and the second mask; A transfer exposure method in a semiconductor process, wherein the transfer is performed by using the method.

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