JP2004135188A - Optical receiving circuit and electronic apparatus having the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a substrate space and the costs and to achieve further power saving until an optical signal is actually received after an operating state is instructed in the case of realizing shutdown control for power saving in digital equipment having an optical receiving circuit. <P>SOLUTION: The optical receiving circuit is provided with a signal detection means 15 which detects reception of the optical signal in a photodiode PD and a control means 16 which performs the shutdown control on the basis of a shutdown signal to be inputted from the outside via a terminal P14 and output of the signal detection means 15. The control means 16 performs control for switching a state from a shutdown state to the operating state when the signal detection means 15 detects the reception of the optical signal in the photodiode PD when the shutdown signal is the one which instructs the operating state. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical receiver circuit used for an optical fiber link that converts an electric signal into an optical signal and transmits the optical signal, and an electronic apparatus including the same.
[0002]
[Prior art]
The optical fiber link converts a signal such as an audio signal or a video signal into one optical signal by converting an electric signal into an optical signal on a transmitting side and transmitting the signal, and converting a received optical signal into an electric signal on a receiving side. Easy high-speed transmission over fiber. In recent years, with the spread of digital devices, optical fiber links have become widespread even in ordinary households.
[0003]
For example, an optical fiber link is used for signal transmission from a DVD (digital video disc) player, a digital broadcast STB (set top box) and a CD (compact disc) player to an MD (mini disc) player, an amplifier, and the like. . Recently, transmission of music signals to personal portable devices such as personal computers using optical fiber links has also become widespread. Furthermore, the optical fiber link is also used for signal transmission in a place where electrical insulation is required.
[0004]
On the other hand, in digital devices, especially in portable devices, reduction of power consumption which affects battery operation time is always required. For this reason, the configuration as shown in FIG. 6 is conventionally used in the optical communication circuit. That is, in the configuration shown in FIG. 6, a regulator IC 102 having a shutdown function is interposed between a power supply (not shown) and the optical communication circuit 101. The regulator IC 102 responds to a shutdown signal input to the shutdown input terminal P111 to output a power supply voltage Vcc input from the power supply to the power input terminal P112 from the power output terminal P113 to the optical communication circuit 101. Control.
[0005]
Thus, when the operation of the optical communication circuit 101 is unnecessary, a shutdown signal is input to the shutdown input terminal P111 to shut down the output of the regulator IC 102, thereby realizing low power consumption.
[0006]
There is no prior art document relating to the above-mentioned prior art related to the invention known in the literature.
[0007]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, the provision of the dedicated regulator IC occupies a space on the circuit board, and there is a problem in that a digital device having an optical communication circuit is disadvantageous in terms of miniaturization or cost.
[0008]
The present invention has been made to solve the above problems, and an object of the present invention is to reduce board space and cost in implementing shutdown control for power saving in a digital device having an optical receiving circuit. It is an object of the present invention to provide an optical receiving circuit capable of performing the above-described operations and an electronic apparatus including the same.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, an optical receiving circuit according to the present invention includes, in an optical receiving circuit provided with a converting unit that converts an optical signal into an electric signal, a shutdown unit that shuts off power supply to an internal circuit; Signal detection means for detecting reception of an optical signal in the means, and control means for controlling the shutdown means based on a shutdown signal input from outside and an output of the signal detection means, wherein the control means Controlling the switching of the shutdown unit from the shutdown state to the operation state when the signal detection unit detects the reception of the optical signal by the conversion unit when the shutdown signal indicates the operation state of the shutdown unit; It is characterized by performing.
[0010]
According to the above configuration, even if a shutdown signal instructing the operation state of the shutdown unit is input, until the signal detection unit detects the reception of the optical signal by the conversion unit, that is, the light from the partner device is detected. Until the signal is input, the control means controls the shutdown means to maintain the shutdown state.
[0011]
Thereby, even after the shutdown signal indicates the operation state of the shutdown means, the optical receiving circuit does not shift to the operation state until the optical signal is actually input from the partner device, and the optical receiver circuit does not receive the signal from the partner device. It is possible to suppress a bias current or the like in an internal circuit while there is no input of an optical signal, and to further reduce power consumption.
[0012]
In the light receiving circuit, the conversion unit is a photodiode, and the signal detection unit detects an open voltage of the photodiode when the photodiode receives an optical signal in a shutdown state, and outputs a detection signal. It can be configured to output.
[0013]
According to the above configuration, since the open-circuit voltage of the photodiode is detected, it is not necessary to separately prepare a photodiode for detecting a signal, which is advantageous for downsizing the circuit.
[0014]
Further, in the above-mentioned optical receiving circuit, the above-mentioned signal detecting means may be configured to include a MOS transistor and a resistor.
[0015]
According to the above configuration, the use of a MOS transistor and a resistor for the signal detection means makes it possible to easily configure the circuit with a simple configuration.
[0016]
Further, in the optical receiving circuit, the control unit includes an AND circuit that receives the shutdown signal and the output of the signal detection unit, and a latch circuit that holds an output of the AND circuit. Can be.
[0017]
Further, in the above-described optical receiving circuit, the optical receiving circuit may be configured to be configured on a monolithic integrated circuit.
[0018]
According to the above configuration, in the electronic device provided with the optical receiving circuit, it is advantageous for miniaturization and space saving.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0020]
The present inventors have filed Japanese Patent Application No. 2002-17626 as an optical communication circuit that can reduce board space and cost when implementing shutdown control for power saving. First, the configuration of the optical communication circuit in Japanese Patent Application No. 2002-17626 will be described with reference to FIGS.
[0021]
FIG. 2 is a block diagram showing an electrical configuration of the optical receiving circuit 11 in Japanese Patent Application No. 2002-17626. The light receiving circuit 11 is monolithically formed on one chip including the photodiode PD. The light receiving circuit 11 generally includes a photodiode PD, a dummy capacitor CD, first-stage amplifiers A11 and A12, differential amplifiers A2 and A3, a comparator CMP, a buffer B, an output circuit 12, and a bias circuit. 13 and a shutdown circuit 14.
[0022]
The photodiode PD is biased by the corresponding first-stage amplifier A11 and outputs a current corresponding to the received optical signal. The current output from the photodiode PD is converted into a voltage by the resistor R11 of the first-stage amplifier A11, and is output from the first-stage amplifier A11 with low impedance.
[0023]
The dummy capacitance CD is formed to be equal to the parasitic capacitance of the photodiode PD. The current flowing through the dummy capacitor CD is converted into a voltage by the first-stage amplifier A12 and the resistor R12 having the same configuration as the first-stage amplifier A11, and is output with low impedance.
[0024]
Outputs from the first-stage amplifiers A11 and A12 are supplied to respective inputs of a differential amplifier A2 that is AC-coupled by coupling capacitors C1 and C2. Further, a reference voltage Vref is applied to each input of the differential amplifier A2 via pull-up resistors R21 and R22.
[0025]
Therefore, each input of the differential amplifier A2 has a value in which the AC components of the outputs from the first-stage amplifiers A11 and A12 are superimposed around the reference voltage Vref. The differential amplifier A2 amplifies the difference between those inputs and outputs the result as a differential voltage signal. Here, noise from the GND potential via the photodiode PD that appears in the output from the first-stage amplifier A11 also appears in the same phase in the output from the first-stage amplifier A12. Therefore, a signal from which the noise has been removed is output from the differential amplifier A2.
[0026]
The output from the differential amplifier A2 is further amplified by the differential amplifier A3, and the output differential voltage signals are compared with each other by the comparator CMP to be shaped into a differential rectangular signal. The differential output from the comparator CMP is made a single output in the buffer B and input to the output circuit 12.
[0027]
The output circuit 12 is a push-pull amplifier of a CMOS configuration using a power supply voltage Vcc input to a power input terminal P11 and a GND potential applied to a ground terminal P12 as power sources and including a PMOS transistor QP and an NMOS transistor QN. The output from the output circuit 12 inverts the output from the buffer B and becomes either the power supply voltage Vcc or the GND potential. Further, the output from the output circuit 12 becomes the output Vout at the output terminal P13.
[0028]
Power is supplied from the bias circuit 13 to the first-stage amplifiers A11 and A12, the differential amplifiers A2 and A3, the comparator CMP, and the buffer B. The power supply from the bias circuit 13 is controlled by the shutdown circuit 14. The shutdown circuit 14 controls power supply from the bias circuit 13 in response to a shutdown signal externally input to the shutdown input terminal P14.
[0029]
FIG. 3 is a block diagram showing a specific configuration of the bias circuit 13 and the shutdown circuit 14 in the optical receiving circuit 11 configured as described above. Parts corresponding to FIG. 2 are denoted by the same reference numerals. Shown.
[0030]
The bias circuit 13 includes transistors Q10 to Q12 for controlling voltage supply to the first-stage amplifiers A11 and A12, and transistors Q1 to Q5 for controlling voltage supply to the differential amplifiers A2 and A3, the comparator CMP and the buffer B. It is configured.
[0031]
The PMOS transistors Q11 and Q12 control whether to supply the power supply voltage Vcc to the first-stage amplifiers A11 and A12, respectively. The PMOS transistor Q10 controls ON / OFF of the PMOS transistors Q11 and Q12 in common. The NMOS transistors Q2, Q3, Q4, and Q5 control whether or not to supply power by connecting the differential amplifiers A2 and A3, the comparator CMP, and the buffer B to the GND potential, respectively. The NMOS transistor Q1 controls ON / OFF of the NMOS transistors Q2 to Q5 in common.
The drains of the PMOS transistors Q11 and Q12 are respectively connected to the high-level power supply inputs of the first-stage amplifiers A11 and A12, the sources are commonly supplied with the power supply voltage Vcc, and the gates are commonly connected to the drain of the PMOS transistor Q10. You. The source of the PMOS transistor Q10 is supplied with the power supply voltage Vcc, and the gate thereof is supplied with the output of the preceding inverter INV1 of the two-stage inverters INV1 and INV2 constituting the shutdown circuit 14.
[0032]
A low-level bias Pbias is applied to the drain of the PMOS transistor Q10, that is, the gates of the PMOS transistors Q11 and Q12, via a not-shown pull-down resistor or the like. Both low-level power inputs of the first-stage amplifiers A11 and A12 are connected to the GND potential (not shown).
[0033]
The drains of the NMOS transistors Q2, Q3, Q4, and Q5 are respectively connected to the differential amplifiers A2 and A3, the comparator CMP, and the low-level power supply input of the buffer B, the sources are commonly connected to the GND potential, and the gates are commonly used. Connected to the drain of NMOS transistor Q1. The source of the NMOS transistor Q1 is connected to the GND potential, and the gate thereof is supplied with the output of the inverter INV2 at the subsequent stage of the shutdown circuit 14.
[0034]
A high-level bias Nbias is applied to the drain of the NMOS transistor Q1, that is, the gates of the NMOS transistors Q2, Q3, Q4, and Q5 via a pull-up resistor (not shown). A power supply voltage Vcc is applied to the high-level power supply inputs of the differential amplifiers A2 and A3, the comparator CMP, and the buffer B (not shown).
[0035]
Therefore, while the shutdown signal input to the shutdown input terminal P14 is at the low level, the output of the inverter INV1 is at the high level, the output of the inverter INV2 is at the low level, and both the PMOS transistor Q10 and the NMOS transistor Q1 are turned off. .
[0036]
When the PMOS transistor Q10 is turned off, the gates of the PMOS transistors Q11 and Q12 are biased to a low level, the PMOS transistors Q11 and Q12 are turned on, and a desired constant current is supplied to the first-stage amplifiers A11 and A12.
[0037]
Similarly, when the NMOS transistor Q1 turns off, the gates of the NMOS transistors Q2 to Q5 are biased to a high level, the NMOS transistors Q2 to Q5 turn on, and the differential amplifiers A2 and A3, the comparator CMP and the buffer B Is supplied.
[0038]
On the other hand, when the shutdown signal goes high, the output of the inverter INV1 goes low and the output of the inverter INV2 goes high, turning on both the PMOS transistor Q10 and the NMOS transistor Q1.
[0039]
When the PMOS transistor Q10 is turned on, the gates of the PMOS transistors Q11 and Q12 go high, the PMOS transistors Q11 and Q12 are turned off, and a desired constant current is not supplied to the first-stage amplifiers A11 and A12.
[0040]
Similarly, when the NMOS transistor Q1 is turned on, the gates of the NMOS transistors Q2 to Q5 are biased to a low level, the NMOS transistors Q2 to Q5 are turned off, and a desired signal is supplied to the differential amplifiers A2 and A3, the comparator CMP and the buffer B. No constant current is supplied.
[0041]
Thus, when the operation of the optical receiving circuit 11 is unnecessary, the shutdown signal is set to the high level, whereby the bias circuit 13 is shut down, whereby the bias current supplied to each internal circuit can be shut down. Thus, power consumption of the optical receiving circuit 11 can be reduced.
[0042]
However, in the optical receiving circuit 11 having the above-described configuration, the state in which the bias current flows inside the circuit continues while the shutdown signal is at the low level and the photodiode PD does not receive the optical signal. This will be described with reference to FIG. In FIG. 4, the first-stage amplifier A11 is provided as a transistor, and the shutdown means 13a is obtained by extracting a portion related to the voltage control of the first-stage amplifier A11.
[0043]
In FIG. 4, the gate of the PMOS transistor Q11 is biased by the Pbias voltage, and when the PMOS transistor Q10 is OFF, a desired bias current is supplied from the PMOS transistor Q11 to the transistor A11 as the first-stage amplifier (operation state). . When the PMOS transistor Q10 is ON, no current is supplied from the PMOS transistor Q11 to the transistor A11 (shutdown state).
[0044]
In the shutdown state, a high-level signal is input to the shutdown input terminal P14. At this time, the output of the inverter INV1 is at a low level, and the PMOS transistor Q10 is turned on. As a result, the PMOS transistor Q11 is turned off, no bias current is supplied to the transistor A11, and a shutdown state is realized.
[0045]
In the operation state, a low level signal is input to the shutdown input terminal P14. At this time, the output of the inverter INV1 is at the high level, and the PMOS transistor Q10 is turned off. As a result, the PMOS transistor Q11 turns ON, a desired bias current is supplied to the transistor A11, and the transistor A11 enters an operating state.
In the electronic device including the light receiving circuit 11, when the light receiving circuit 11 is changed from the shutdown state to the operating state (a state in which a signal from a partner device is received), a low-level signal is input to the shutdown input terminal P14. Is done. Until an optical signal is input from an external device connected to the electronic device including the optical receiving circuit 11 by a fiber cable, a bias current is generated inside the optical receiving circuit 11 in the electronic device in the operating state. It will be kept in the flowing state.
[0046]
For this reason, if no signal is output from the partner device connected to the electronic device, or if the fiber cable is not properly connected between these devices, a bias current flows inside the optical receiving circuit 11. The states are continuous, and wasteful power is consumed during that time.
[0047]
The present invention is characterized in that in a light receiving circuit having a shutdown function, power consumption due to a bias current in an operating state is suppressed, and further power saving is achieved. This feature will be described with reference to FIGS. 1 and 5, parts corresponding to the configurations shown in FIGS. 2 to 4 are denoted by the same reference numerals.
[0048]
FIG. 5 is a block diagram schematically showing a mechanism for supplying a bias current to the photodiode PD. FIG. 5 shows a configuration in which a signal detection unit 15 and a control unit 16 are added to the configuration of FIG. 4 described above.
[0049]
The signal detection unit 15 is connected to the cathode and the anode of the photodiode PD, and detects that an optical signal has been input from a partner device. The control unit 16 controls the shutdown unit 13a based on the output of the signal detection unit 15 and the input from the shutdown input terminal P14.
[0050]
That is, in the configuration of FIG. 4, the shutdown unit 13a switches between the shutdown state and the operation state by the shutdown signal from the shutdown input terminal P14. However, in the configuration of FIG. 5, the shutdown unit 13a performs the shutdown signal from the shutdown input terminal P14. In addition, the switching of the shutdown unit 13a is controlled by the output of the signal detection unit 15 as well.
[0051]
Specifically, the control unit 16 does not switch the shutdown unit 13a from the shutdown state to the operation state only when the shutdown signal from the shutdown input terminal P14 switches from the high level to the low level. When the reception of the signal is detected, the shutdown unit 13a is switched from the shutdown state to the operation state. As a result, the shutdown state of the shutdown unit 13a can be maintained until an optical signal is input from the partner device, and further power saving can be achieved.
[0052]
Further, a specific configuration of the optical receiving circuit including the signal detecting unit 15, the control unit 16, and the shutdown unit 13a will be described with reference to FIG. In the optical receiving circuit 1 of FIG. 1, the same components as those of the optical receiving circuit 11 of FIG. 3 are denoted by the same reference numerals, and the detailed description thereof will be omitted.
[0053]
The signal detecting means 15 includes an NMOS transistor Q31 and a resistor R31, and the control means 16 includes an inverter INV3, an AND circuit 16a, and a latch circuit 16b. Further, the PMOS means Q10 and Q11 in the bias circuit 13 correspond to the shutdown means 13a in FIG.
Hereinafter, the circuit operation in FIG. 1 will be described.
[0054]
In the signal detecting means 15, the gate of the NMOS transistor Q31 is connected to the anode of the photodiode PD, and the source is connected to the cathode of the photodiode PD.
[0055]
When an optical signal is input to the photodiode PD in a state where the bias current Ibias from the PMOS transistor Q11 in the shutdown unit 13a is not flowing, an open voltage is generated in the cathode voltage of the photodiode PD. Its voltage is on the order of -0.5 volts.
[0056]
At this time, a forward voltage is applied between the gate and the source of the NMOS transistor Q31, whereby the NMOS transistor Q31 is turned on, and the output of the signal detection means 15 indicated by a point A in FIG.
[0057]
When the electronic device including the optical receiving circuit 1 in FIG. 1 attempts to return from the shutdown state to the operation state and a low-level shutdown signal is input to the shutdown input terminal P14, the shutdown signal is inverted to a high level by the inverter INV1. You. The shutdown signal inverted by the inverter INV1 is input to the gate of the PMOS transistor Q10 via the AND circuit 16a and the latch circuit 16b of the control unit 16.
[0058]
However, even when a low-level shutdown signal is input to the shutdown input terminal P14, the output of the signal detection unit 15 maintains a high level until an optical signal is input from the partner device. During this time, the output of the inverter INV3 is at the low level, and the output of the AND circuit 16a is kept at the low level. Therefore, the PMOS transistor Q10 in the shutdown means 13a is kept on, the PMOS transistor Q11 is kept off, and the light receiving circuit 1 is The shutdown state will be maintained.
[0059]
Here, when an optical signal is input from the partner device, as described above, the NMOS transistor Q31 of the signal detection unit 15 is turned on, and the output (point A) of the signal detection unit 15 becomes low level. Accordingly, the output of the inverter INV3 goes high, and if a high-level shutdown signal is input to the other terminal of the AND circuit 16a, the output of the AND circuit 16a goes high.
[0060]
As a result, the PMOS transistor Q10 in the shutdown means 13a is turned off and the transistor Q11 is turned on, a bias current flows through the transistor A11 which is the first-stage amplifier, and the light receiving circuit 1 is activated.
[0061]
The latch circuit 16b in the control means 16 changes the output of the signal detection means 15 from the low level to the high level after the output of the signal detection means 15 changes from the high level to the low level and the output of the AND circuit 16a changes to the high level. This is necessary to prevent the shutdown means 13a from again entering the shutdown state.
[0062]
Further, by configuring the optical receiving circuit 1 having the above-described configuration in a monolithic integrated circuit, it is advantageous for downsizing and space saving in an electronic device including the optical receiving circuit 1.
[0063]
Further, in the optical communication circuit according to the present embodiment, by using MOS transistors for the configuration of the shutdown means, the signal detection means, and the control means, only the circuit composed of bipolar transistors when driven by a low power supply voltage can be used. Therefore, operation at a lower power supply voltage becomes possible.
[0064]
【The invention's effect】
As described above, the light receiving circuit of the present invention includes a shutdown unit that shuts off power supply to an internal circuit, a signal detection unit that detects reception of an optical signal in the conversion unit, and a shutdown signal that is input from the outside. Control means for controlling the shutdown means based on the output of the signal detection means, wherein the control means outputs the signal when the shutdown signal indicates an operation state of the shutdown means. When the detecting means detects the reception of the optical signal by the converting means, control is performed to switch the shutdown means from the shutdown state to the operating state.
[0065]
Therefore, even if a shutdown signal instructing the operation state of the shutdown unit is input, the shutdown state is maintained by the control unit until the signal detection unit detects the reception of the optical signal by the conversion unit. As a result, even after the shutdown signal indicates the operation state of the shutdown unit, the bias current and the like in the internal circuit can be suppressed while no optical signal is input from the partner device, and further power saving can be achieved. This has the effect of realizing the effect.
[0066]
In the light receiving circuit, the conversion unit is a photodiode, and the signal detection unit detects an open voltage of the photodiode when the photodiode receives an optical signal in a shutdown state, and outputs a detection signal. It can be configured to output.
[0067]
Therefore, since the open-circuit voltage of the photodiode is detected, it is not necessary to separately prepare a photodiode for detecting a signal, which is advantageous in reducing the size of the circuit.
[0068]
Further, in the above-mentioned optical receiving circuit, the above-mentioned signal detecting means may be configured to include a MOS transistor and a resistor.
[0069]
Therefore, the use of a MOS transistor and a resistor for the signal detection means has an effect that the circuit can be easily configured with a simple configuration.
[0070]
Further, in the optical receiving circuit, the control unit includes an AND circuit that receives the shutdown signal and the output of the signal detection unit, and a latch circuit that holds an output of the AND circuit. Can be.
[0071]
Further, in the above-described optical receiving circuit, the optical receiving circuit may be configured to be configured on a monolithic integrated circuit.
[0072]
Therefore, in the electronic device provided with the light receiving circuit, there is an effect that it is advantageous for miniaturization and space saving.
[Brief description of the drawings]
FIG. 1 illustrates one embodiment of the present invention, and is a circuit diagram illustrating an electrical configuration of an optical receiving circuit.
FIG. 2 is a circuit block diagram showing an electrical configuration of an optical receiving circuit in Japanese Patent Application No. 2002-17626, which is a prior application of the present invention.
FIG. 3 is a circuit diagram showing an electrical configuration of an optical receiving circuit in Japanese Patent Application No. 2002-17626.
FIG. 4 is a circuit diagram showing a specific configuration in the vicinity of a first-stage amplifier section of an optical receiving circuit in Japanese Patent Application No. 2002-17626.
FIG. 5 is a circuit block diagram illustrating a schematic configuration in the vicinity of a first-stage amplifier section of the optical receiving circuit according to the present invention.
FIG. 6 is a block diagram illustrating a configuration of a conventional optical receiving device.
[Explanation of symbols]
1 Optical receiving circuit
13 Bias circuit
13a Shutdown means
15 Signal detection means
16 control means
16a AND circuit
16b latch circuit
PD photodiode (conversion means)
Q31 NMOS transistor (MOS transistor in signal detection means)
R31 resistance (resistance in signal detection means)

Claims (6)

In an optical receiving circuit including a conversion unit that converts an optical signal into an electric signal,
Shutdown means for cutting off power supply to the internal circuit;
Signal detection means for detecting reception of the optical signal in the conversion means,
Control means for controlling the shutdown means based on an externally input shutdown signal and an output of the signal detection means,
The control means, when the shutdown signal indicates the operation state of the shutdown means, when the signal detection means detects the reception of the optical signal in the conversion means, the control means changes the shutdown means from the shutdown state to the operation state. An optical receiving circuit for performing control for switching to the optical receiving circuit. The conversion means is a photodiode,
2. The light receiving circuit according to claim 1, wherein the signal detecting means detects an open circuit voltage of the photodiode and outputs a detection signal when the photodiode receives an optical signal in a shutdown state. 3. The optical receiving circuit according to claim 2, wherein said signal detecting means comprises a MOS transistor and a resistor. 2. The optical receiver according to claim 1, wherein the control unit includes an AND circuit that receives the shutdown signal and an output of the signal detection unit as inputs, and a latch circuit that holds an output of the AND circuit. circuit. 5. The optical receiving circuit according to claim 1, wherein the optical receiving circuit is configured on a monolithic integrated circuit. An electronic apparatus comprising the optical receiving circuit according to claim 1.

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