JP3805688B2 - Optical communication circuit chip and electronic device including the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical communication circuit chip used for an optical fiber link that converts an electrical signal into an optical signal and transmits the optical signal, and an electronic device including the optical communication circuit chip.
[0002]
[Prior art]
The optical fiber link converts an electrical signal into an optical signal on the transmitting side and transmits the optical signal, and the receiving side reconverts the received optical signal into an electrical signal, so that a multi-channel signal such as an audio signal or a video signal can be obtained. Since high-speed transmission can be easily performed with a single optical fiber, in recent years, with the spread of digital equipment equipped with the optical communication circuit chip, it has become widespread in general households. For example, signal transmission from a DVD (digital video disc) player, a digital broadcast STB (set top box) and a CD (compact disc) player to an MD (mini disc) player, an amplifier, or the like. Recently, transmission of music signals to personal portable devices such as personal computers has also become widespread. Furthermore, the optical fiber link is also used for signal transmission at a place where electrical insulation is required.
[0003]
On the other hand, in the digital devices, especially portable devices, reduction of power consumption that affects battery operating time is always required. For this reason, the configuration shown in FIG. 19 is conventionally used for the optical communication circuit. That is, a regulator IC 2 having a shutdown function is interposed between a power supply (not shown) and the optical communication circuit 1, and the regulator IC 2 is connected to the power supply (not shown) in response to a shutdown signal input to the shutdown input terminal P1. It controls whether or not the power supply voltage Vcc input to the power input terminal P2 is output from the power output terminal P3 to the optical communication circuit 1.
[0004]
As a result, when the operation of the optical communication circuit 1 is unnecessary, the output of the regulator IC 2 is shut down by inputting a shutdown signal to the shutdown input terminal P1, thereby realizing low power consumption.
[0005]
[Problems to be solved by the invention]
However, when the dedicated regulator IC 2 is provided, it occupies the space of the circuit board, which is disadvantageous for downsizing and disadvantageous in terms of cost.
[0006]
An object of the present invention is to provide an optical communication circuit chip capable of reducing board space and cost and an electronic device including the same in realizing shutdown control for power saving.
[0007]
[Means for Solving the Problems]
The optical communication circuit chip of the present invention is an optical communication circuit chip that converts an electrical signal into an optical signal for communication. A shutdown input terminal, an internal circuit, and a shutdown circuit, wherein the shutdown circuit includes: From outside To the shutdown input terminal of the optical communication circuit chip In response to the input shutdown signal, Said A shutdown circuit is provided to cut off the power supply to the internal circuit. The bias circuit that supplies power to the internal circuit includes a first MOS transistor that supplies a constant current to each internal circuit, and the shutdown circuit includes the plurality of first MOS transistors. A second MOS transistor is provided which is divided according to polarity and controls each of them together. The second MOS transistor controls the gate of the first MOS transistor, and the shutdown circuit responds to the shutdown signal. And a control circuit for driving the second MOS transistor. It is characterized by that.
[0008]
According to the above configuration, the light receiving element and the signal processing circuit that performs processing such as amplification and waveform shaping of the signal received by the light receiving element, or the light emitting element and the drive circuit that amplifies the transmission signal and applies the signal to the light emitting element are provided. In response to a shutdown signal input from an external control circuit, etc., depending on whether a plug of a transmission medium such as an optical fiber is attached to the corresponding jack or a user operation, etc. The shutdown circuit controls whether to supply power to the internal circuits such as the light receiving element and the signal processing circuit.
[0009]
Therefore, when realizing the shutdown control for power saving, by incorporating the shutdown circuit in the optical communication circuit chip, it is possible to reduce the board space and cost as compared with the case where a separate regulator IC is used. .
[0010]
In the optical communication circuit chip of the present invention, the bias circuit that supplies power to the internal circuit includes a first MOS transistor that supplies a constant current to each internal circuit, and the shutdown circuit includes: The second MOS transistor for controlling the gate of the first MOS transistor and a control circuit for driving the second MOS transistor in response to the shutdown signal.
[0011]
According to the above configuration, the bias circuit that supplies power to the internal circuits such as the light receiving element and the signal processing circuit normally has a diode structure, and the first current that supplies a constant current to each internal circuit. The MOS transistors are divided by polarity or the like, and one or a plurality of the first MOS transistors are collectively driven by the second MOS transistor.
[0012]
Therefore, when the first and second transistors are configured as bipolar transistors, it is necessary to supply a base current to the transistor that is turned on at the time of shutdown. Unnecessary current does not flow and power consumption can be further reduced.
[0013]
Furthermore, the optical communication circuit chip of the present invention is characterized in that the circuit of the output stage is composed of a MOS transistor.
[0014]
According to the above configuration, when the circuit of the output stage is configured with a bipolar transistor, the output signal response is made with an open collector type in order to increase the amplitude range of the output signal, with an external pull-up resistor. In order to increase the load current, it is necessary to reduce the value of the pull-up resistor. For this reason, the load current flowing through the pull-up resistor increases. Therefore, a sufficient response speed can be achieved with low power consumption.
[0015]
An electronic apparatus according to the present invention includes any one of the above-described optical communication circuit chips.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0017]
FIG. 1 is a block diagram showing an electrical configuration of an optical receiver circuit 11 which is an optical communication circuit chip according to an embodiment of the present invention. The optical receiving circuit 11 is monolithically formed on one chip including the photodiode PD. The optical receiver circuit 11 generally includes the photodiode PD, a dummy capacitor CD, first-stage amplifiers A11 and A12, differential amplifiers A2 and A3, a comparator CMP, a buffer B, an output circuit 12, A bias circuit 13 and a shutdown circuit 14 are provided.
[0018]
The photodiode PD is biased by the corresponding first-stage amplifier A11, and the current corresponding to the optical signal received from the photodiode PD is converted into a voltage by the resistor R11 of the first-stage amplifier A11. Is output. The dummy capacitor CD is formed to be equal to the parasitic capacitance of the photodiode PD, and the current flowing through the dummy capacitor CD is converted into a voltage by the first-stage amplifier A12 and the resistor R12 having the same configuration as the first-stage amplifier A11. Output with impedance.
[0019]
Outputs from the first stage amplifiers A11 and A12 are given to respective inputs of the differential amplifier A2 that is AC-coupled by the coupling capacitors C1 and C2. A reference voltage Vref is applied to each input of the differential amplifier A2 via pull-up resistors R21 and R22. Accordingly, each input of the differential amplifier A2 has a value in which the AC component of the output from the first stage amplifiers A11 and A12 is superimposed with the reference voltage Vref as the center, and the differential amplifier A2 And a differential voltage signal is output. Here, the noise from the GND potential via the photodiode PD that appears in the output from the first-stage amplifier A11 also appears in the same phase in the output from the first-stage amplifier A12. Therefore, the signal from which the noise has been removed is output from the differential amplifier A2. Is output.
[0020]
The output from the differential amplifier A2 is further amplified by the differential amplifier A3, and the differential voltage signal of the output is compared with each other by the comparator CMP and shaped into a rectangular signal differentially. The differential output from the comparator CMP is a single output in the buffer B and is input to the output circuit 12.
[0021]
The output circuit 12 is a push-pull amplifier having a CMOS configuration that includes a PMOS transistor QP and an NMOS transistor QN, using a power supply voltage Vcc input to the power input terminal P11 and a GND potential applied to the ground terminal P12 as power supplies. The output Vout to the output terminal P13 is inverted from the output from the buffer B and becomes either the power supply voltage Vcc or the GND potential.
[0022]
The first stage amplifiers A11 and A12, the differential amplifiers A2 and A3, the comparator CMP, and the buffer B are supplied with power from the bias circuit 13. Whether or not the bias circuit 13 supplies power is controlled by the shutdown circuit 14 in response to a shutdown signal input to the shutdown input terminal P14 from the outside.
[0023]
FIG. 2 is a block diagram showing a specific configuration of the bias circuit 13 and the shutdown circuit 14 in the optical receiver circuit 11 configured as described above, and portions corresponding to those in FIG. Attached is shown. The bias circuit 13 includes PMOS transistors Q11 and Q12 for controlling whether or not the power supply voltage Vcc is supplied to the first stage amplifiers A11 and A12, a PMOS transistor Q10 for commonly controlling the PMOS transistors Q11 and Q12, The NMOS transistors Q2, Q3, Q4, and Q5 that control whether or not to supply power by connecting the differential amplifiers A2 and A3, the comparator CMP, and the buffer B to the GND potential, respectively, and the NMOS transistors Q2 to Q5 are shared. And an NMOS transistor Q0 to be controlled.
[0024]
The drains of the PMOS transistors Q11 and Q12 are connected to the high-level power supply inputs of the first stage amplifiers A11 and A12, respectively, the power supply voltage Vcc is commonly applied to the sources, and the gates are commonly connected to the drain of the PMOS transistor Q10. The The source of the PMOS transistor Q10 is supplied with the power supply voltage Vcc, and the gate thereof is supplied with the output of the inverter INV1 on the previous stage among the two stages of inverters INV1 and INV2 constituting the shutdown circuit 14. A low level bias PBIAS is also applied to the drain of the PMOS transistor Q10, that is, the gates of the PMOS transistors Q11 and Q12 via a pull-down resistor (not shown). The power inputs on the low level side of the first stage amplifiers A11 and A12 are both connected to the GND potential (not shown).
[0025]
The drains of the NMOS transistors Q2, Q3, Q4, and Q5 are connected to the power inputs on the low level side of the differential amplifiers A2 and A3, the comparator CMP, and the buffer B, respectively, the sources are commonly connected to the GND potential, and the gates are commonly used. Are connected to the drain of the NMOS transistor Q0. The source of the NMOS transistor Q0 is connected to the GND potential, and the output of the inverter INV2 on the rear stage side of the shutdown circuit 14 is given to the gate. The drain of the NMOS transistor Q0, that is, the gate of the NMOS transistors Q2, Q3, Q4, and Q5 is also supplied with a high level bias NBIAS via a pull-up resistor (not shown). A power supply voltage Vcc is applied to the high-level power inputs of the differential amplifiers A2 and A3, the comparator CMP, and the buffer B (not shown).
[0026]
Accordingly, while the shutdown signal is at the low level, the output of the inverter INV1 is at the high level and the PMOS transistor Q10 is turned off, whereby the gates of the PMOS transistors Q11 and Q12 are biased to the low level, and the PMOS transistor Q11 , Q12 are turned ON, and a desired constant current is supplied to the first stage amplifiers A11, A12. Similarly, when the shutdown signal is at a low level, the output of the inverter INV2 is at a low level and the NMOS transistor Q0 is turned OFF, whereby the gates of the NMOS transistors Q2 to Q5 are biased to a high level, and the NMOS transistor Q2 ... Q5 is turned ON, and a desired constant current is supplied to the differential amplifiers A2 and A3, the comparator CMP, and the buffer B.
[0027]
On the other hand, when the shutdown signal becomes a high level, the output of the inverter INV1 becomes a low level and the PMOS transistor Q10 is turned on, whereby the gates of the PMOS transistors Q11 and Q12 become the high level, and the PMOS transistors Q11, Q11, Q12 is turned OFF, and a desired constant current is not supplied to the first stage amplifiers A11 and A12. Similarly, when the shutdown signal becomes high level, the output of the inverter INV2 becomes high level and the NMOS transistor Q0 is turned on, whereby the gates of the NMOS transistors Q2 to Q5 become low level, and the NMOS transistors Q2 to Q5 The desired constant current is not supplied to the differential amplifiers A2 and A3, the comparator CMP, and the buffer B.
[0028]
Thus, when the operation of the optical receiver circuit 11 is not required, the bias signal 13 can be shut down by setting the shutdown signal to a high level, thereby shutting down the bias current supplied to each internal circuit. As a result, the power consumption of the optical receiver circuit 11 can be reduced. For example, the current consumption during normal operation of the optical receiver circuit 11 is 2 mA on average, and 1 μA at the maximum during shutdown. Thereby, for example, when a 500 mAH battery is mounted on a mobile phone terminal, the standby time can be increased from 250 hours to 300 hours.
[0029]
In order to realize such shutdown control for power saving, the shutdown regulator 14 and the control MOS transistors Q10 and Q0 are built in the chip of the optical receiver circuit 11, so that a main regulator (not shown) is provided. Further, power can be supplied directly from the smoothing capacitor, and the mounting area can be reduced by 16%, for example, compared with the case where the regulator IC for shutdown control and the smoothing capacitor are interposed in the middle, thereby reducing the cost. Can do. Further, the current consumption during operation can be reduced to, for example, 12 mA to 1/6 of the 2 mA on average because the current consumption by the regulator IC for shutdown control and its smoothing capacitor is eliminated. In this case, if Vcc = 1.5V, the power consumption is 3 mW.
[0030]
Further, the bias circuit 13 is usually of a diode structure, and a plurality of MOS transistors Q11, Q12; Q2-Q5, which are first MOS transistors for supplying a constant current to each internal circuit, are divided by polarity. MOS transistors Q11, Q12; Q2-Q5 are collectively controlled by MOS transistors Q10, Q0, which are second MOS transistors, respectively, so that when the transistors Q11, Q12; Q2-Q5 are composed of bipolar transistors, The base current needs to be supplied to the transistors Q10 and Q0 which are turned on at the time of shutdown, but by using the MOS transistor, it is only necessary to apply a voltage to the gate, and such an unnecessary current flows. In other words, the power consumption can be further reduced.
[0031]
Furthermore, in the case where the output circuit 12 is composed of bipolar transistors, in order to increase the amplitude range of the output Vout, an open collector type is used, and an external pull-up resistor is added to further increase the response of the output Vout. In order to reduce the CR time constant between the parasitic capacitance or load capacitance of the bipolar transistor and the pull-up resistor, it is necessary to reduce the value of the pull-up resistor, which increases the load current flowing through the pull-up resistor. On the other hand, by configuring the MOS transistors QP and QN, the response of the MOS transistor is determined by the ON resistance, so that the load current does not increase and a sufficient response speed is reduced. It can be realized with electric power.
[0032]
Thus, in the present invention, a BiCMOS process in which a MOS process is added to the bipolar processes such as the amplifiers A11, A12, A2, A3, the comparator CMP, and the buffer B is adopted, and the MOS transistors Q11, Q12, Q10: Q2 to Q5 and Q0 are created.
[0033]
3-6 is a figure which shows an example of the optical / electrical transmission apparatus 21 which mounts the chip | tip of the optical receiver circuit 11 comprised as mentioned above. FIG. 3 is a plan view, FIG. 4 is a cross-sectional view taken along the section line AA of FIG. 3, and FIG. 5 is a front view of the module 22 on which the chip of the optical receiver circuit 11 is mounted. The module 22 is provided on the opposite side to the insertion port 24 of the plug 23 in the optical / electrical transmission device 21, and the chip of the optical receiver circuit 11 faces the head of the plug 23.
[0034]
FIG. 6 is a diagram showing the presence / absence of the plug 23 and the manner in which it is detected. The plug 23 is created based on a single-headed so-called stereo mini plug PL1 for audio. In this plug PL1, the head PL1a is for L channel signals, the short body portion PL1b connected to it is for R channel signals, and the long body portion PL1c connected to it is for GND for LR sharing. It transmits analog audio signals via electric wires.
[0035]
On the other hand, in the plug PL2 that transmits a digital audio signal through an electric wire, the head PL2a is for a + signal, the short body portion PL2b that is connected to the head PL2a is for a-signal, and is further connected to it. The short body part PL2c is for GND, and the short body part PL2d connected thereto is insulated.
[0036]
Further, the plug PL3 for transmitting a digital audio signal through an optical fiber has a head PL3a made of metal, and a long body portion PL3b connected to the plug PL3 is insulated, so that the inside of these cylindrical optical fibers is optical fiber. Are communicated, and the end face is exposed from the tip of the head PL3a.
[0037]
The optical / electrical transmission device 21 is generally configured to include a cylindrical holder 25 having the insertion port 24 therein and the module 22. As described above, the module 22 is provided at the distal end of the insertion port 24, and the module 22 has four terminals 26 a, 26 b, 26 c, and 26 d that are led out from the peripheral edge of the chip of the optical receiver circuit 11. Is provided. The terminals P11, P12, P13, and P14 of the chip are electrically connected to the terminals 26a, 26b, 26c, and 26d by bonding wires 27. The terminal 26a serves as an input terminal for the power supply voltage Vcc. 26b serves as an input terminal for the ground potential GND, terminal 26c serves as an output terminal for the output signal Vout, and terminal 26d serves as an input terminal for a shutdown signal.
[0038]
After the chip of the optical receiver circuit 11 is mounted on the frame 26e connected to the terminal 26b of the GND potential, the module 22 is connected to each terminal 26a, 26b, 26c, 26d and the chip by wire bonding, The terminals 26a, 26b, 26c, and 26d are integrally formed by molding using a translucent resin. For example, the chip size of the optical receiver circuit 11 is 1.3 mm square, and the terminal widths of the terminals 26a, 26b, 26c, and 26d are 0.4 mm.
[0039]
On the other hand, in the holding body 25, terminals 28a, 28b, 28c, 28d, 28e, and 28f for electrical connection are formed from the inner peripheral surface of the insertion port 24 to the outside. Terminals 28a, 28b, and 28c are for audio signal transmission and correspond to the plugs PL1 and PL2. When the plugs PL1 and PL2 are fitted into the insertion port 24, the terminals 28a, 28b, and 28c are respectively connected to the respective parts. PL1a, PL2a; PL1b, PL2b: electrically connected to PL1c, PL2c.
[0040]
On the other hand, the terminals 28d, 28e, and 28f are terminals for determining whether or not the plug 23 is inserted and the type of the plug 23, and outside the photoelectric transmission apparatus 21, the terminal 28d is a pull-up resistor R1. Is connected to the reference voltage Vref, the terminal 28e is connected to GND, and the terminal 28f is connected to the reference voltage Vref via the pull-up resistor R2. The terminal 28c is also externally connected to the reference voltage Vref via the pull-up resistor R3. Furthermore, the terminal 28e is a movable contact 28g, which forms a switch with the fixed contact 28h connected to the terminal 28d. When the plug 23 is mounted, it is pressed by the plug 23 and the movable contact 28g is fixed. It touches 28h and is separated when not attached.
[0041]
Therefore, if the potentials of the terminals 28d, 28f, and 28c connected to the reference voltage Vref through the pull-up resistors R1, R2, and R3 are V1, V2, and V3, respectively, as shown in FIG. , 28h are turned on, the potential V1 becomes low level, and the terminals 28f, 28c and the terminal 28e are turned on by the long body portion PL1c, so that the potentials V2, V3 become all low levels. It can be determined that the signal plug PL1 is attached. Further, when the contacts 28g and 28h are turned on, the potential V1 is at a low level, the terminal 28f is insulated by the short body PL2d, the potential V2 is at a high level, and the terminal 28c and the terminal 28e are at the short body PL2c. When the potential V3 becomes low level due to conduction, it can be determined that the plug PL2 for digital electric signal is attached. Furthermore, when the contacts 28g and 28h are turned on, the potential V1 becomes low level, and the terminals 28f and 28c and the terminal 28e are insulated by the long body portion PL3b so that the potentials V2 and V3 become high level. It can be determined that the digital signal plug PL3 is attached. Further, when the contacts 28g and 28h are cut off, the potential V1 is at a high level, and when the terminals 28f and 28c and the terminal 28e are open, the potentials V2 and V3 are all at a high level. It can be determined that the plugs PL1 to PL3 are not attached.
[0042]
In this way, whether any of the electrical analog, electrical digital, and optical digital plugs PL1 to PL3 is used, whether or not the plugs PL1 to PL3 are installed is determined. However, it can be understood that any signal can be shared.
[0043]
Here, in the above description, the chip mounted on the module 22 provided in the optical / electrical transmission device 21 is described by taking the optical receiver circuit 11 as an example, but it may be an optical transmitter circuit. An example of the module 32 in that case is shown in FIG. The module 32 includes a light emitting element LED and a drive circuit 33 that drives the light emitting element LED and mounts the shutdown circuit. The chip of the light emitting element LED is mounted on the frame 36e connected to the input terminal 36a of the power supply voltage Vcc, the chip of the drive circuit 33 is mounted on the frame 36f connected to the terminal 36b of the GND potential, and the input terminal 36a of the power supply voltage Vcc, After the GND potential terminal 36b, the input signal Vin input terminal 36c and / or the shutdown signal input terminal 36d are electrically connected to each other by a bonding wire 37, a die molding is performed using a translucent resin. Is done.
[0044]
8 to 11 are diagrams each showing a mode of shutdown control. In these examples, the chip of the light receiving circuit 11 described above is used as the optical / electrical transmission device 21, but the same applies to the chip of the light emitting element LED and the driving circuit 33. In the example of FIGS. 8 to 10, the optical receiving signal 11 is attached to the optical receiving circuit 11 from FIG. 6, so that the potential V <b> 1 is at a low level and the potential V <b> 3 is at a high level. In this example, the power supply may be performed only at a certain time and the shutdown operation may be performed in the remaining case. That is, the potential V1 and the potential V3 are used as plug insertion presence / absence detection means and plug type detection means.
[0045]
The example of FIG. 8 is an example in which a simple logic circuit 41 is provided as a control circuit for determining whether shutdown is necessary or not outside the shared optical transmission apparatus 21. The logic circuit 41 includes an inverter 42 and an OR circuit. Circuit 43. The potential V1 is directly applied to one input of the OR circuit 43, and the other input of the OR circuit 43 is input after the potential V3 is inverted by the inverter. Therefore, the shutdown signal SD given from the inverter 43 to the terminal 26d is low only when the two inputs of the OR circuit 43 are both low level, that is, when the potential V1 is low level and the potential V3 is high level. It becomes a level, and when it is remaining, it becomes a high level.
[0046]
Thus, only by adding a simple logic circuit 41, power is supplied only when the plug 23 is inserted and it is the optical digital signal plug PL3, and when the plug 23 is not inserted, and Even if it is inserted, if it is the electric plugs PL1 and PL2, shutdown control for shutting off the power supply can be performed.
[0047]
Further, the example of FIG. 9 is an example in which the optical receiving circuit 11a having a function as an internal determination circuit that determines whether shutdown is necessary is used. That is, a circuit such as the logic circuit 41 is further provided in the optical receiver circuit 11a, and the optical receiver circuit 11a has a potential as a plug insertion presence / absence detecting means and a plug type detecting means. In order to input V1 and potential V3, respectively, two terminals 26d1 and 26d2 are provided as shutdown signal input terminals.
[0048]
As a result, the shutdown control can be appropriately performed by the internal determination of the optical / electrical transmission apparatus 21a, and the control is performed by a simple logical process inside, so that a software burden is imposed on an external microcomputer or the like. Shutdown control can be performed without giving.
[0049]
Furthermore, the example of FIG. 10 is an example in which a control circuit 44 for determining whether shutdown is necessary is provided outside the shared optical transmission apparatus 21. The control circuit 44 is provided for digital signal processing. A microcomputer or a digital signal processor (DSP) can be used. The control circuit 44 receives the potential V1 and the potential V3 as the plug insertion presence / absence detecting means and the plug type detecting means, and outputs a shutdown signal SD to the terminal 26d of the optical receiving circuit 11 in response thereto. To do.
[0050]
Thus, shutdown control can be performed without providing a dedicated circuit such as the logic circuit 41 separately. In addition, after the presence / absence of plug insertion and the determination of the type, it is possible to perform control such as releasing the shutdown after a predetermined delay time has elapsed.
[0051]
The example of FIG. 11 uses a control circuit 45 that also serves as a digital signal processing microcomputer or DSP provided outside, as in the example of FIG. In this example, control is performed by determining whether shutdown is necessary in response to an operation on the circuit 46.
[0052]
As a result, for example, when audio data is downloaded from a digital audio device to a mobile phone terminal, it is possible to realize a control in which power is supplied to the optical receiving circuit 11 after the recording state is set, and according to the operation state of the device. Shutdown control can be performed. Needless to say, the control circuit 45 may be inputted with the potential V1 and the potential V3 to perform the shutdown control in more detail by combining the external operation with the results of the insertion detection and the type detection. Yes.
[0053]
The following will describe another embodiment of the present invention with reference to FIG. 12 and FIG.
[0054]
FIG. 12 is a front view of an optical transmission device 51 according to another embodiment of the present invention on which the above-described optical receiver circuit 11 is mounted, and FIG. 13 is a side view thereof. 12 and 13, parts corresponding to those in FIGS. 3 to 5 described above are given the same reference numerals, and descriptions thereof are omitted. This optical transmission device 51 is a rectangular optical transmission device compliant with the digital audio interface standard RC-5720B, and a substantially rectangular insertion port 53 is formed in a holding body 52 that houses and holds the optical reception circuit 11. The optical receiving circuit 11 is disposed at the rear portion of the insertion port 53. Conductive contact pieces 54, 55 face a pair of inner peripheral surfaces (upper surface and lower surface in FIGS. 12 and 13) facing each other in the rectangular insertion port 53, and these contact pieces 54, 55 communicates with terminals 54a and 55a extending from the outer peripheral surface of the holding body 52 (the lower surface in FIGS. 12 and 13) to the outside. On the inner peripheral surface of the insertion port 53, a pair of spring portions 53a that generate a resilient force for holding the attached plug 56 is provided.
[0055]
Correspondingly, the plug 56 is formed with a substantially rectangular insertion tube portion 57 that fits into the insertion port 53, and an optical fiber 58 is held in the insertion tube portion 57. In the rectangular insertion cylinder portion 57, a pair of outer peripheral surfaces (upper surface and lower surface in FIGS. 12 and 13) face plate spring-like conductive contact pieces 59a and 59b, and these contact pieces 59a. 59 b are mutually short-circuited by a short-circuit piece 59 in the plug 56.
[0056]
Therefore, when the plug 56 is attached to the insertion port 53, the end face of the optical fiber 58 faces the light receiving surface of the photodiode PD, and the contact pieces 54 and 55 are short-circuited by the contact pieces 59a and 59b and the short-circuit piece 59. Is done. Therefore, for example, by pulling up the terminal 54a to the power supply voltage Vcc with a pull-up resistor or the like and setting the terminal 55a to the GND potential, the mounting detection can be performed from the potential of the terminal 54a and the above-described shutdown control can be performed. it can.
[0057]
The following will describe still another embodiment of the present invention with reference to FIGS.
[0058]
14 is a front view of an optical transmission device 61 according to still another embodiment of the present invention on which the above-described optical receiver circuit 11 is mounted, FIG. 15 is a side view thereof, and FIG. 16 is a cross-sectional line in FIG. FIG. 17 is a cross-sectional view taken along line BB in FIG. 15, and FIG. 18 is a cross-sectional view showing a state where the plug 69 is attached to FIG. The optical transmission device 61 is similar to the optical transmission device 51 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that this optical transmission device 61 is provided with a shutter 63 at the insertion port 53.
[0059]
Correspondingly, the holding body 62 is provided with a pair of upper and lower pins 64 for supporting one end of the shutter 63 so as to be swingable about a vertical axis, and the shutter 63 is moved from the inner side to the outer side. A biasing spring 65 is provided. The holding body 62 has a part of the inner wall 66 corresponding to the one end 65b that presses the shutter 63 of the spring 65 formed of a conductive resin or a metal terminal. The spring 65 and the inner wall 66 are formed to extend to the outside and serve as terminals 65a and 66a.
[0060]
Therefore, the spring 65 and the inner wall 66 constitute a switch that is turned ON / OFF in accordance with whether or not the plug 69 is attached. That is, when the plug 69 is not attached and the shutter 63 is closed, the one end 65b of the spring 65 is separated from the inner wall 66, thereby blocking between the terminals 65a and 66a. On the other hand, when the plug 69 is attached, the shutter 63 is opened, and one end 65b of the spring 65 comes into contact with the inner wall 66, whereby the terminals 65a and 66a are electrically connected. In this way, the presence or absence of the plug 69 can be detected from the open / closed state of the shutter 63.
[0061]
Accordingly, it is not necessary to provide a dedicated metal terminal for mounting detection such as the contact pieces 54 and 55. It should be noted that the shutter 63 itself may be made of conductive resin or metal and connected to an external terminal, and mounting detection may be performed based on whether or not the shutter 63 and the inner wall 66 are electrically connected.
[0062]
The chip of the optical receiver circuit 11 and the chip of the light emitting element LED and the drive circuit 33 of the present invention described above, and the transmission devices 21, 51 and 61 on which they are mounted are electronic devices that perform at least optical signal communication, particularly power saving. Therefore, it is preferable that the shutdown control can be realized with almost no increase in the chip area of the circuit portion.
[0063]
【The invention's effect】
As described above, the optical communication circuit chip of the present invention is an optical communication circuit chip that converts electrical signals into optical signals for communication, and whether or not a plug of a transmission medium such as an optical fiber is attached to a corresponding jack. In response to a shutdown signal input from the outside in response to a user operation or the like, a shutdown circuit that cuts off the power supply to the internal circuit is incorporated.
[0064]
Therefore, the board space and cost can be reduced as compared with the case where a separate regulator IC is used.
[0065]
Further, as described above, the optical communication circuit chip of the present invention comprises a bias circuit that supplies power to the internal circuit, including a first MOS transistor that supplies a constant current to each internal circuit. The shutdown circuit includes a second MOS transistor that controls the gate of the first MOS transistor, and a control circuit that drives the second MOS transistor in response to the shutdown signal.
[0066]
Therefore, when the first and second transistors are bipolar transistors, it is necessary to supply a base current to the transistor that is turned on at the time of shutdown. Unnecessary current does not flow and power consumption can be further reduced.
[0067]
Furthermore, in the optical communication circuit chip of the present invention, the circuit of the output stage is composed of MOS transistors as described above.
[0068]
Therefore, when the circuit of the output stage is composed of bipolar transistors, in order to increase the amplitude range of the output signal, it is made an open collector type, an external pull-up resistor is added, and the response of the output signal is further accelerated. However, it is necessary to reduce the value of the pull-up resistor, so that the load current flowing through the pull-up resistor is increased. On the other hand, the MOS transistor is used to increase the load current. And a sufficient response speed can be achieved with low power consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an electrical configuration of an optical receiver circuit which is an optical communication circuit chip according to an embodiment of the present invention.
2 is a block diagram showing a specific configuration of a bias circuit and a shutdown circuit in the optical receiver circuit shown in FIG. 1. FIG.
FIG. 3 is a plan view showing an example of an optical / electrical transmission apparatus on which the chip of the optical receiver circuit shown in FIGS. 1 and 2 is mounted.
4 is a cross-sectional view taken along section line AA of FIG.
FIG. 5 is a front view of a module on which the chip of the optical receiver circuit is mounted.
FIG. 6 is a diagram showing how a plug is attached and its type is detected.
FIG. 7 is a diagram illustrating an example of a transmission module as an example of the optical communication circuit chip.
FIG. 8 is a diagram illustrating an example of shutdown control.
FIG. 9 is a diagram illustrating another example of shutdown control.
FIG. 10 is a diagram illustrating still another example of shutdown control.
FIG. 11 is a diagram illustrating another example of shutdown control.
FIG. 12 is a front view of an optical transmission apparatus according to another embodiment of the present invention on which the above-described optical receiver circuit is mounted.
13 is a side view of FIG.
FIG. 14 is a front view of an optical transmission apparatus according to still another embodiment of the present invention on which the above-described optical receiver circuit is mounted.
15 is a side view of FIG.
16 is a cross-sectional view taken along section line BB in FIG.
17 is a cross-sectional view taken along the section line CC in FIG.
18 is a cross-sectional view showing a state where the plug is attached to FIG.
FIG. 19 is a block diagram showing conventional shutdown control.
[Explanation of symbols]
11 Optical receiver circuit
11a Optical receiver circuit (internal determination circuit)
12 Output circuit
13 Bias circuit
14 Shutdown circuit
21, 21a Opto-electric shared transmission device
22,32 modules
23, 56, 69 plug
24, 53 insertion slot
25, 52, 62 holder
26a, 26b, 26c, 26d; 36a, 36b, 36c, 36d terminals
26d1, 26d2 terminal
27,37 Bonding wire
28a, 28b, 28c, 28d, 28e, 28f terminals
28g, 28h contact (insertion presence detection means, type detection means)
33 Drive circuit
41 logic circuit
42 Inverter
43 OR circuit
44, 45 Control circuit
46 Key operation circuit
51, 61 Optical transmission equipment
53a Spring part
54,55 Contact piece (second metal terminal)
54a, 55a terminals
56 Shorting piece
57 Insertion tube
58 optical fiber
59a, 59b Contact piece (first metal terminal)
63 Shutter
65 Spring (switch)
65a, 66a terminals
66 Inner wall (switch)
A11, A12 First stage amplifier
A2, A3 differential amplifier
B buffer
C1, C2 coupling capacitor
CD dummy capacity
CMP comparator
INV1, INV2 inverter
LED light emitting element
P11 Power input terminal
P12 Ground terminal
P13 output terminal
P14 Shutdown input terminal
PD photodiode
PL1 Electric analog plug
PL2 Electric digital plug
PL3 optical digital plug
PL1a; PL2a; PL3a Head
PL1b; PL2b, PL2c Short trunk
PL1c Long torso
PL2d short body
PL3b long torso
Q0 NMOS transistor (second MOS transistor)
Q2, Q3, Q4, Q5 NMOS transistor (first MOS transistor)
Q10 PMOS transistor (second MOS transistor)
Q11, Q12 PMOS transistor (first MOS transistor)
QP PMOS transistor
QN NMOS transistor
R1, R2, R3 pull-up resistors (insertion detection means, type detection means)
R11, R12 resistance
R21, R22 Pull-up resistors

Claims (3)

In an optical communication circuit chip that converts electrical signals into optical signals for communication,
A shutdown input terminal, an internal circuit, and a shutdown circuit are provided.
The shutdown circuit is responsive to a shutdown signal externally input to the shutdown input terminal of said optical communication circuit chip, e Bei shutdown circuit to cut off the power supply to the internal circuit,
The bias circuit that supplies power to the internal circuit includes a first MOS transistor that supplies a constant current to each internal circuit.
The shutdown circuit is
The plurality of first MOS transistors are divided according to polarity, and each of the first MOS transistors includes a second MOS transistor that collectively controls,
The second MOS transistor controls the gate of the first MOS transistor,
An optical communication circuit chip , wherein the shutdown circuit includes a control circuit that drives the second MOS transistor in response to the shutdown signal . 2. The optical communication circuit chip according to claim 1, wherein the circuit of the output stage is composed of a MOS transistor. An electronic apparatus comprising the optical communication circuit chip according to claim 1.

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