JP2003218795A - Optical communication circuit chip and electronic apparatus comprising the chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a basic space and a cost for achieving shut-down control to save electricity in a chip of an optical receiving circuit 11 composed of an optical fiber link and communicating by converter a received optical signal into an electrical signal. <P>SOLUTION: In an optical communication circuit chip, a shut-down function is added to a bias circuit 13 for supplying electric power to inner circuits such as a photo diode PD, amplifiers A11, A12, A2 and A3, a comparator CMP and a buffer B, and also a shut-down control circuit 14 for controlling shut-down to the bias circuit 13 in response to a shut down-signal inputted to a shut-down input terminal P14 depending upon whether plugs of optical fibers, etc., are inserted into corresponding jacks or user operations, etc., is provided. Accordingly, for achieving the shut-down control, it is possible to reduce the basic space ant the cost in comparison with the use of an additional regulator IC. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical communication circuit chip used for an optical fiber link that converts an electric signal into an optical signal and transmits the optical signal, and an electronic device including the same.

[0002]

2. Description of the Related Art The above-mentioned optical fiber link converts an electric signal into an optical signal on the transmitting side and transmits the optical signal, and a receiving side reconverts the received optical signal into an electric signal. Since signals of a plurality of channels can be easily transmitted at a high speed by using one optical fiber, it has become widespread in general households in recent years with the spread of digital devices equipped with the optical communication circuit chip. For example, DVD (digital video disc) players, digital broadcast STBs (set top boxes) and CDs (compact discs)
For example, signal transmission from a player to an MD (mini disc) player, an amplifier, or the like. In addition, recently, the transmission of music signals to personal portable devices such as personal computers has become widespread. Furthermore, the optical fiber link is also used for signal transmission in a place where electrical insulation is required.

On the other hand, in the above digital devices, particularly portable devices, there is always a demand for reduction of power consumption that influences battery operation time. Therefore, in the optical communication circuit,
Conventionally, a configuration as shown in FIG. 19 is used.
That is, a regulator IC2 having a shutdown function is interposed between a power supply (not shown) and the optical communication circuit 1, and the regulator IC2 responds to a shutdown signal input to a shutdown input terminal P1 from the power supply (not shown). It controls whether the power supply voltage Vcc input to the power supply input terminal P2 is output from the power supply output terminal P3 to the optical communication circuit 1.

Thus, when the operation of the optical communication circuit 1 is unnecessary, the output of the regulator IC2 is shut down by inputting a shutdown signal to the shutdown input terminal P1 to realize low power consumption.

[0005]

However, when the dedicated regulator IC 2 is provided, it occupies the space of the circuit board, which is disadvantageous in downsizing and is also disadvantageous in terms of cost.

An object of the present invention is to provide an optical communication circuit chip capable of reducing the board space and cost in realizing shutdown control for power saving, and an electronic device including the same.

[0007]

The optical communication circuit chip of the present invention is an optical communication circuit chip for converting an electrical signal into an optical signal for communication, and responds to a shutdown signal input from the outside to an internal circuit. It is characterized by comprising a shutdown circuit for shutting off the power supply of.

According to the above structure, the light receiving element and the signal processing circuit for performing processing such as amplification and waveform shaping of the signal received by the light receiving element, or the light emitting element and the drive for amplifying and transmitting the transmission signal to the light emitting element In an optical communication circuit chip that is configured with circuits, etc., shutdown input from an external control circuit, etc., depending on whether or not a plug of a transmission medium such as an optical fiber is attached to the corresponding jack and user operation etc. In response to the signal, the shutdown circuit controls whether or not power is supplied to internal circuits such as the light receiving element and the signal processing circuit.

Therefore, in realizing the shutdown control for power saving, by incorporating the shutdown circuit in the optical communication circuit chip, the board space and the cost are reduced as compared with the case where the regulator IC is separately used. be able to.

Further, in the optical communication circuit chip of the present invention, the bias circuit for supplying power to the internal circuits comprises a first MOS transistor for supplying a constant current to each internal circuit, and the shutdown circuit is provided. The circuit is configured to include a second MOS transistor that controls the gate of the first MOS transistor, and a control circuit that drives the second MOS transistor in response to the shutdown signal. And

According to the above structure, the bias circuit for supplying power to the internal circuits such as the light receiving element and the signal processing circuit usually has a diode structure and supplies a constant current to each internal circuit. The first MOS transistor is divided by polarity and the like, and one or a plurality of the first MOS transistors are collectively driven by the second MOS transistor.

Therefore, when the first and second transistors are composed of bipolar transistors, it is necessary to supply the base current to the transistor turned on at the time of shutdown, whereas the MOS transistor is used. Such unnecessary current does not flow, and the power consumption can be further reduced.

Furthermore, the optical communication circuit chip of the present invention is characterized in that the circuit at the output stage is composed of MOS transistors.

According to the above construction, when the circuit of the output stage is composed of bipolar transistors, it is of an open collector type in order to increase the amplitude range of its output signal, and a pull-up resistor is externally attached to further output. In order to speed up the signal response, it is necessary to reduce the value of the pull-up resistor, which increases the load current flowing through the pull-up resistor. It is possible to realize a sufficient response speed with low power consumption without causing an increase in current.

The electronic equipment of the present invention is characterized by including any one of the above optical communication circuit chips.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Regarding one embodiment of the present invention,
The following is a description based on FIGS. 1 to 11.

FIG. 1 is a block diagram showing an electrical configuration of an optical receiving circuit 11 which is an optical communication circuit chip according to an embodiment of the present invention. The light receiving circuit 11 is monolithically formed on one chip including the photodiode PD. The light receiving circuit 11 is generally composed of the photodiode PD, a dummy capacitor CD, a first stage amplifier A11,
A12, differential amplifiers A2 and A3, and comparator CM
P, buffer B, output circuit 12, and bias circuit 1
3 and a shutdown circuit 14.

The photodiode PD is biased by the corresponding first-stage amplifier A11, and the current corresponding to the optical signal received from the photodiode PD is converted into a voltage by the resistor R11 of the first-stage amplifier A11. Output with low impedance. Further, the dummy capacitance CD is formed to be equal to the parasitic capacitance of the photodiode PD, and the current flowing through the dummy capacitance CD is converted into a voltage by a first stage amplifier A12 and a resistor R12 having the same configuration as the first stage amplifier A11, and a low voltage. It is output as impedance.

The outputs from the first-stage amplifiers A11 and A12 are
It is given to each input of the differential amplifier A2 which is AC-coupled by the coupling capacitors C1 and C2. The reference voltage Vref is also applied to the respective inputs of the differential amplifier A2 via pull-up resistors R21 and R22. Therefore, each input of the differential amplifier A2 becomes a value obtained by superposing the AC components of the outputs from the first-stage amplifiers A11 and A12 with the reference voltage Vref as the center, and the differential amplifier A2 receives those inputs. The difference is amplified and output as a differential voltage signal. Here, the noise from the GND potential through the photodiode PD, which appears in the output from the first-stage amplifier A11, also appears in the same phase in the output from the first-stage amplifier A12, and therefore this differential amplifier A2
Outputs a signal from which the noise has been removed.

The output from the differential amplifier A2 is further amplified by the differential amplifier A3, and the differential voltage signals of the outputs are compared with each other by the comparator CMP and shaped into a differential rectangular signal. The differential output from the comparator CMP is converted into a single output in the buffer B and input to the output circuit 12.

The output circuit 12 has a power input terminal P11.
Is a push-pull amplifier having a CMOS configuration, which is composed of a PMOS transistor QP and an NMOS transistor QN, and which uses the power supply voltage Vcc input to the input terminal and the GND potential applied to the ground terminal P12 as power supplies, and the output Vout to the output terminal P13 is Invert the output from buffer B,
Further, it becomes either the power supply voltage Vcc or the GND potential.

Power is supplied from the bias circuit 13 to the first-stage amplifiers A11 and A12, the differential amplifiers A2 and A3, the comparator CMP and the buffer B. Whether or not the bias circuit 13 supplies power is controlled by the shutdown circuit 14 in response to a shutdown signal externally input to the shutdown input terminal P14.

FIG. 2 is a block diagram showing a specific configuration of the bias circuit 13 and the shutdown circuit 14 in the optical receiving circuit 11 configured as described above.
Parts corresponding to those in FIG. 1 are designated by the same reference numerals. The bias circuit 13 includes the first-stage amplifiers A11 and A1.
2 and PMOS transistors Q11 and Q12 for controlling whether or not to supply the power supply voltage Vcc to
P for commonly controlling the MOS transistors Q11 and Q12
MOS transistor Q10 and the differential amplifiers A2 and A
3. Comparator CMP and buffer B are set to G
N for controlling whether or not to supply power by connecting to ND potential
N for commonly controlling the MOS transistors Q2, Q3, Q4, Q5 and those NMOS transistors Q2 to Q5
And a MOS transistor Q0.

The PMOS transistors Q11 and Q12
Are connected to the high-level power supply inputs of the first-stage amplifiers A11 and A12, the sources are commonly supplied with the power supply voltage Vcc, and the gates are commonly connected to the drain of the PMOS transistor Q10. The power supply voltage Vcc is applied to the source of the PMOS transistor Q10,
Of the two stages of inverters INV1 and INV2 forming the shutdown circuit 14, the output of the preceding stage inverter INV1 is applied to the gate. A low-level bias PBIAS is also applied to the drain of the PMOS transistor Q10, that is, the gates of the PMOS transistors Q11 and Q12 via a pull-down resistor (not shown).
Is given. The low-level power supply inputs of the first-stage amplifiers A11 and A12 are both connected to the GND potential (not shown).

The NMOS transistors Q2, Q3, Q
The drains of Q4 and Q5 are respectively connected to the low-level power supply inputs of the differential amplifiers A2 and A3, the comparator CMP and the buffer B, the sources are commonly connected to the GND potential, and the gates are commonly connected to the drain of the NMOS transistor Q0. Connected. The source of the NMOS transistor Q0 is connected to the GND potential, and the output of the inverter INV2 on the subsequent stage side of the shutdown circuit 14 is given to the gate. A high level bias NBIAS is also applied to the drain of the NMOS transistor Q0, that is, the gates of the NMOS transistors Q2, Q3, Q4, and Q5 via a pull-up resistor (not shown). A power supply voltage Vcc is applied to the high-level-side power supply inputs of the differential amplifiers A2 and A3, the comparator CMP, and the buffer B (not shown).

Therefore, while the shutdown signal is low level, the output of the inverter INV1 is high level and the PMOS transistor Q10 is off.
As a result, the PMOS transistors Q11 and Q12
Is biased to a low level, the PMOS transistors Q11 and Q12 are turned on, and the first stage amplifier A11,
A desired constant current is supplied to A12. Similarly, when the shutdown signal is low level, the inverter I
The output of NV2 becomes low level and the NMOS transistor Q0 is turned off, whereby the gates of the NMOS transistors Q2 to Q5 are biased to high level and the N
The MOS transistors Q2 to Q5 are turned on, and the differential amplifier A
A desired constant current is supplied to 2, A3, the comparator CMP and the buffer B.

On the other hand, when the shutdown signal goes high, the output of the inverter INV1 goes low and the PMOS transistor Q10 turns on.
As a result, the gates of the PMOS transistors Q11 and Q12 become high level, and the PMOS transistor Q1
1, Q12 is turned off, and the desired constant current is not supplied to the first-stage amplifiers A11, A12. Similarly, when the shutdown signal goes high, the output of the inverter INV2 goes high and the NMOS transistor Q0 is turned on.
N, which causes the gates of the NMOS transistors Q2 to Q5 to go to the low level,
2 to Q5 are turned off, and the desired constant current is not supplied to the differential amplifiers A2 and A3, the comparator CMP and the buffer B.

In this way, when the operation of the optical receiving circuit 11 is unnecessary, the shutdown signal is set to the high level to shut down the bias circuit 13 and thereby shut down the bias current supplied to each internal circuit. You can As a result, the optical receiver circuit 1
It is possible to reduce the power consumption by 1. For example, the current consumption of the optical receiver circuit 11 during normal operation is 2 mA on average, and at shutdown it is 1 μA at maximum. This makes it possible to extend the standby time from 250 hours to 300 hours when a battery of 500 mAH is mounted on a mobile phone terminal, for example.

In order to realize such a shutdown control for power saving, the optical receiving circuit 11
By incorporating the shutdown control circuit 14 and the control MOS transistors Q10 and Q0 in the chip,
Power can be directly supplied from a main regulator and a smoothing capacitor (not shown), and the mounting area is 16% smaller than that when a shutdown control regulator IC and the smoothing capacitor are provided on the way.
It can be reduced and the cost can be reduced.
Further, the current consumption during operation is, for example, 12 mA on average because the current consumption due to the shutdown control regulator IC and its smoothing capacitor is eliminated.
Can be reduced to 1/6 of the above 2 mA. In this case, if Vcc = 1.5V, the power consumption is 3 mW.

Further, in the bias circuit 13, normally,
MOS transistors Q11, Q12; Q2 to Q5, which are first MOS transistors having a diode structure and each of which supplies a constant current to each internal circuit, are divided according to polarity, and a plurality of the MOS transistors Q11, Q12;
2 to Q5 are collectively controlled by the second MOS transistors Q10 and Q0, respectively. Therefore, when the transistors Q11 and Q12; Q2 to Q5 are bipolar transistors, they are turned on at the time of shutdown. While it is necessary to supply a base current to Q10 and Q0, by using a MOS transistor, it is only necessary to apply a voltage to the gate, and such an unnecessary current does not flow, resulting in lower power consumption. Can be converted.

Furthermore, when the output circuit 12 is composed of bipolar transistors, it is of an open collector type in order to increase the amplitude range of the output Vout,
In order to further speed up the response of the output Vout by externally attaching a pull-up resistor, C of the parasitic capacitance or load capacitance of the bipolar transistor and the pull-up resistor is used.
In order to reduce the R time constant, it is necessary to reduce the value of the pull-up resistor, which increases the load current flowing through the pull-up resistor, whereas the MOS transistors QP and QN are used. Since the response of the MOS transistor is determined by the ON resistance, the load current does not increase, and a sufficient response speed can be realized with low power consumption.

As described above, in the present invention, the amplifier A1
1, A12, A2, A3, a comparator CMP, a buffer B, etc., a BiCMOS process in which a MOS process is added to the bipolar process is adopted.
S transistors Q11, Q12, Q10: Q2 to Q5
Creating Q0.

FIG. 3 to FIG. 6 show an optical / electrical shared transmission device 2 on which the chip of the optical receiving circuit 11 configured as described above is mounted.
It is a figure which shows an example of 1. 3 is a plan view, FIG. 4 is a sectional view taken along the section line AA of FIG. 3, and FIG. 5 is a front view of a module 22 on which the chip of the optical receiving circuit 11 is mounted. In the optical / electrical shared transmission device 21, the module 22 is provided on the side opposite to the insertion port 24 of the plug 23, and the chip of the optical receiving circuit 11 faces the head of the plug 23.

FIG. 6 is a diagram showing the presence / absence of the plug 23 and its type detection. The plug 23 is a single-headed stereo mini plug PL1 for so-called audio.
It is created based on. With this plug PL1,
The head portion PL1a is for the L channel signal, the short body portion PL1b connected to it is for the R channel signal, and the long body portion PL1c connected to it is for the LR shared GND. To transmit an analog audio signal.

On the other hand, the plug PL2 for transmitting the digital audio signal via the electric wire is the head PL2a.
Is for + signal, and the short body part PL2b connected to it
Is for signals, and the short body part P connected to it is
L2c is for GND, and the short body part PL2d connected to it is insulated.

In the plug PL3 for transmitting a digital audio signal via an optical fiber, the head portion PL3a is made of metal, and the long body portion PL3b connected to the head portion PL3a is insulated. Through the optical fiber, and the end face thereof is exposed from the tip of the head PL3a.

The optical / electrical shared transmission device 21 generally has a cylindrical holder 25 having the insertion port 24 therein.
And the module 22. As described above, the module 22 is provided at the tip of the insertion port 24, and the module 22 has four terminals 26a, which are drawn out from the peripheral portion of the chip of the optical receiving circuit 11.
26b, 26c and 26d are provided. The terminals P11, P12, P13, P14 of the chip and these terminals 26a, 26b, 26c, 26d are electrically connected by bonding wires 27, respectively.
The terminal 26a becomes an input terminal of the power supply voltage Vcc, and the terminal 2
6b serves as an input terminal for the ground potential GND, the terminal 26c serves as an output terminal for the output signal Vout, and the terminal 26d serves as an input terminal for a shutdown signal.

The module 22 includes the optical receiving circuit 1
After the first chip is mounted on the frame 26e connected to the GND potential terminal 26b, the terminals 26a, 26b, 26
The terminals 26a, 26b, 26c and 26d are formed by internally connecting the c and 26d and the chip by wire bonding and then molding with a translucent resin.
Are integrally molded. For example, the optical receiving circuit 11
Has a chip size of 1.3 mm square and has terminals 26a, 2
The terminal width of 6b, 26c, and 26d is 0.4 mm.

On the other hand, in the holder 25, the insertion port 2
4 from the inner peripheral surface to the outside, terminals 28a, 28 for electrical connection
b, 28c, 28d, 28e and 28f are formed. The terminals 28a, 28b and 28c are for transmitting audio signals and correspond to the plugs PL1 and PL2. When the plugs PL1 and PL2 are fitted into the insertion port 24, the terminals 28a, 28b and 28c are respectively connected to respective parts. PL1a, PL
2a; PL1b, PL2b: electrically connected to PL1c, PL2c.

On the other hand, the terminals 28d, 28e, 28
f is a terminal for determining whether or not the plug 23 is inserted and the type of the plug 23, and outside the opto-electric shared transmission device 21, the terminal 28d is connected to the reference voltage Vref via the pull-up resistor R1. The terminal 28e is connected to GND, and the terminal 28f is connected to the reference voltage Vref via the pull-up resistor R2. Also, the terminal 28c
Is also externally connected to the reference voltage Vref via the pull-up resistor R3. Furthermore, the terminal 28e is a movable contact 28g, which forms a switch with a fixed contact 28h connected to the terminal 28d. When the plug 23 is attached, the movable contact 28g is pressed by the plug 23.
Contacts the fixed contact 28h and is separated when not mounted.

Therefore, each of the pull-up resistors R1,
The potentials of the terminals 28d, 28f, 28c connected to the reference voltage Vref via R2, R3 are respectively V1, V
2, V3, as shown in FIG. 6, contact points 28g, 2
The potential V1 is at a low level when 8h is conducted, and the terminal 28
When the potentials V2 and V3 are all low level due to conduction between the f and 28c and the terminal 28e by the long body portion PL1c, it is determined that the plug PL1 for analog electric signal is attached. You can Also, the contact 28
When g and 28h are conducted, the potential V1 is low level, and the terminal 28f is insulated by the short body portion PL2d, so that the potential V2 is
Is high level and the potential V3 becomes low level due to conduction between the terminal 28c and the terminal 28e by the short body portion PL2c, it can be determined that the plug PL2 for digital electric signal is attached. Furthermore, the contacts 28g, 2
The potential V1 is at a low level when 8h is conducted, and the terminal 28
When the potentials V2 and V3 become high level due to the long barrel portion PL3b insulating between f and 28c and the terminal 28e, it can be determined that the plug PL3 for optical digital signal is attached. Further, when the contacts 28g and 28h are cut off, the potential V1 is at a high level, and when the terminals 28f and 28c and the terminal 28e are opened, the potentials V2 and V3 are also at a high level. Plug P
It is possible to determine that L1 to PL3 are not mounted either.

In this way, whichever plug PL1 to PL3 of electric analog, electric digital, or optical digital is used, whether or not those plugs PL1 to PL3 are mounted, and when they are mounted It will be appreciated that the type can be determined and shared with any signal.

In the above description, the optical receiver circuit 11 is used as an example of the chip mounted on the module 22 provided in the optical / electrical shared transmission device 21.
It may be an optical transmission circuit. Module 32 in that case
An example of is shown in FIG. The module 32 is configured to include a light emitting element LED and a drive circuit 33 that drives the light emitting element LED and mounts the shutdown circuit. The chip of the light emitting element LED is mounted on the frame 36e connected to the input terminal 36a of the power supply voltage Vcc, the chip of the drive circuit 33 is mounted on the frame 36f connected to the terminal 36b of the GND potential, and the input terminal 36a of the power supply voltage Vcc, The bonding wire 37 is formed by connecting the GND potential terminal 36b, the input signal Vin input terminal 36c and / or the shutdown signal input terminal 36d to the chip.
After they are electrically connected to each other, they are molded using a translucent resin.

FIG. 8 to FIG. 11 are diagrams showing the modes of shutdown control. In these examples, the chip of the above-mentioned optical receiving circuit 11 is used as the optical / electrical shared transmission device 21, but the same applies to the chip of the light emitting element LED and the driving circuit 33. 8 to 10
In the example of FIG. 6, from the above-mentioned FIG.
In this example, power is supplied only when 1 is at a low level and the potential V3 is at a high level, and a shutdown operation may be performed at the time of remaining.
That is, the potentials V1 and V3 are used as plug insertion presence / absence detecting means and plug type detecting means.

The example of FIG. 8 is an example in which a simple logic circuit 41 is provided outside the optical / electrical shared transmission device 21 as a control circuit for determining the necessity of shutdown. The logic circuit 41 is an inverter 42. And an OR circuit 43. The potential V1 is directly applied to one input of the OR circuit 43, and the other input of the OR circuit 43 is input after the potential V3 is inverted by the inverter 42.
Therefore, the shutdown signal SD supplied from the inverter 43 to the terminal 26d becomes low only when the two inputs of the OR circuit 43 are both low level, that is, the potential V1 is low level and the potential V3 is high level. It becomes a level, and when it remains, it becomes a high level.

Thus, only by adding the simple logic circuit 41, the power is supplied only when the plug 23 is inserted and it is the plug PL3 for the optical digital signal, and the plug 23 is not inserted. In this case, and if the plugs are electric plugs PL1 and PL2 even if they are inserted, the shutdown control for cutting off the power supply can be performed.

Further, the example of FIG. 9 is an example of using the optical receiving circuit 11a having a function as an internal determination circuit for determining the necessity of shutdown. That is, a circuit such as the logic circuit 41 is further provided in the optical receiving circuit 11a, and the optical receiving circuit 11a has a potential as the plug insertion presence / absence detecting means and the plug type detecting means. Two terminals 26d are provided as input terminals for the shutdown signal in order to input V1 and the potential V3, respectively.
1, 26d2.

As a result, the optical / electrical shared transmission device 21a is provided.
Shutdown control can be performed appropriately by the internal judgment of the system, and because it is controlled by a simple logical process inside, it is possible to perform the shutdown control without giving a software-like burden to an external microcomputer. it can.

Furthermore, the example of FIG. 10 is an example in which a control circuit 44 for deciding the necessity of shutdown is provided outside the optical / electrical shared transmission device 21, and the control circuit 44 is for digital signal processing. Microcomputer or digital signal processor (D
SP) can also be used. The control circuit 44 receives the potentials V1 and V3 as the plug insertion presence / absence detecting means and the plug type detecting means, and outputs a shutdown signal SD to the terminal 26d of the optical receiving circuit 11 in response to the potentials V1 and V3. To do.

Thus, the shutdown control can be performed without separately providing a dedicated circuit such as the logic circuit 41. In addition, it is possible to perform control such as canceling the shutdown after a lapse of a predetermined delay time after determining whether or not the plug is inserted and the type.

Further, in the example of FIG. 11, as in the example of FIG. 10, a control circuit 45 which also serves as a microcomputer or a DSP for digital signal processing provided outside is used, and the control circuit 45 thereof is also used. Is an example of determining whether or not shutdown is necessary in response to an operation on the key operation circuit 46 and performing control.

As a result, it is possible to realize control such that power is supplied to the optical receiving circuit 11 after a recording state, as in the case of downloading audio data from a digital audio device to a mobile phone terminal, for example, and operation of the device. Shutdown control can be performed according to the state. It is needless to say that the potential V1 and the potential V3 may be input to the control circuit 45 to perform the shutdown control in more detail by combining the external operation and the results of the insertion detection and the type detection. Yes.

FIG. 12 shows another embodiment of the present invention.
It will be described below with reference to FIG.

FIG. 12 is a front view of an optical transmission device 51 of another embodiment of the present invention in which the above-mentioned optical receiving circuit 11 is mounted, and FIG. 13 is a side view thereof. 12 and 13, parts corresponding to those in FIGS. 3 to 5 are designated by the same reference numerals, and the description thereof will be omitted. This optical transmission device 51 is a digital audio interface standard R
A rectangular optical transmission device conforming to C-5720B, in which a holding body 52 for accommodating and holding the optical receiving circuit 11 is formed with a substantially rectangular insertion port 53, and the optical receiving circuit 11 is provided with this insertion port. It is located at the rear of 53. The rectangular insertion port 53
At the pair of inner peripheral surfaces (upper surface and lower surface in FIGS. 12 and 13) facing each other, conductive contact pieces 54,
55, and these contact pieces 54, 55 communicate with terminals 54a, 55a extending from the outer peripheral surface of the holding body 52 (the lower surface in FIGS. 12 and 13) to the outside, respectively. The plug 56 mounted on the inner peripheral surface of the insertion port 53 is also mounted.
Pair of spring portions 53a for generating elastic force for holding
Is provided.

Correspondingly, the plug 56 is formed with a substantially rectangular insertion tube portion 57 which is fitted in the insertion port 53, and an optical fiber 58 is held in the insertion tube portion 57. ing. The pair of outer peripheral surfaces (the upper surface and the lower surface in FIGS. 12 and 13) of the square-shaped insertion tube portion 57 face the leaf spring-shaped conductive contact pieces 59a and 59b.
These contact pieces 59a. 59b are short-circuited to each other by a short-circuit piece 59 in the plug 56.

Therefore, when the plug 56 is attached to the insertion port 53, the end surface of the optical fiber 58 faces the light receiving surface of the photodiode PD, and the contact pieces 54, 55 are contacted by the contact pieces 59a, 59b and the short-circuit piece 59. Shorted to each other. Therefore, for example, the terminal 54a is pulled up to the power supply voltage Vcc by a pull-up resistor or the like,
By setting the terminal 55a to the GND potential, the terminal 54a
It is possible to detect the attachment from the potential of and to perform the shutdown control described above.

With respect to still another embodiment of the present invention,
The following is a description based on FIGS. 14 to 17.

FIG. 14 is a front view of an optical transmission device 61 according to still another embodiment of the present invention in which the above-described optical receiving circuit 11 is mounted, FIG. 15 is a side view thereof, and FIG. 16 is FIG.
17 is a cross-sectional view as seen from the section line B-B of FIG.
5 is a sectional view taken along the line C-C of FIG. 5, and FIG. 18 is a sectional view showing a state in which the plug 69 is mounted in FIG. 16.
This optical transmission device 61 is similar to the above-described optical transmission device 51, and corresponding parts are designated by the same reference numerals and description thereof is omitted. It should be noted that in this optical transmission device 61, a shutter 63 is provided at the insertion port 53.

Correspondingly, the holding body 62 is provided with a pair of upper and lower pins 64 for supporting one end of the shutter 63 so as to be swingable about the vertical axis, and the shutter 63 from the inside to the outside. A spring 65 that urges toward one side is provided. Further, the holding body 62 has a part of the inner wall 6 corresponding to one end 65b of the spring 65 that presses the shutter 63.
6 is formed of a conductive resin or a metal terminal. The spring 65 and the inner wall 66 are formed to extend to the outside and serve as terminals 65a and 66a.

Therefore, the spring 65 and the inner wall 66 constitute a switch which is turned on / off depending on whether the plug 69 is attached or not. That is, in the state where the plug 69 is not attached and the shutter 63 is closed, the one end 65b of the spring 65 is separated from the inner wall 66, thereby disconnecting the terminals 65a and 66a. On the other hand, when the plug 69 is attached, the shutter 63 is opened, and the one end 65b of the spring 65 contacts the inner wall 66, whereby the terminals 65a and 66a are electrically connected. In this way, whether or not the plug 69 is attached can be detected from the opened / closed state of the shutter 63.

As a result, it is not necessary to provide a dedicated metal terminal for detecting attachment such as the contact pieces 54 and 55. The shutter 63 itself is made of conductive resin or metal and is connected to an external terminal.
The attachment detection may be performed based on whether or not the inner wall 66 and the inner wall 66 are electrically connected to each other.

The above-described chip of the optical receiving circuit 11 of the present invention, the chip of the light emitting element LED and the driving circuit 33, and the transmission devices 21, 51 and 61 equipped with them are at least electronic devices for communicating optical signals, in particular. In a portable device with strong demand for power saving, shutdown control can be realized without increasing the chip area of the circuit portion, which is preferable.

[0063]

As described above, in the optical communication circuit chip of the present invention, a plug of a transmission medium such as an optical fiber is attached to the corresponding jack in the optical communication circuit chip for converting an electric signal into an optical signal for communication. A shutdown circuit that shuts off the power supply to the internal circuit in response to a shutdown signal input from the outside according to whether or not it is being operated, a user operation, or the like is incorporated.

Therefore, as compared with the case where a regulator IC is separately used, the board space and the cost can be reduced.

In the optical communication circuit chip of the present invention, as described above, the bias circuit for supplying power to the internal circuits is supplied to the first M circuit for supplying a constant current to each internal circuit.
A second MOS transistor configured to include an OS transistor, the shutdown circuit controlling a gate of the first MOS transistor, and a control circuit driving the second MOS transistor in response to the shutdown signal. And is configured.

Therefore, when the first and second transistors are composed of bipolar transistors, it is necessary to supply the base current to the transistor turned on at the time of shutdown, whereas the MOS transistor is used. Moreover, such an unnecessary current does not flow, and the power consumption can be further reduced.

Furthermore, in the optical communication circuit chip of the present invention, the circuit of the output stage is composed of MOS transistors as described above.

Therefore, when the circuit of the output stage is composed of bipolar transistors, the open-collector type is adopted in order to widen the amplitude range of the output signal, a pull-up resistor is externally attached, and the response of the output signal is further increased. In order to increase the speed, it is necessary to reduce the value of the pull-up resistor. Therefore, the load current flowing through the pull-up resistor increases, whereas the MOS transistor is used to increase the load current. It is possible to realize a sufficient response speed with low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an optical receiving circuit that is an optical communication circuit chip according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a bias circuit and a shutdown circuit in the optical receiving circuit shown in FIG.

FIG. 3 is a plan view showing an example of an optical / electrical shared transmission device equipped with a chip of the optical receiving circuit shown in FIGS. 1 and 2.

4 is a cross-sectional view taken along the section line AA of FIG.

FIG. 5 is a front view of a module on which the chip of the optical receiving circuit is mounted.

FIG. 6 is a diagram showing how a plug is attached and its type is detected.

FIG. 7 is a diagram showing an example of a transmission module as an example of the optical communication circuit chip.

FIG. 8 is a diagram showing an example of shutdown control.

FIG. 9 is a diagram showing another example of shutdown control.

FIG. 10 is a diagram showing still another example of shutdown control.

FIG. 11 is a diagram showing another example of shutdown control.

FIG. 12 is a front view of an optical transmission device according to another embodiment of the present invention, which is equipped with the optical receiving circuit described above.

FIG. 13 is a side view of FIG.

FIG. 14 is a front view of an optical transmission device according to still another embodiment of the present invention, which is equipped with the above-described optical receiving circuit.

FIG. 15 is a side view of FIG.

16 is a cross-sectional view taken along the section line BB of FIG.

FIG. 17 is a sectional view taken along the line C-C in FIG.

FIG. 18 is a cross-sectional view showing a state in which the plug is attached to FIG. 16.

FIG. 19 is a block diagram showing conventional shutdown control.

[Explanation of symbols]

11 Optical Receiver Circuit 11a Optical Receiver Circuit (Internal Judgment Circuit) 12 Output Circuit 13 Bias Circuit 14 Shutdown Circuit 21, 21a Photoelectric Common Transmission Device 22, 32 Module 23, 56, 69 Plug 24, 53 Insertion Port 25, 52, 62 Holders 26a, 26b, 26c, 26d; 36a, 36b, 3
6c, 36d terminals 26d1, 26d2 terminals 27, 37 bonding wires 28a, 28b, 28c, 28d, 28e, 28f
Terminals 28g, 28h Contact points (insertion presence / absence detection means, type detection means) 33 Drive circuit 41 Logic circuit 42 Inverter 43 OR circuit 44, 45 Control circuit 46 Key operation circuit 51, 61 Optical transmission device 53a Spring portion 54, 55 Contact piece ( Second metal terminal) 54a, 55a terminal 56 Short-circuit piece 57 Inserting tube portion 58 Optical fiber 59a, 59b Contact piece (first metal terminal) 63 Shutter 65 Spring (switch) 65a, 66a Terminal 66 Inner wall (switch) A11, A12 First stage amplifier A2, A3 Differential amplifier B Buffer C1, C2 Coupling capacitor CD Dummy capacitance CMP Comparator INV1, INV2 Inverter LED Light emitting element P11 Power input terminal P12 Ground terminal P13 Output terminal P14 Shutdown input terminal PD Photodiode PL1 Electrical analog plug L2 electric digital plug PL3 optical digital plug PL1a; PL2a; PL3a head PL1b; PL2b, PL2c short trunk PL1c long trunk PL2d short trunk PL3b long trunk Q0 NMOS transistor (second MOS transistor) Q2, Q3 , Q4, Q5 NMOS transistors (first
MOS transistor) Q10 PMOS transistor (second MOS transistor) Q11, Q12 PMOS transistor (first MO transistor)
S transistor) QP PMOS transistor QN NMOS transistor R1, R2, R3 pull-up resistance (insertion presence / absence detection means, type detection means) R11, R12 resistance R21, R22 pull-up resistance

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04B 10/26 10/28 F term (reference) 5F049 MA01 NA17 NA19 NB01 RA07 RA08 UA13 5K002 AA01 AA03 EA04

Claims (4)

[Claims] 1. An optical communication circuit chip for converting an electric signal into an optical signal for communication, comprising a shutdown circuit for cutting off power supply to an internal circuit in response to a shutdown signal inputted from the outside. Optical communication circuit chip. 2. A bias circuit for supplying power to the internal circuit comprises a first MOS transistor for supplying a constant current to each internal circuit, and the shutdown circuit comprises the first MOS transistor. Second to control the gate of the
And a second MOS transistor in response to the shutdown signal.
The optical communication circuit chip according to claim 1, comprising a control circuit for driving a transistor. 3. The optical communication circuit chip according to claim 1, wherein the output stage circuit is composed of a MOS transistor. 4. An electronic device comprising the optical communication circuit chip according to claim 1. Description: