JP2004134530A - Level shifter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shifter circuit for reducing the manufacturing cost by preventing breakdown of the junction between the gate oxidation layer and the drain junction face. <P>SOLUTION: The level shifter circuit includes at least one or more complementary metal oxide film semiconductor transistors formed on p-type substrate and provided with a p-type metal oxide film semiconductor transistor and an n-type metal oxide film semiconductor transistor. The n-type metal oxide film semiconductor 60 is composed of a gate 62, a drain 66 provided with an n-type well 70 formed on the p-type substrate and a first N+ doping region formed in the n-type well and formed adjacent to the n-type well, and a source 64 having a second N+ doping region formed on the p-type substrate. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a potential shift circuit, and more particularly to a potential shift circuit that can prevent a gate oxide layer from breaking down and a drain junction surface from occurring.
[0002]
[Prior art]
In metal oxide semiconductor transistors (MOS), the quality of the gate oxide layer directly affects the operating characteristics of the entire transistor. For example, the distribution of charge in the oxide layer affects the threshold voltage of the transistor, and the presence of the charge reduces the breakdown voltage of the oxide layer.
[0003]
FIG. 1 discloses a charge distribution in an oxide layer of a conventional metal oxide semiconductor transistor 10. The metal oxide semiconductor transistor 10 includes a metal layer 11 serving as a gate, an oxide layer 12, and a substrate 13. Generally, the types of charges in the oxide layer are classified into interface trap charges 14, oxide layer fixed charges 16, oxide layer trap charges 18, and movable charges 20.
[0004]
The interface trap charge 14 disclosed in FIG. 1 is mainly formed at a junction between the oxide layer 12 and the substrate 13. That is, since the crystal lattice at the junction of the oxide layer 12 and the substrate 13 is not connected, the crystal lattice has a defect. Therefore, in the silicon atoms in the substrate 13 and the silicon dioxide molecules in the oxide layer 11, a chain of silicon and silicon is formed. Then, the chain of silicon and oxygen is broken, and the interface and the wrap charge 14 are generated.
[0005]
The oxide layer fixed charge 16 disclosed in FIG. 1 is mainly distributed at a position close to the junction between the oxide layer 11 and the substrate 13. The oxide layer fixed charge 15 is a positive charge and does not disappear by charging and discharging. This occurs because if the oxidation is suddenly stopped in the course of the oxidation, a large amount of silicon ions present at the junction between the oxide layer 12 and the substrate 13 cannot cause an oxidation reaction with oxygen molecules and remain in the oxide layer 12. It depends.
[0006]
The oxide layer trap charge 18 disclosed in FIG. 1 is distributed in the oxide layer 12 and is mainly generated by a structural defect of the oxide layer 12 itself. Become.
[0007]
The movable charge 20 is one in which impurities such as metal ions such as sodium ions and potassium ions move freely in the oxide layer 12 mainly in the manufacturing process.
[0008]
FIG. 2 discloses the structure of the metal oxide semiconductor transistor 10 of FIG. As shown, the metal oxide semiconductor transistor 10 includes an n-type metal oxide semiconductor (NMOS) transistor 22 and a p-type metal oxide semiconductor (PMOS) transistor 24. The n-type metal oxide semiconductor transistor 22 includes a gate 26 made of metal, a source 28 as an n-type doping region, a drain 30 as an n-type doping region, and an oxide layer 31. The p-type metal oxide semiconductor transistor 24 includes a gate 32 made of metal, a source 34 that is a p-type doping region, a drain 36 that is a doping region that is a p-type doping region, and an oxide layer 37. .
[0009]
Further, the n-type metal oxide film transistor 22 and the p-type metal oxide film transistor 24 are formed on a p-type substrate 38, and the p-type metal oxide film semiconductor 24 separately forms an n-type well 40 adjacent to the p-type substrate 38. The source 34 and the drain 36 are isolated from the p-type substrate 38 by the n-type well 40, and a channel is formed through the n-type well 40 when a current is conducted to the p-type metal oxide semiconductor transistor 24.
[0010]
In the n-type metal oxide semiconductor transistor 22, when a voltage difference between the gate 26 and the drain 30 is larger than a predetermined value, a covalent bond in the semiconductor material is broken by an external electric field. In addition, since the oxide layer 31 itself also includes a plurality of electric charges, the disturbance of the electrons occurs in the oxide layer 31 under the influence of such an external electric field, and the number of electrons contained in the oxide layer 31 increases rapidly. The breakdown of the layer 31 occurs, destroying the characteristics of the n-type metal oxide semiconductor 22 and losing its effectiveness.
[0011]
Similarly, in the p-type metal oxide semiconductor transistor 24, when the voltage difference between the gate 32 and the drain 36 exceeds a predetermined value, the covalent bond in the semiconductor material is broken by an external electric field. In addition, since the oxide layer 37 itself also includes a plurality of charges, when affected by such an external electric field, disturbance of electrons occurs in the oxide layer 37, and the number of electrons contained in the oxide layer 37 increases rapidly. Then, the breakdown of the oxide layer 31 occurs, and the characteristics of the p-type metal oxide semiconductor 24 are destroyed, losing its effectiveness.
[0012]
FIG. 3 discloses a conventional level shift circuit 50. As shown, the level shift circuit 50 includes a plurality of metal oxide semiconductor transistors 52, 54, 56, 58, wherein the metal oxide semiconductor transistors 52, 56 are p-type metal oxide semiconductor transistors, The semiconductor transistors 54 and 58 are n-type metal oxide semiconductor transistors. The voltage Vdd is connected to the gate of the metal oxide semiconductor transistor 54, the voltage Vn is connected to the sources of the metal oxide semiconductor transistors 52 and 56, and the high level voltage value of the input voltage Vin is Vdd. The level voltage value is the ground voltage (0 V). For example, if Vn and Vdd are 10V and 3.3V, respectively, and the breakdown voltage of the metal oxide semiconductor transistors 52, 54, 56, 58 is 10V, the input voltage Vin is changed to a high level voltage (3.3V). Then, the metal oxide semiconductor transistor 58 is turned on, and the transistor 54 is turned off. Therefore, the voltage at the end point B approaches the ground voltage, and the metal oxide semiconductor transistor 52 becomes conductive. At the same time, the voltage at the end point A approaches 10 V, and in this case, the metal oxide semiconductor transistor 56 is turned off. Therefore, the output voltage Vout approaches the ground voltage. The metal oxide semiconductor transistors 52 and 58 are conducting, but the reverse bias between the drain and the gate approaches 10V.
[0013]
As described above, when the reverse bias exceeds the breakdown voltage of the metal oxide semiconductor transistors 52 and 58, the breakdown of the gate oxide layer occurs and the characteristics of the level shift circuit 50 are destroyed. Similarly, when the input voltage Vin is at a low level (0 V), the metal oxide semiconductor transistor 58 is turned off, the metal oxide semiconductor transistor 54 is turned on, the voltage at the end point A approaches 0 V, and at the same time, the metal oxide semiconductor transistor is turned off. The film semiconductor transistor 56 conducts, and the voltage at the end point B approaches 10V. In this case, the metal oxide semiconductor transistor 52 is turned off. Therefore, the output voltage Vout approaches 10V. The metal oxide semiconductor transistors 54 and 56 are turned on, except that the bias between the drain and the gate approaches 10V.
[0014]
As described above, when the bias exceeds the breakdown voltage of the metal oxide semiconductor transistors 54 and 56, the corresponding oxide layer breaks down, generating a large amount of breakdown current and destroying the characteristics of the level shift circuit 50.
[0015]
In order to prevent the breakdown of the oxide layers of the metal oxide semiconductor transistors 52, 54, 56 and 58 when the oxide layers of the metal oxide semiconductor transistors 52, 54, 56 and 58 are at a high voltage difference, the level shift circuit 50 operates at the level of the voltage Vn ( For example, the metal oxide semiconductor transistors 52, 54, 56, and 58 must be operated normally by controlling 5 V). If a general manufacturing process of a metal oxide semiconductor transistor is applied to manufacture the metal oxide semiconductor transistors 52, 54, 56, and 58, the gate oxide layer itself has a relatively low break voltage due to charge doping. In other words, if the level shift circuit 50 is further operated at a high voltage (Vn), the level shift circuit 50 becomes unstable under the influence of the low break voltage of the metal oxide semiconductor transistors 52, 54, 56, 58. Therefore, the level shift circuit 50 cannot convert a low-level input signal into a high-level output signal having an excessively large voltage difference.
[0016]
[Problems to be solved by the present invention]
The present invention can effectively prevent the occurrence of breakdown, improve the breakdown voltage of a metal oxide semiconductor transistor by applying a general manufacturing process of a metal oxide semiconductor transistor, and reduce the manufacturing cost. It is an object of the present invention to provide a level shift circuit which can achieve the following.
[0017]
[Means for Solving the Problems]
Accordingly, the present inventor has conducted intensive studies in view of the drawbacks found in the prior art, and as a result, has formed at least a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor formed on a p-type substrate. In a level shift circuit including one or more complementary metal oxide semiconductor transistors,
The n-type metal oxide semiconductor transistor comprises: a gate;
A drain comprising an n-type well formed on the p-type substrate and a first N + doping region formed in the n-type well and formed adjacent to the n-type well;
The inventors have focused on the point that the problem can be solved by a structure including a source having a second N + doping region formed on the p-type substrate, and completed the present invention based on such findings.
[0018]
That is, as described above, by forming at least one or more complementary metal oxide semiconductor transistors on a p-type substrate and converting an input voltage to an output voltage, a level that prevents the occurrence of breakdown, which is an object of the present invention, is obtained. A shift circuit is obtained.
[0019]
Hereinafter, the present invention will be described specifically.
[0020]
The level shift circuit according to claim 1, wherein at least one or more complementary metal oxide semiconductor transistors including a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor are formed on a p-type substrate. In the level shift circuit comprising
The n-type metal oxide semiconductor transistor comprises: a gate;
A drain comprising an n-type well formed on the p-type substrate and a first N + doping region formed in the n-type well and formed adjacent to the n-type well;
A source having a second N + doping region formed on the p-type substrate;
Converts input voltage to output voltage.
[0021]
According to a second aspect of the present invention, the level shift circuit according to the first aspect includes first and second complementary metal oxide semiconductor transistors, and first and second p-type metal oxide semiconductor transistors.
In the first and second complementary metal oxide semiconductor transistors, the gates of the p-type metal oxide semiconductor transistors of the two complementary metal oxide semiconductor transistors are connected to each other to provide a reference voltage,
In the first and second p-type metal oxide semiconductor transistors, both of the sources of the p-type metal oxide semiconductor transistors are connected to power supply means,
A gate of the first p-type metal oxide semiconductor transistor is connected to a drain of the p-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor;
A gate of the second p-type metal oxide semiconductor transistor is connected to a drain of the p-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor;
A drain of the first p-type metal oxide semiconductor transistor is connected to a source of the p-type metal oxide semiconductor of the first complementary metal oxide semiconductor transistor;
The drain of the second p-type metal oxide semiconductor transistor is connected to the source of the p-type metal oxide semiconductor of the second complementary metal oxide semiconductor transistor.
[0022]
According to a third aspect of the present invention, there is provided a level shift circuit comprising: a drain connected to a source of an n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor;
A gate connected to a source of the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor, further comprising a first n-type metal oxide semiconductor transistor;
The source of the first n-type metal oxide semiconductor is grounded.
[0023]
According to a fourth aspect of the present invention, the level shift circuit is connected to the gate of the first n-type metal oxide semiconductor transistor according to the third aspect, receives the input voltage, and turns on / off the first n-type metal oxide semiconductor transistor. Further comprising an input for controlling.
[0024]
In a level shift circuit according to a fifth aspect, the gates of the n-type metal oxide semiconductor transistors of the first and second complementary metal oxide semiconductor transistors according to the fourth aspect are connected to a control voltage, and the control voltage and the control voltage are connected to each other. The conduction and non-conduction of the n-type metal oxide semiconductor transistors of the two complementary metal oxide semiconductor transistors are determined based on the input voltage.
[0025]
In the level shift circuit according to the present invention, when the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor in claim 5 is turned on, the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor is turned on. The metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor become non-conductive,
When the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor conduct,
The n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor is turned off.
[0026]
The level shift circuit according to claim 7 further includes first and second n-type metal oxide semiconductor transistors whose gates are connected to each other via the inverter according to claim 2,
A drain of the first n-type metal oxide semiconductor transistor is connected to a source of the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor;
A drain of the second n-type metal oxide semiconductor transistor is connected to a source of the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor;
The sources of the n-type metal oxide semiconductor transistors are grounded.
[0027]
The level shift circuit according to claim 8 is connected to the gate of the first n-type metal oxide semiconductor transistor according to claim 7 and receives an input voltage to input the input voltage to the first n-type metal oxide semiconductor transistor or the second n-type metal oxide semiconductor transistor. Controlling the conduction and non-conduction of the type metal oxide semiconductor transistor.
[0028]
In the level shift circuit according to the ninth aspect, the gates of the n-type metal oxide semiconductor transistors of the first and second complementary metal oxide semiconductor transistors according to the eighth aspect are connected to a control voltage, and the control voltage and The conduction and non-conduction of the n-type metal oxide semiconductor transistors of the two complementary metal oxide semiconductor transistors are determined based on the input voltage.
[0029]
According to a tenth aspect of the present invention, in the level shift circuit according to the ninth aspect, when the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor conduct, The n-type metal oxide semiconductor transistor of the two complementary metal oxide semiconductor transistors and the second n-type metal oxide semiconductor transistor become non-conductive,
When the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor and the second n-type metal oxide semiconductor transistor conduct,
The n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor become non-conductive.
[0030]
A level shift circuit according to claim 11 is provided between an n-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor of the complementary metal oxide semiconductor transistor according to claim 1, and controls the output voltage. An output terminal for outputting is further included.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention provides a gate oxide layer and a level shift circuit capable of suppressing breakdown occurring at a drain junction surface, comprising at least one or more complementary metal oxide semiconductor transistors. The complementary metal oxide semiconductor transistor includes a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor.
[0032]
In order to detail the structure and features of such a level shift circuit, a specific embodiment will be described below with reference to the drawings.
[0033]
[First Embodiment]
FIG. 4 discloses the structure of an n-type metal oxide semiconductor transistor 60 according to the present invention. As shown, the n-type metal oxide semiconductor 60 includes a gate 62 made of metal or composite crystal silicon, a source 64 that is an n-type doping region, a drain 66 that is an n-type doping region, and a p-type substrate 68. And an oxide layer 67, and an n-type well 70. The n-type well is formed between the drain 66 and the p-type substrate 68 so that the drain 66 and the p-type Isolation is performed so as not to form a junction surface, and the breakdown voltage between the p-type substrate 68 and the drain 66 is increased by the n-type well 70, so that a breakdown phenomenon occurs at the junction surface between the drain 66 and the p-type substrate 68. prevent.
[0034]
FIG. 5 discloses a level shift circuit 80 according to the present invention. As shown, the level shift circuit 80 includes a plurality of metal oxide semiconductor transistors 82, 84, 86, 88, 90, 92, 94. The metal oxide semiconductor transistors 86, 88, 90, and 92 are p-type metal oxide semiconductor transistors, and the metal oxide semiconductor transistors 82, 84, and 94 are n-type metal oxide semiconductor transistors. Here, it should be noted that the metal oxide semiconductor transistors 84 and 94 use the n-type metal oxide semiconductor transistor 60 disclosed in FIG. 4, and the metal oxide semiconductor transistor 82 is a conventional n-type metal oxide semiconductor transistor. The point is to use.
[0035]
The sources of the metal oxide semiconductor transistors 88 and 90 are connected to a voltage supply source Vn, and the metal oxide semiconductor transistors 88 and 90 are connected in a cross-coupling manner. The gates of the metal oxide semiconductor transistors 86 and 92 are connected to the reference voltage Vk, and the gates of the metal oxide semiconductor transistors 84 and 94 are connected to the voltage supply source Vdd. The high level voltage value of the input voltage Vin is Vdd, and the low level voltage value is the ground voltage (0 V).
[0036]
Hereinafter, the operation of the level shift circuit 80 will be described in detail. Suppose that the high-level voltage value Vdd of the input voltage Vin is 3.3 V, the reference voltage Vk is 3.3 V, the power supply source Vn is 10 V, and the breakdown voltage is 10 V. When the input voltage Vin is at a high level (3.3 V), the metal oxide semiconductor transistor 94 is turned off, the metal oxide semiconductor transistors 82 and 84 are turned on, and the voltage at the end point B approaches the ground voltage (0 V). . When the gates of the metal oxide semiconductor transistors 86 and 92 are connected to the reference voltage Vk (3.3 V), the metal oxide semiconductor transistor 86 is turned off, and the voltage (0 V) at the end point B is transmitted to the end point C. Will not be. When the source (end point C) voltage of the metal oxide semiconductor transistor 86 rises and exceeds the sum of the gate voltage (3.3 V) and the threshold voltage Vt, the metal oxide semiconductor transistor 86 is turned on, and the metal oxide semiconductor transistor 86 is turned on. The source voltage of the oxide semiconductor transistor 86 is gradually adjusted until it becomes lower than the sum of the gate electrode and the threshold voltage thereof. Therefore, the metal oxide semiconductor transistor 90 becomes conductive, and the voltage at the end point D approaches 10V.
[0037]
Regarding the metal oxide semiconductor transistor 90, the voltage difference between the gate and the drain approaches 6.6 V, so that breakdown does not occur. Similarly, the voltage difference between the gate and the drain of the metal oxide semiconductor transistor 88 approaches 6.6 V, so that no breakdown occurs.
[0038]
Finally, the voltage at the end point D approaches 10 V, and the voltage at the end point A approaches 10 V due to conduction of the metal oxide semiconductor transistor 92.
[0039]
As described above, in the embodiment, breakdown of the metal oxide semiconductor transistors 88 and 90 caused by transmission of the voltage 0V from the end point B to the end point C can be prevented.
[0040]
When the input voltage Vin is at a low level (0 V), the metal oxide semiconductor transistor 82 is turned off, the metal oxide semiconductor transistor 94 is turned on, and the voltage at the end point A approaches the ground voltage (0 V). By connecting the gates of the metal oxide semiconductor transistors 86 and 92 to the reference voltage Vk (3.3 V), the voltage (0 V) at the end point A is not transmitted to the end point C. When the source (end point D) voltage of the metal oxide semiconductor transistor 92 rises and exceeds the sum of the gate voltage (3.3 V) and the threshold voltage Vt, the metal oxide semiconductor transistor 92 is energized and the metal oxide semiconductor transistor 92 is turned on. The source voltage of the oxide semiconductor transistor 92 is gradually adjusted until it becomes lower than the sum of the gate electrode and the threshold voltage thereof. Therefore, the metal oxide semiconductor transistor 88 becomes conductive, and the voltage at the end point C approaches 10V.
[0041]
With respect to the metal oxide semiconductor transistor 88, the voltage difference between the gate and the drain approaches 6.6 V, so that breakdown does not occur. Similarly, the voltage difference between the gate and the drain of the metal oxide semiconductor transistor 90 approaches 6.6 V, so that no breakdown occurs.
[0042]
Finally, the voltage at the end point C approaches 10V, and the voltage at the end point B approaches 10V due to conduction of the metal oxide semiconductor transistor 86.
[0043]
As described above, in the embodiment, it is possible to prevent breakdown of the metal oxide semiconductor transistors 88 and 90 caused by transmission of the voltage 0V from the end point A to the end point D. In addition, the voltage (10 V) at the drain end point that must be received in the process of operating the metal oxide semiconductor transistors 84 and 94 is higher than the breakdown voltage at the junction. Therefore, in the embodiment, the metal oxide semiconductor transistors 84 and 94 have a high breakdown voltage characteristic by using the structure of the n-type metal oxide semiconductor transistor 60 disclosed in FIG.
[0044]
[Second embodiment]
FIG. 6 discloses a level shift circuit 100 according to the second embodiment. As shown, the level shift circuit 100 includes a plurality of metal oxide semiconductor transistors 82, 84, 86, 88, 90, 92, 94, 102 and an inverter 104. The metal oxide semiconductor transistors 86, 88, 90 and 92 are p-type metal oxide semiconductor transistors, and the metal oxide semiconductor transistors 86, 84, 94 and 102 are n-type metal oxide semiconductor transistors. Here, it should be noted that the metal oxide semiconductor transistors 84 and 94 use the n-type metal oxide semiconductor transistor 60 disclosed in FIG. 4, and the metal oxide semiconductor transistors 82 and 102 use the conventional n-type metal oxide film. The point is that a semiconductor transistor is used.
[0045]
The sources of the metal oxide semiconductor transistors 88 and 90 are connected to a voltage supply source Vn, and the metal oxide semiconductor transistors 88 and 90 are connected in a cross-coupling manner. The gates of the metal oxide semiconductor transistors 86 and 92 are connected to the reference voltage Vk, and the gates of the metal oxide semiconductor transistors 84 and 94 are connected to the voltage supply source Vdd. The high level voltage value of the input voltage Vin is Vdd, and the low level voltage value is the ground voltage (0 V). The inverter 104 is connected to the gates of the metal oxide semiconductor transistors 82 and 102.
[0046]
Hereinafter, the operation of the level shift circuit 100 will be described in detail. Suppose that the high-level voltage value Vdd of the input voltage Vin is 3.3 V, the reference voltage Vk is 3.3 V, the power supply source Vn is 10 V, and the oxide layer breakdown voltage and the junction surface breakdown voltage are , And both are 10V. When the input voltage Vin is at a low level (0 V), the metal oxide semiconductor transistors 94 and 102 are turned off, the metal oxide semiconductor transistors 82 and 84 are turned on, and the voltage at the end point B approaches the ground voltage (0 V). . By connecting the gates of the metal oxide semiconductor transistors 86 and 92 to the reference voltage Vk (3.3 V), the voltage (0 V) at the end point B is not transmitted to the end point C. When the voltage of the source end point C of the metal oxide semiconductor transistor 86 rises and exceeds the sum of the gate voltage (3.3 V) and the threshold voltage Vt, the metal oxide semiconductor transistor 86 is energized and the metal oxide semiconductor transistor 86 is turned on. The source voltage of the film semiconductor transistor 86 is gradually adjusted until it becomes lower than the sum of the gate electrode and its threshold voltage. Therefore, the metal oxide semiconductor transistor 90 becomes conductive, and the voltage at the end point D approaches 10V.
[0047]
Regarding the metal oxide semiconductor transistor 90, the voltage difference between the gate and the drain approaches 6.6 V, so that breakdown does not occur. Similarly, the voltage difference between the gate and the drain of the metal oxide semiconductor transistor 88 approaches 6.6 V, so that no breakdown occurs.
[0048]
Finally, the voltage at the end point D approaches 10 V, and the voltage at the end point A approaches 10 V due to conduction of the metal oxide semiconductor transistor 92.
[0049]
As described above, in the second embodiment, it is possible to prevent breakdown of the metal oxide semiconductor transistors 88 and 90 caused by transmission of the voltage 0V from the end point B to the end point C.
[0050]
When the input voltage Vin is at a high level (3.3 V), the metal oxide semiconductor transistor 82 is turned off, the metal oxide semiconductor transistors 94 and 102 are turned on, and the voltage at the end point A approaches the ground voltage 0V. By connecting the gates of the metal oxide semiconductor transistors 86 and 92 to the reference voltage Vk (3.3 V), the voltage (0 V) at the end point A is not transmitted to the end point C. When the source (end point D) voltage of the metal oxide semiconductor transistor 92 rises and exceeds the sum of the gate voltage (3.3 V) and the threshold voltage Vt, the metal oxide semiconductor transistor 92 conducts, The source voltage of the metal oxide semiconductor transistor 92 is gradually adjusted until it becomes lower than the sum of the gate electrode and its threshold voltage. Therefore, the metal oxide semiconductor transistor 88 becomes conductive, and the voltage at the end point C approaches 10V.
[0051]
With respect to the metal oxide semiconductor transistor 88, the voltage difference between the gate and the drain approaches 6.6 V, so that breakdown does not occur. Similarly, the voltage difference between the gate and the drain of the metal oxide semiconductor transistor 90 approaches 6.6 V, so that no breakdown occurs.
[0052]
Finally, the voltage at the end point C approaches 10V, and the voltage at the end point B approaches 10V due to conduction of the metal oxide semiconductor transistor 86.
[0053]
As described above, in the second embodiment, it is possible to prevent breakdown of the metal oxide semiconductor transistors 88 and 90 caused by transmission of the voltage 0V from the end point A to the end point D. In addition, the voltage (10 V) at the drain end point that must be received in the process of operating the metal oxide semiconductor transistors 84 and 94 is higher than the breakdown voltage at the junction. Therefore, in the second embodiment, the metal oxide semiconductor transistors 84 and 94 have high breakdown voltage characteristics by using the structure of the n-type metal oxide semiconductor transistor 60 disclosed in FIG.
[0054]
As shown in FIGS. 3, 5, and 6, the conventional level shift circuit 50 cannot smoothly switch from the low level voltage (Vdd) to the high level (Vn) due to the breakdown. However, when the level shift circuit 50 is a primary circuit and the level shift circuit 80 or the level shift circuit 100 is a secondary circuit, the output voltage of the level shift circuit 50 is changed to the input voltage of the level shift circuit 80 or the input voltage of the level shift circuit 100. As a further conversion can be made. For example, when the high level of the input voltage Vin of the level shift circuit 50 is 3.3 V, the low level is the ground voltage, and the power supply source Vn is 5 V, the output voltage Vout is 5 V or 0 V, and the gate is The voltage difference between the gate and the drain is lower than the breakdown voltage. Next, the output voltage Vout of the level shift circuit 50 is used as the input voltage Vin of the next level shift circuit 80 or the level shift circuit 100 to perform a level conversion operation.
[0055]
It should be noted that the low level Vdd of the secondary circuit is 5 V, the high level of the output voltage Vout of the level shift circuit 80 or the level shift circuit 100 is 10 V, and the low level is the ground voltage (0 V). However, the required level switching can be achieved, and the voltage across the gate and drain of the transistor can be reduced, and such a setting also belongs to the scope of the present invention. .
[0056]
The level shift circuits 80 and 100 according to the present invention control the conduction and non-conduction of the metal oxide semiconductor transistors 86 and 92 by the reference voltage Vk so that the ground voltage is increased via the metal oxide semiconductor transistors 86 and 92. It is possible to prevent a phenomenon that an oxide layer is broken down by being transmitted to the gates of the semiconductor transistors 88 and 90. Further, in the manufacturing process of a general metal oxide semiconductor transistor, the flake-down voltage of the metal oxide semiconductor transistors 84 and 94 in the level shift circuits 80 and 100 is reduced by implanting an n-type well structure between the drain and the substrate. In other words, it is possible to prevent the level shift circuits 80 and 100 from receiving a high voltage difference between the drain and the substrate to cause a breakdown. Further, since the step of implanting the n-type well structure does not require an extra special manufacturing step, it can be completed by applying a general manufacturing step of a metal oxide semiconductor transistor. Not only can the breakdown voltage be improved, but also lower costs in the manufacturing process can be achieved.
[0057]
The above is a preferred embodiment of the present invention, and does not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made in the spirit of the present invention and which have an equivalent effect on the present invention, fall within the scope of the claims of the present invention. .
[0058]
【The invention's effect】
The level shift circuit according to the present invention can effectively prevent the occurrence of breakdown at the gate oxide layer and the drain junction surface of the transistor, and applies a general metal oxide semiconductor transistor manufacturing process to its manufacturing process. In order to improve the breakdown voltage of the metal oxide semiconductor transistor, the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram concerning charges distributed in an oxide layer of a conventional metal oxide semiconductor transistor.
FIG. 2 is an explanatory diagram illustrating a structure of the metal oxide semiconductor transistor disclosed in FIG.
FIG. 3 is an explanatory diagram showing a conventional level shift circuit.
FIG. 4 is an explanatory diagram showing a structure of an n-type metal oxide semiconductor transistor according to the present invention.
FIG. 5 is an explanatory diagram showing a level shift circuit according to the first embodiment.
FIG. 6 is an explanatory diagram showing a level shift circuit according to a second embodiment.
[Explanation of symbols]
10, 52, 54, 56, 58, 82, 84, 86, 88, 90, 92, 94, 102 Metal oxide semiconductor transistors
11 Metal layer
12, 31, 37, 67 oxide layer
13, 38, 68 substrates
14 Interface trap charge
16 Oxide layer fixed charge
18 Oxide trap charge
20 mobile charge
22,60 n-type metal oxide semiconductor transistor
24 p-type metal oxide semiconductor transistor
26, 32, 62 gate
28, 34, 64 sauces
30, 36, 66 drain
40, 70 n-type wells
50, 80, 100 level shift circuit
104 inverter

Claims (11)

A level shift circuit formed on a p-type substrate and including at least one or more complementary metal oxide semiconductor transistors including a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor,
The n-type metal oxide semiconductor transistor comprises: a gate;
A drain comprising an n-type well formed on the p-type substrate and a first N + doping region formed in the n-type well and formed adjacent to the n-type well;
A source having a second N + doping region formed on the p-type substrate;
A level shift circuit for converting an input voltage to an output voltage. The level shift circuit includes first and second complementary metal oxide semiconductor transistors, and first and second p-type metal oxide semiconductor transistors,
In the first and second complementary metal oxide semiconductor transistors, the gates of the p-type metal oxide semiconductor transistors of the two complementary metal oxide semiconductor transistors are connected to each other to provide a reference voltage,
In the first and second p-type metal oxide semiconductor transistors, both of the sources of the p-type metal oxide semiconductor transistors are connected to power supply means,
A gate of the first p-type metal oxide semiconductor transistor is connected to a drain of the p-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor;
A gate of the second p-type metal oxide semiconductor transistor is connected to a drain of the p-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor;
A drain of the first p-type metal oxide semiconductor transistor is connected to a source of the p-type metal oxide semiconductor of the first complementary metal oxide semiconductor transistor;
2. The level shift circuit according to claim 1, wherein the drain of the second p-type metal oxide semiconductor transistor is connected to the source of the p-type metal oxide semiconductor of the second complementary metal oxide semiconductor transistor. A drain connected to a source of the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor;
A gate connected to a source of the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor, further comprising a first n-type metal oxide semiconductor transistor;
3. The level shift circuit according to claim 2, wherein a source of said first n-type metal oxide semiconductor is grounded. The semiconductor device further includes an input terminal connected to a gate of the first n-type metal oxide semiconductor transistor, for inputting the input voltage to control conduction / non-conduction of the first n-type metal oxide semiconductor transistor. The level shift circuit according to claim 3, wherein The gates of the n-type metal oxide semiconductor transistors of the first and second complementary metal oxide semiconductor transistors are connected to a control voltage, and the two complementary metal oxide films are based on the control voltage and the input voltage. 5. The level shift circuit according to claim 4, wherein conduction and non-conduction of the n-type metal oxide semiconductor transistor of the semiconductor transistor are determined. When the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor conducts, the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor Non-conduction with the transistor,
When the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor conduct,
6. The level shift circuit according to claim 5, wherein an n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor is turned off. First and second n-type metal oxide semiconductor transistors having gates connected to each other via an inverter;
A drain of the first n-type metal oxide semiconductor transistor is connected to a source of the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor;
A drain of the second n-type metal oxide semiconductor transistor is connected to a source of the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor;
3. The level shift circuit according to claim 2, wherein the sources of the n-type metal oxide semiconductor transistors are grounded. It is connected to the gate of the first n-type metal oxide semiconductor transistor and receives an input voltage to control conduction / non-conduction of the first n-type metal oxide semiconductor transistor or the second n-type metal oxide semiconductor transistor. The level shift circuit according to claim 7, wherein: The gates of the n-type metal oxide semiconductor transistors of the first and second complementary metal oxide semiconductor transistors are connected to a control voltage, and the two complementary metal oxide films are based on the control voltage and the input voltage. 9. The level shift circuit according to claim 8, wherein conduction and non-conduction of an n-type metal oxide semiconductor transistor of the semiconductor transistor are determined. An n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor; and an n-type metal oxide film of the second complementary metal oxide semiconductor transistor when the first n-type metal oxide semiconductor transistor conducts. The semiconductor transistor and the second n-type metal oxide semiconductor transistor become non-conductive,
When the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor and the second n-type metal oxide semiconductor transistor conduct,
10. The level shift circuit according to claim 9, wherein the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor are non-conductive. The output terminal provided between the n-type metal oxide semiconductor transistor of the complementary metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor and configured to output the output voltage. 2. The level shift circuit according to 1.

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