JP4667928B2 - Level conversion circuit and semiconductor device - Google Patents

Description

  The present invention relates to a level conversion circuit used for connection between circuits having different power supply voltages and a semiconductor device including the level conversion circuit.

  When connecting between circuits with different power supply voltages, for example, when outputting a signal from a circuit on the low power supply voltage side to an input of the circuit on the high power supply voltage side, A level conversion circuit that converts an amplitude level into an input amplitude level in a circuit on the high power supply voltage side is used.

An example of the level conversion circuit is the level conversion circuit shown in FIG. This level conversion circuit includes two sets of NMOS transistors and PMOS transistors connected in series between paths of a high power supply voltage and a ground potential. An input signal and an inverted input signal are respectively connected to the gates of the NMOS transistors of each set, and an inverted output signal and an output signal are taken out from a connection point where the NMOS transistor and the PMOS transistor of each set are connected. The gates of the PMOS transistors in each set are cross-coupled to the other set of connection points. For example, when one set of NMOS transistors is turned on by an input signal, the other set of PMOS transistors is turned on by cross-couple connection. At this time, since the other set of NMOS transistors is non-conductive, a signal for setting the high power supply voltage to a high level is output from the connection point of the other set.
In this way, in this level conversion circuit, the output signal and the inverted output signal converted into the amplitude level of the input of the circuit on the high power supply voltage side according to the input signal and the inverted input signal from the circuit of the low power supply voltage are received. Is output.

  This type of level conversion circuit is increasingly used as an interface circuit with an external circuit in a semiconductor integrated device. With the recent reduction in power supply voltage of semiconductor integrated devices, in the circuit shown in FIG. 2 of Patent Document 1 described above, the output from the semiconductor integrated device side may be at a voltage level that is insufficient to conduct the NMOS transistor. It came to occur. In this case, the low level potential in the output signal does not drop to the ground potential, or the transition time of the output signal becomes long.

In order to solve such a problem, a level shifter circuit shown in FIG. 1 of Patent Document 1 has been proposed. This level shifter circuit includes, in addition to the circuit shown in FIG. 1 of Patent Document 1, a first diode whose anode is connected to the back gate of the first NMOS transistor and whose cathode is connected to the output signal, and whose anode is the second NMOS transistor. And a second diode connected to the back gate and having a cathode connected to the inverted output signal.
For example, when the input signal transitions from the low level and the inverted input signal to the high level, the first NMOS transistor is turned on and the drain potential decreases when the input signal transitions to the high level and the inverted input signal to the low level. start. As a result, the second PMOS transistor connected in a cross-coupled state is subjected to conduction control, and the potential of the output signal starts to rise. Then, since the bias of the first diode is reversed, a parasitic capacitance is generated. Further, due to the capacitive coupling due to the parasitic capacitance, the back gate bias voltage of the first NMOS transistor rises and the threshold voltage of the first NMOS transistor falls. When the threshold voltage decreases, the conduction conductance of the first NMOS transistor increases and the drain potential further decreases. By such a series of feedback, the output voltage transitions quickly, and eventually transitions to a predetermined level. For this reason, even when the input signal and the inverted input signal do not have sufficient amplitude levels to control the conduction of the first NMOS transistor in the normal time when the back gate bias voltage is the ground potential, the potential of the output signal Can be changed as soon as possible, the state of the output signal can be changed quickly and reliably.

In addition to the circuit shown in FIG. 13 of Patent Document 1, the level shift circuit disclosed in FIG. 1 of Patent Document 2 has a source and a drain connected to the input signal, the first NMOS transistor, and a gate connected to the output signal, respectively. The third PMOS transistor includes a fourth PMOS transistor having a source and a drain connected to an input signal, a second NMOS transistor, and a gate connected to an inverted output signal, respectively.
For example, when the input signal is at a low level and the inverted input signal is at a high level, the third PMOS transistor is turned on and the fourth PMOS transistor is turned off. Next, when the input signal transitions to the high level and the inverted input signal transitions to the low level, the back gate bias voltage of the first NMOS transistor also rises according to the input signal, and the threshold value for the conduction control of the first NMOS transistor falls. Therefore, even when the input signal and the inverted input signal do not have an amplitude level sufficient to control the conduction of the first NMOS transistor in the normal time when the back gate bias voltage is the ground potential, The state of the output signal can be reliably shifted.
JP 2003-143004 A (FIGS. 1 and 2) Japanese Patent Laying-Open No. 2003-283326 (FIG. 1)

  However, in the level shift circuit of FIG. 1 of Patent Document 1, for example, when the high level voltage of the input signal is not sufficient to turn on the NMOS transistor, the back gate bias voltage of the first NMOS transistor is changed. This is a problem because the state of the output signal cannot be changed.

On the other hand, in the level shift circuit of FIG. 1 of Patent Document 2, for example, when the input signal transitions to a high level, the back gate voltage of the first NMOS transistor also increases at the same time. it can. However, when a voltage is applied to the back gate of the first NMOS transistor, the path from the back gate to the source is connected in the forward direction, and a large forward current flows. That is, a large current flows from the input signal and the inverted input signal, which increases current consumption and affects the circuit side that outputs the input signal and the inverted input signal.
In the level shift circuits of Patent Document 1 and Patent Document 2, since the back gate bias voltage is changed according to the output signal, the output signal is unstable (for example, an intermediate potential or a high impedance state). In the case where the back gate bias voltage is not changed normally, the back gate bias voltage may not be changed normally.

  The present invention has been made to solve at least one of the above-mentioned problems of the background art, and can quickly and reliably convert amplitude levels between circuits having different power supply voltages, and operates with low current consumption. An object of the present invention is to provide a level converting circuit and a semiconductor device in which the level converting circuit is configured.

In order to achieve the above object, a solution means according to the present invention is a level conversion circuit used for connection between circuits having different power supply voltages, and outputs a first input signal and a first input signal which are output from one circuit and are inverted from each other. A level conversion circuit that receives two input signals and outputs a first output signal and a second output signal whose amplitude levels are converted based on the input level of the other circuit, wherein the first input signal is converted to a high level. In response to the transition, the first NMOS transistor that conducts and controls the path from the output point of the first output signal to the ground point, and the output of the second output signal in response to the transition of the second input signal to the high level. A second NMOS transistor that conducts and controls a path from a point to a ground point, and a transition to the high level of the first input signal due to capacitive coupling. A level conversion circuit comprising: a first capacitor for transmitting a back gate bias voltage; and a second capacitor for transmitting a transition of the second input signal to a high level to the back gate bias voltage of the second NMOS transistor by capacitive coupling. It is.
Further, when the back gate bias voltage of the first NMOS transistor or the second MOS transistor after being transmitted by capacitive coupling of the first capacitor or the second capacitor is the first voltage, the first input signal is changed according to the transition to the low level. A first switch unit that conducts the back gate bias voltage of the first NMOS transistor to a second voltage lower than the first voltage, and the back of the second NMOS transistor according to the transition of the second input signal to a low level. And a second switch unit that conducts the gate bias voltage to the second voltage.

  The level conversion circuit of the present invention includes a first capacitor that transmits a transition of a first input signal to a high level to the back gate bias voltage of the first NMOS transistor by capacitive coupling, and a high level of the second input signal by capacitive coupling. And a second capacitor for transmitting the transition to the back gate bias voltage of the second NMOS transistor. For example, when the first input signal transitions to a high level, the back gate bias voltage of the first NMOS transistor increases due to capacitive coupling, and the threshold value of the first NMOS transistor decreases. That is, since feedback of the output signal is not used, the back gate bias voltage is increased only in response to the transition of the first input signal to the high level. Therefore, even when the first input signal does not have an amplitude level sufficient to control the conduction of the first NMOS transistor at the normal time when the back gate bias voltage is the ground potential, it can be performed quickly and reliably. The state of the output signal can be transitioned to.

  In the level conversion circuit of the present invention, the first input signal and the second input signal are transmitted to the back gate bias voltages of the first NMOS transistor and the second NMOS transistor by capacitive coupling of the first capacitor and the second capacitor. . For this reason, the stationary current from the first input signal and the second input signal does not flow. Therefore, a level conversion circuit that consumes less power and does not place a burden on the output circuit of the first input signal and the second input signal can be obtained.

  As the first (second) capacitor, any capacitor can be used as long as the transition to the high level of the first (second) input signal can be transmitted to the back gate bias voltage of the first (second) NMOS transistor by capacitive coupling. May be. For example, specifically, a normal capacitive element or a diode connected in the reverse direction can be used. In addition, when this level conversion circuit is configured by an integrated circuit, for the gate capacitance obtained through the gate oxide film of the MOS transistor and the parasitic diode generated by the junction of the p-type and n-type diffusion layers, The first (second) capacitor can also be configured using a diffusion capacitance obtained by applying a reverse bias voltage.

  By applying the present invention, it is possible to provide a level conversion circuit that performs level conversion between circuits having different power supply voltages quickly and reliably and operates with low power consumption, and a semiconductor device including the level conversion circuit. it can.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a level conversion circuit according to an embodiment of the present invention will be described below in detail with reference to FIGS.

(First embodiment)
The level conversion circuit 100 according to the first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the level conversion circuit 100 includes first and second PMOS transistors TP1 and TP2, first to fourth NMOS transistors TN1 to TN4, and first and second capacitors C1 and C2. FIG. 1 also includes inverters INV1 and INV2 that are driven by a first power source that is a low-voltage power source (not shown). The inverter INV1 logically inverts the first input signal VI and outputs a second input signal VIX. The inverter INV2 further inverts the logic of the second input signal VIX and outputs an input signal VI2 having the same phase as the first input signal VI.
The third NMOS transistor TN3 constitutes the first switch part in claim 2, and the fourth NMOS transistor TN4 constitutes the second switch part in claim 2.

The first NMOS transistor TN1 has a gate connected to the input signal VI2. The first NMOS transistor TN1 and the first PMOS transistor TP1 are connected in series between a second power source VD2 that is a high voltage power source and a ground point GND. A first output signal V1O is taken out from a connection point between the first PMOS transistor TP1 and the first NMOS transistor TN1.
On the other hand, the gate of the second NMOS transistor TN2 is connected to the second input signal VIX. The second NMOS transistor TN2 and the second PMOS transistor TP2 are also connected in series between the second power supply VD2 and the ground point GND. Further, the second output signal V1OX is extracted from the connection point between the second NMOS transistor TN2 and the second PMOS transistor TP2.
The first output signal V1O is connected to the gate of the second PMOS transistor TP2, and the second output signal V1OX is connected to the gate of the first PMOS transistor TP1, thereby forming a so-called cross-couple connection.

  On the other hand, the back gate of the first NMOS transistor TN1 is connected to the first capacitor C1 whose other end is connected to the input signal VI2 and the drain of the third NMOS transistor TN3. The second NMOS transistor TN2, the second capacitor C2, and the fourth NMOS transistor TN4 are also connected in the same relationship. Among these, the third NMOS transistor TN3 has a gate connected to the second input signal VIX and a source connected to the ground point GND. The fourth NMOS transistor TN4 has a gate connected to the first input signal VI and a source connected to the ground point GND.

  Next, the operation of the level conversion circuit 100 will be described with reference to FIG. FIG. 2 shows operation waveforms of respective parts in the period T11 in which the first input signal VI is at a high level and the period T12 in which the first input signal VI is at a low level.

In the period T11, when the first input signal VI transitions to a high level, the second input signal VIX transitions to a low level. Furthermore, when the second input signal VIX transitions to a low label, the input signal VI2 transitions to a high level. That is, a change in the second input signal VIX causes a delay of the inverter INV1 with respect to a change in the first input signal VI, and a delay of the inverter INV2 occurs in the input signal VI2 with respect to the second input signal VIX.
Here, when the second input signal VIX transitions to a low level, the third NMOS transistor TN3 whose gate is connected to the second input signal VIX is turned off. Next, when the input signal VI2 transits to a high level, the back gate voltage VBG11 rises to the peak voltage Vcp due to capacitive coupling of the first capacitor C1. At the same time, the first NMOS transistor TN1 transitions to a conductive state. Further, since a forward current flows from the back gate to the source of the first NMOS transistor TN1, the back gate voltage VBG11 subsequently changes to the forward voltage Vth. Such a change in the back gate voltage VBG11 causes a back gate bias effect in the first NMOS transistor TN1, lowers the threshold voltage, and accelerates the transition to the conductive state.
Further, since the third NMOS transistor TN3 is controlled to be non-conductive prior to the capacitive coupling of the first capacitor C1, the voltage of the back gate voltage VBG11 can be reliably increased.

  As the first NMOS transistor TN1 changes to the conductive state, the potential of the first output signal V1O changes to the low voltage side, and thus the second PMOS transistor TP2 changes to the conductive state. Further, the second NMOS transistor TN2 transitions to a non-conductive state because the second input signal VIX is input to the gate. As a result, the potential of the second output signal V1OX changes toward the potential of the second power supply VD2. In addition, since the first PMOS transistor TP1 to which the second output signal V1OX is input to the gate transitions to the non-conductive state, the potential of the first output signal V1O quickly transitions toward the potential of the ground point GND. .

  The fourth NMOS transistor TN4, to which the first input signal VI is input to the gate, is controlled for conduction. Thereby, in the second NMOS transistor TN2, the back gate voltage VBG12 becomes the potential of the ground point GND, and the threshold voltage becomes a normal state, so that the conductance in the non-conduction state is lowered. Therefore, in the level conversion circuit 100, it is possible to suppress a through current through the second PMOS transistor TP2 and the second NMOS transistor TN2.

In the period T12, the first input signal VI transitions to a low level, and the second input signal VIX transitions to a high level. When the second input signal VIX transitions to a high level, the input signal VI2 transitions to a low level. As in the case of the period T11, when the first input signal VI transitions to a low level, the fourth NMOS transistor TN4 whose gate is connected to the first input signal VI is turned off. Next, when the second input signal VIX transitions to a high level, the back gate voltage VBG12 rises to the peak voltage Vcp due to capacitive coupling of the second capacitor C2, and transitions to the forward voltage Vth. At the same time, the second NMOS transistor TN2 transitions to a conductive state. Also in the second NMOS transistor TN2, a back gate bias effect occurs, the threshold voltage decreases, and the transition to the conductive state is performed at high speed. After that, as in the case of the period T11, the potential of the first output signal V1O transitions toward the second power supply VD2 due to the action of the cross-couple connection, and the potential of the second output signal V1OX changes from the ground point GND. It will make a rapid transition toward the potential.
Similarly to the period T11, the fourth NMOS transistor TN4 is controlled to be non-conductive prior to the capacitive coupling of the second capacitor C2, so that the voltage of the back gate voltage VBG12 can be reliably increased.

  Similarly to the period T11, the back gate voltage VBG11 of the first NMOS transistor TN1 is set to the potential of the ground point GND by the third NMOS transistor TN3. Therefore, in the level conversion circuit 100, a through current through the first PMOS transistor TP1 and the first NMOS transistor TN1 can be suppressed.

As described above, in the level conversion circuit 100 according to the first embodiment, the back gate voltages VBG11 and VBG12 are changed in accordance with changes in the first input signal VI and the second input signal VIX, so that the circuit on the low power supply voltage side The conversion from the output amplitude level to the input amplitude level in the circuit on the high power supply voltage side is performed quickly and reliably.
In addition, the transition of the first input signal VI and the second input signal VIX is transmitted to the first NMOS transistor TN1 and the second NMOS transistor TN2 using the capacitive coupling of the first capacitor C1 and the second capacitor C2. For this reason, since a steady current from the first input signal VI and the second input signal VIX does not flow, the operation can be performed with low power consumption, and the circuit that generates the first input signal VI and the second input signal VIX is provided. There is no risk of adverse effects.

  3A and 3B show the layout structure of the semiconductor device 100A in which the level conversion circuit 100 according to the first embodiment is configured. Here, (A) is a plan view, and (B) is an AA cross-sectional schematic diagram of (A).

In the semiconductor device 100A in which the level conversion circuit 100 is configured, an N well NW composed of an N− layer is formed on a P substrate PS. The N well NW includes a first P well PW1 composed of P− layers separated from each other and the same. A second P well PW2 made of a P− layer is formed. That is, the P substrate PS, the N well NW, and the first P well PW1 or the second P well PW2 form a triple well structure.
The P substrate PS includes a third NMOS transistor TN3 and a fourth NMOS transistor TN4, and the N well NW includes a first PMOS transistor TP1 and a second PMOS transistor TP2.

  Of the P wells formed in the N well NW, one first P well PW1 includes a first NMOS transistor TN1 and a first capacitor C1 (NMOS transistor TNC1).

  The first NMOS transistor TN1 includes a P-layer first P well PW1 as a back gate, two N + regions n1 and n2 as drains and sources, and a gate oxide film GST above the first P well PW1. Polysilicon PT formed in this way is used as a gate. Among these, the second output signal V1OX is connected to the drain, the ground point GND is connected to the source, and the first input signal VI is connected to the gate via an aluminum wiring via a contact.

  The NMOS transistor TNC1 has a first P well PW1 as a back gate, two N + regions n3 and n4 as a drain and a source, respectively, and a polysilicon PT formed above the first P well PW1 via a gate oxide film GST. The gate. Among these, the drain of the third NMOS transistor TN3 is connected to the drain, source, and back gate by an aluminum wiring through a contact. That is, the NMOS transistor TNC1 includes a first capacitor C1 having one end of the first P well PW1 and the other end of a polysilicon PC formed via the gate oxide film GSC above the first P well PW1. Yes.

  In the semiconductor device 100A in which the level conversion circuit 100 is configured, one end of the first capacitor C1 and the back gate of the first NMOS transistor TN1 are formed in the same first P well PW1. Therefore, no contact or wiring for connecting them is required. The same applies to the second capacitor C2 and the second NMOS transistor TN2. Therefore, in the semiconductor device 100A in which the level conversion circuit 100 is configured, the layout area can be reduced as compared with the case where the capacitor and the NMOS transistor are formed on different substrates.

  In the present embodiment, the NMOS transistor TNC1 and the NMOS transistor TNC2 are formed, and the parasitic capacitance generated between the back gate and the gate is used as the first capacitor C1 and the second capacitor C2. The present invention is not limited to this layout structure. For example, in the first P well PW1, the formation of the N + regions n3 and n4 is omitted, and the polysilicon PC formed via the gate oxide film GSC is formed above the first P well PW1 with the first P well PW1 as one end. A first capacitor C1 serving as the other end may be formed.

(Second Embodiment)
Next, a level conversion circuit 200 according to the second embodiment will be described with reference to FIGS.
The level converting circuit 200 is different only in that the first diode D1 and the second diode D2 are used instead of the first capacitor C1 and the second capacitor C2 in the level converting circuit 100. Accordingly, the following description will be focused on different parts, and description of similar parts will be simplified or omitted.

  As shown in FIG. 4, the level conversion circuit 200 includes first and second PMOS transistors TP1 and TP2 and first to fourth NMOS transistors TN1 to TN4. These are connected to each other in the same manner as the level conversion circuit 100. The same applies to the inverter INV shown in FIG. 4 where the first input signal VI is logically inverted and the second input signal VIX is output.

  Instead of the first capacitor C1 in the level conversion circuit 100, a first diode D1 whose other end is connected to the first input signal VI is connected to the back gate of the first NMOS transistor TN1. Accordingly, when the first input signal VI transitions from the low level to the high level, capacitive coupling due to the parasitic capacitance of the first diode D1 connected in the reverse direction occurs, and the potential of the back gate of the first NMOS transistor TN1 rises. Further, a second diode D2 having the other end connected to the second input signal VIX is connected to the back gate of the second NMOS transistor TN2. Accordingly, similarly, when the second input signal VIX transitions from the low level to the high level, capacitive coupling due to the parasitic capacitance of the second diode D2 connected in the reverse direction occurs, and the potential of the back gate of the second NMOS transistor TN2 is To rise.

  Next, the operation of the level conversion circuit 200 will be described with reference to FIG. FIG. 5 shows operation waveforms of the respective parts in the period T21 in which the first input signal VI is at a high level and the period T22 in which the first input signal VI is at a low level.

  In the period T21, when the first input signal VI transitions to a high level, a parasitic capacitance due to a reverse bias is generated in the first diode D1. Due to the capacitive coupling of the parasitic capacitance, the back gate voltage VBG11 of the first NMOS transistor TN1 rises to the peak voltage Vcp. Thereafter, each part operates in the same manner as in the first embodiment, and the potentials of the first output voltage V2O and the second output voltage V2OX are quickly shifted toward the ground point GND and the second power supply VD2, respectively. Become.

  Also in the level conversion circuit 200, as with the level conversion circuit 100, the back gate voltage VBG12 is set to the potential of the ground point GND by the fourth NMOS transistor TN4, and the conductance in the non-conduction state is lowered. Therefore, also in the level conversion circuit 200, it is possible to suppress a through current through the second PMOS transistor TP2 and the second NMOS transistor TN2.

  In the second NMOS transistor TN2, as the potential of the second output voltage V2OX, that is, the drain potential increases, the potential of the back gate increases due to capacitive coupling between the drain and the back gate. When the second input signal VIX transitions to a low level, the second diode D2 becomes forward biased, a current flows from the back gate toward the second input signal VIX, and together with the operation of the fourth NMOS transistor TN4 described above, the back gate The rise in the potential of is suppressed. The action of the second diode D2 is performed earlier than the conduction control of the fourth NMOS transistor TN4 that is performed in response to the transition of the second input signal VIX. For this reason, in the level conversion circuit 200, the through current from the second power supply VD2 to the ground point GND via the second PMOS transistor TP2 and the second NMOS transistor TN2 can be more reliably suppressed.

  Note that in the period T22, the first input signal VI transitions to a low level, and the second input signal VIX transitions to a high level. As a result, instead of the first diode D1, the second diode D2 performs the same operation, and thereafter the same operation is performed, so that the description thereof is omitted. That is, the potentials of the first output voltage V2O and the second output voltage V2OX quickly transition toward the second power supply VD2 and the ground point GND, respectively.

  The potential of the back gate of the first NMOS transistor TN1 is also a through current from the second power supply VD2 to the ground point GND via the first PMOS transistor TP1 and the first NMOS transistor TN1 due to the action of the third NMOS transistor TN3 and the first diode D1. This also applies to the point of more reliably suppressing.

  Note that by setting the low-level potentials of the first input signal VI and the second input signal VIX to a potential lower than the potential of the ground point GND, the potentials of the back gates of the first NMOS transistor TN1 and the second NMOS transistor TN2 are made lower. Can be.

  Next, FIGS. 6A and 6B show a layout structure of the semiconductor device 200A in which the level conversion circuit 200 according to the second embodiment is configured. Here, (A) is a plan view, and (B) is a schematic BB cross-sectional view of (A).

Similar to the semiconductor device 100A in the first embodiment, the semiconductor device 200A in which the level conversion circuit 200 is configured has a triple well structure including a P substrate PS, an N well NW, a first P well PW1, and a second P well PW2. ing.
Similarly, the third NMOS transistor TN3 and the fourth NMOS transistor TN4 are formed on the P substrate PS, and the first PMOS transistor TP1 and the second PMOS transistor TP2 are formed on the N well NW, respectively.

Of the P wells formed in the N well NW, in one of the first P wells PW1, a first diode D1 is formed together with the first NMOS transistor TN1 instead of the first capacitor C1 in the first embodiment.
Among these, the first NMOS transistor TN1 has a P-layer first P well PW1 as a back gate, two N + regions n1 and n2 respectively as a drain and a source, and the upper portion of the first P well PW1 as in the first embodiment. In addition, polysilicon PT formed through the gate oxide film GST is used as a gate.

  The first diode D1 is formed with the first P well PW1 identical to the back gate of the first NMOS transistor TN1 as the anode A and the N + region nd provided in the first P well PW1 as the cathode K. That is, the first diode D1 is formed using a parasitic diode generated by the junction of the first P well PW1 and the N + region nd. The N + region nd forming the cathode K of the first diode D1 is connected to the first input signal VI, and the first P well PW1 is connected to the drain of the third NMOS transistor TN3 via an aluminum wire via a contact. .

  The layout structure of the first NMOS transistor TN1 and the first diode D1 formed in one first P well PW1 among the P wells formed in the N well NW has been described above. However, the layout structure is formed in the other second P well PW2. Since the layout structure of the second NMOS transistor TN2 and the second diode D2 is the same, the description thereof is omitted.

In the layout structure of the semiconductor device 200A constituting the level conversion circuit 200, one end of the first diode D1 and the back gate of the first NMOS transistor TN1 are formed in the same first P well PW1. Therefore, no contact or wiring for connecting them is required. The same applies to the second diode D2 and the second NMOS transistor TN2. Further, since the first diode D1 and the second diode D2 are formed of a diffusion layer, the capacitance value per area can be increased as compared with the case where the capacitance is formed using the gate oxide film.
Therefore, in the semiconductor device 200A in which the level conversion circuit 200 is configured, when the capacitance is formed with a predetermined capacitance value, the layout area can be made smaller than when the capacitance is formed using the gate oxide film.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the first embodiment and the second embodiment, the example in which the NMOS transistor that connects the back gate bias voltage to the ground potential when the NMOS transistor is in the non-conductive state is shown, but depending on the control signal Any element that performs a switching operation may be used, and a bipolar element, a gallium arsenide element, or the like can also be used. Alternatively, it is also Rukoto forming structure by omitting the NMOS transistor for the switching.
In the first embodiment and the second embodiment, the level conversion circuit configured in the semiconductor device has been exemplified. However, the present invention is also applied to the level conversion circuit configured by individual elements.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Supplementary note 1) A level conversion circuit used for connection between circuits having different power supply voltages. The first input signal and the second input signal which are output from one circuit and are inverted from each other are input to the other circuit. A level conversion circuit that outputs a first output signal and a second output signal, the amplitude level of which is converted based on an input level, in response to a transition of the first input signal to a high level. The first NMOS transistor that controls conduction from the output point to the ground point, and the path from the output point of the second output signal to the ground point according to the transition of the second input signal to the high level. A first NMOS for transmitting a transition of the first input signal to a high level to a back gate bias voltage of the first NMOS transistor by capacitive coupling with the second NMOS transistor. A level conversion circuit comprising: a capacitor; and a second capacitor for transmitting a transition to a high level of the second input signal to a back gate bias voltage of the second NMOS transistor by capacitive coupling.
(Supplementary note 2) The level conversion circuit according to supplementary note 1, wherein a back gate bias voltage of the first NMOS transistor or the second MOS transistor after being transmitted by capacitive coupling of the first capacitor or the second capacitor A first switch unit for setting a back gate bias voltage of the first NMOS transistor to a second voltage lower than the first voltage when the first NMOS transistor is in a non-conducting state, A level conversion circuit comprising: a second switch unit that sets a back gate bias voltage of the second NMOS transistor to the second voltage when the second NMOS transistor is non-conductive.
(Supplementary Note 3) The level conversion circuit according to Supplementary Note 2, wherein the second voltage is a ground potential.
(Supplementary note 4) The level conversion circuit according to supplementary note 2, wherein the first switch unit includes a third NMOS transistor, and the second switch unit includes a fourth NMOS transistor.
(Supplementary Note 5) In the level conversion circuit according to Supplementary Note 2, prior to transmission of a transition of the first input signal to a high level by capacitive coupling with a back gate of the first NMOS transistor, the first switch unit is not turned on. A level conversion circuit in which conduction is controlled and the second switch unit is controlled to be non-conducting prior to transmission of a transition of the second input signal to a high level by capacitive coupling to the back gate of the second NMOS transistor.
(Supplementary note 6) The level conversion circuit according to supplementary note 1, wherein the first capacitor includes a first diode connected in a forward direction to a path from a back gate of the first NMOS transistor to the first input signal. The second capacitor includes a second diode connected in a forward direction to a path from the back gate of the second NMOS transistor to the second input signal.
(Supplementary note 7) The semiconductor integrated device having the level conversion circuit according to supplementary note 1, wherein one end of the first capacitor is formed in a first P well that is the same as the back gate of the first NMOS transistor, and the other end. Is formed through a gate oxide film, one end of the second capacitor is formed in the same second P well as the back gate of the second NMOS transistor, and the other end is formed through a gate oxide film. Semiconductor integrated device.
(Supplementary Note 8) In the semiconductor integrated device in which the level conversion circuit according to Supplementary Note 5 is configured, the first diode has an anode formed in the same first P well as a back gate of the first NMOS transistor, and a cathode. The second diode is formed in an n-type region provided in the first P well. The second diode has an anode formed in the same second P well portion as a back gate of the second NMOS transistor, and a cathode formed in the second P well. A semiconductor integrated device formed in an n-type region provided.

It is a circuit diagram of a first embodiment. It is a wave form diagram which shows operation | movement of 1st embodiment. It is a layout figure which shows the layout structure of 1st embodiment. (A) is a top view, (B) is a schematic diagram of an AA cross section. It is a circuit diagram of a second embodiment. It is a wave form diagram which shows operation | movement of 2nd embodiment. It is a layout figure which shows the layout structure of 2nd embodiment. (A) is a top view, (B) is a schematic diagram of a BB cross section.

100 level conversion circuit 100A (constitutes level conversion circuit 100) semiconductor device 200 level conversion circuit 200A (contains level conversion circuit 200) semiconductor device C1 first capacitor C2 second capacitor D1 first diode D2 second diode GSC, GST Gate oxide film NW N well PS P substrate PW1 First P well PW2 Second P well TN1 First NMOS transistor TN2 Second NMOS transistor TN3 Third NMOS transistor (first switch part)
TN4 Fourth NMOS transistor (second switch part)
TP1 First PMOS transistor TP2 Second PMOS transistor VBG11 Back gate voltage VBG12 Back gate voltage VD2 Second power supply

Claims (4)

This is a level conversion circuit used for connection between circuits having different power supply voltages. The first input signal and the second input signal that are output from one circuit and are inverted from each other are input and based on the input level of the other circuit. A level conversion circuit for outputting a first output signal and a second output signal whose amplitude levels have been converted,
A first NMOS transistor for controlling conduction of a path from an output point of the first output signal to a ground point in response to a transition of the first input signal to a high level;
A second NMOS transistor for controlling conduction of a path from an output point of the second output signal to a ground point in response to a transition of the second input signal to a high level;
A first capacitor for transmitting a transition to a high level of the first input signal to a back gate bias voltage of the first NMOS transistor by capacitive coupling;
A second capacitor for transmitting a transition to a high level of the second input signal to a back gate bias voltage of the second NMOS transistor by capacitive coupling;
When the back gate bias voltage of the first NMOS transistor or the second MOS transistor after being transmitted by capacitive coupling of the first capacitor or the second capacitor is a first voltage,
A first switch unit for conducting a back gate bias voltage of the first NMOS transistor to a second voltage lower than the first voltage in response to a transition of the first input signal to a low level;
A second switch unit for conducting a back gate bias voltage of the second NMOS transistor to the second voltage in response to a transition of the second input signal to a low level;
A level conversion circuit comprising: The level conversion circuit according to claim 1, wherein
The first capacitor includes a first diode connected in a forward direction to a path from a back gate of the first NMOS transistor to the first input signal;
The second capacitor is a level conversion circuit including a second diode connected in a forward direction to a path from the back gate of the second NMOS transistor to the second input signal. A semiconductor integrated device in which the level conversion circuit according to claim 1 is configured,
The first capacitor has one end formed in the same first P well as the back gate of the first NMOS transistor and the other end formed through a gate oxide film.
A semiconductor integrated device in which one end of the second capacitor is formed in the same second P well as the back gate of the second NMOS transistor, and the other end is formed through a gate oxide film. A semiconductor integrated device in which the level conversion circuit according to claim 2 is configured,
The first diode has an anode formed in the same first P well as the back gate of the first NMOS transistor, and a cathode formed in an n-type region provided in the first P well,
The semiconductor integrated device, wherein the second diode has an anode formed in a second P well portion that is the same as the back gate of the second NMOS transistor, and a cathode formed in an n-type region provided in the second P well.

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