TW530419B - Level shift circuit without junction breakdown of transistors - Google Patents

Abstract

A level shift circuit for shifting a voltage level of an input voltage includes at least a complementary metal oxide semiconductor transistor fabricated on a p-substrate. The CMOS transistor includes a PMOS transistor and an NMOS transistor. The NMOS transistor has a gate electrode, a drain electrode, and a source electrode. The drain electrode has an n-well fabricated on the p-substrate, and a first N-doped region inside the n-well. The source electrode has a second N-doped region fabricated on the p-substrate.

Description

530419 V. Description of the invention α) Field of the invention The present invention provides a potential conversion circuit, especially a potential conversion circuit without gate oxide layer collapse and without drain junction collapse. Background: In metal oxide semiconductor transistor (MOS) devices, the quality of the gate oxide layer (ox i de) will affect the operating characteristics of the entire transistor device, such as the charge in the oxide layer. The distribution not only affects the threshold voltage (Vt) of the transistor element, but also reduces the breakdown voltage of the oxide layer due to the presence of charge. Please refer to FIG. 1. FIG. 1 is a schematic diagram of the charge distribution of an oxide layer of a conventional metal oxide semiconductor transistor 10. Metal oxide semiconductor transistors 丨 0 includes a metal layer 1 1 (as a gate electrode), an oxide layer 12 and a substrate 13. Generally speaking, the types of charges in the oxide layer can be mainly divided into interface traps. Interface trapped charge (Qit) 14, fixed oxide charge (Qf) 16, oxide trapped charge (Qot) 18, and mobile charge (Qm) 20, of which The interface trapped charge 1 4 is mainly formed at the junction of the oxide layer 12 and the substrate 13, mainly the silicon (Si) atoms in the substrate 13 and the silicon dioxide (Si 〇2) molecules in the oxide layer 11 Because the lattice at the junction of the oxide layer 12 and the substrate 13

Page 5 530419 V. Description of the invention (2) (lattice) Defects caused by non-continuous succession, further causing the bond between the silicon-shixi and the silicon-oxygen bond to break off, resulting in interface depression The trapped charge 1 4 and the fixed oxide layer charge 16 are mainly distributed near the junction of the oxide layer 1 1 and the substrate 1 3. The 'fixed oxide layer charge 16 is a positive charge, and the fixed oxide layer charge 16 cannot be charged and discharged. The disappearance is mainly due to the oxidation process. When the oxidation suddenly stops, the excessive oxidized ions will be too late to be in the oxide layer 12. The oxide layer traps electricity 'mainly due to the formation of the oxide layer 2 itself' and in The electron or hole introduces this lack of charge 2 0 mainly into the daughter 'potassium ions' introduced in the process, and can carry out the oxidation reaction of the oxygen molecules existing at the interface between the oxide layer 12 and the substrate 13 and the retained charge 18 is distributed. Only when the entire structure of the oxide layer i 2 is caused by a defect (defect) is charged, and impurities such as mobile electric metal ions, such as sodium, can move freely in the layer 12. Volume diagram: Figure 1: Metal oxide semiconductor transistor shown in the figure: metal oxide semiconductor metal oxide: ^, belongs to the oxide semiconductor transistor 1 〇 contains an η-type body (PMOS) e e ^^ S)] transistor 22 and- ρ-type metal oxide semiconducting ινιυ ~ inferior crystal 24, η-type metal "all umbrellas, all of which are metal, a source of 28 genus / system 1 body 22 contains-interpole: conductor 24 contains-leisure, It is a metal layer 31 '”type metal oxide doped region: Infinite 36, which is a hetero: source 34 丄, which is an n-type metal halide semiconductor 2 2 and a p-type metal ^ °°, and a Oxide layer conduction: p-bstrate 38, semi-conductor 4 ~ n-well 4 0 phase 1 P-type metal oxide half-0 adjacent to P-type substrate 38, and

530419 V. Description of the invention (3) Source 3 4 and non-pole 3 6 are required when isolating the p-type substrate 38 from the n-type well 40 and passing the n-type well 40 to provide the on-state current of the p-type metal oxide semiconductor 24 Channel. For the n-type metal oxide semiconductor 22, when the voltage difference between the gate electrode 26 and the drain electrode 30 is greater than a rated value, covalent bonds in the semiconductor material will be damaged by an external electric field, and due to the oxide layer 3 1 itself contains a plurality of charges. Therefore, due to the influence of the applied electric field, an electronic disturbance in the oxide layer 3 1 is caused, and the number of electrons in the oxide layer 31 is increased sharply, so that the characteristics of the n-type metal oxide semiconductor 2 2 are due to the oxide layer 3 1 The crash was destroyed and failed. Similarly, for the p-type metal oxide semiconductor 24, when the voltage difference between the gate 32 and the non-electrode 36 is greater than a rated value, the covalent bonds in the semiconductor material will be damaged by an external electric field. And because the oxide layer 3 7 itself contains a plurality of charges, it is affected by the external electric field, which causes an electronic disturbance in the oxide layer 3 丨 and the number of electrons in the oxide layer 31 increases sharply, which makes the ρ-type metal oxide semiconductor 2 4 The characteristics are lost because the oxide layer 37 is destroyed. Please refer to FIG. 3, which is a schematic diagram of a conventional level shift circuit 50. The potential conversion circuit 50 includes a plurality of transistors 52, 54, 56, and 58. The transistors 52, 56 are p-type metal oxide semiconductor transistors, and the transistors 5 4, 58 are n-type metal oxide semiconductor transistors. . The gate of transistor 54 is connected to a voltage ν dd, the source of transistors 5 2 and 5 6 is connected to a voltage Vn, and the high level voltage value of the input voltage Vin is Vdd, and the low level voltage is Value is ground voltage (0 volts). For example, 乂 ’If Vn and Vdd are equal to 10 volts and 3.3 volts, respectively, and the breakdown voltage of transistor 5 2, 5 4, 5 6, 5 8 is 丨 0 volts, then when the input voltage

530419 V. Description of the invention (4) 5 4 series crystal 52 conductive crystal 5 6 series is V i η is high level (3.3 volts), transistor 5 8 series is conductive and transistor is non-conductive, so the terminal The voltage at the point B will approach the ground voltage and cause electricity c; ○ broadcast ^, and at the same time the voltage at the terminal A will approach 10 volts, and at this time the electric conduction is turned on, so the output voltage Vout approaches the ground voltage, the oblique transistor 5 2, 5 8 'Although it is in the on state, the reverse bias between the drain and gate approaches 10 volts. As mentioned above, the reverse bias is greater than the transistor 5 2, 5 8 The breakdown voltage will cause the breakdown of the gate oxide layer and generate a large amount of breakdown current, which will destroy the characteristics of the potential conversion circuit 50. Similarly, when the input voltage V i η is at a low level (0 volts), the transistor 58 is non-conducting and the transistor 54 will be turned on, so that the voltage at the terminal A will approach 0 volts and turn on. The crystal 5 6 makes the voltage at the terminal B approach 10 volts ... At this time, the transistor 52 is non-conducting, so the output voltage Vout will approach 10 volts. For the transistors 5 4 and 5 6, Although it is in the on state, the bias voltage between the drain and the gate approaches 10 volts. As mentioned above, because the bias voltage is greater than the breakdown voltage of the transistors 54 and 56, it will cause corresponding oxidation. The collapse of the layer generates a large amount of collapse current, and simultaneously destroys the characteristics of the potential conversion circuit 50. If the potential conversion circuit 50 is to prevent the oxide layers of the transistors 54, 56, and 58 from collapsing under high voltage differences, the bit conversion circuit 50 must control the level of the voltage Vn (for example, 5 volts) to the transistor 52. , 54, 56, 58 are operating normally. As mentioned above, if the transistors 54, 56, 58 are made of general metal oxide semiconductor transistors, the gate oxide layer itself will have a lower voltage due to charge doping, and the potential conversion circuit will be further advanced. Due to the high voltage (Vn) operation, the low breakdown voltage of transistors 52, 54, 56, and 58 is not stable.

530419 V. Description of the invention (5) The potential conversion circuit 50 cannot convert an input signal with a low potential to a high potential output signal with an excessive voltage difference. SUMMARY OF THE INVENTION The main object of the present invention is to provide a potential conversion circuit including a high breakdown voltage electric crystal to solve the above problems. The patent application scope of the present invention provides a potential conversion circuit for converting an input voltage into an output voltage. The potential conversion circuit includes at least a complementary metal oxide semiconductor transistor and is disposed on a p-type substrate. (p-substrate), which includes a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor. The n-type metal oxide semiconductor transistor includes a gate, a drain, and a source. The drain electrode includes an n-well formed on the p-type substrate, and a first N + doped region is provided in the n-well, and the source electrode includes a second N-well. A + doped region is formed on the p-type substrate. Detailed description of the invention Please refer to FIG. 4. FIG. 4 is a schematic structural diagram of an n-type metal oxide semiconductor electric crystal 60 according to the present invention. The n-type metal oxide semiconductor transistor 60 includes a gate electrode 62, which is a metal or a polycrystalline silicon, and a source electrode 64, which is an η-type.

Page 9 530419

Doped region, and a drain 66, which is an n-type doped region, a p-type substrate 68, an oxide layer 67, and an n-type well 70, and the n-type well 70 is formed at the drain 66 The drain electrode 66 and the p-type substrate 68 are separated from the p-type substrate 68 to avoid direct contact between the drain electrode 66 and the p-type substrate 68 to form a PN interface. The n-type well 70 is used to raise the south substrate 68 and the substrate. The collapse voltage between the poles 6 and 6 avoids the collapse effect of the interface between the poles 6 and the substrate 6 8. Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a first potential conversion circuit 80 of the present invention. The potential conversion circuit 80 includes a plurality of transistors 82, 84, 86, 88, 90, 92, and 94. Among them, the transistors 86, 88, 90, and 9 are P-type metal oxide semiconductor transistors, and the transistors 82, 84 Series 94 and 94 are n-type metal oxide semiconductor transistors. Please note that transistors 84 and 94 are η-type metal oxide semiconductor transistors 60 shown in Figure 4, and transistor 8 2 is a conventional η-type metal. Oxidized semiconductor transistor structure. The sources of the transistors 88 and 90 are connected to the voltage source Vn, while the transistors 88 and 90 are connected in a cros s-coup led manner. The gates of the transistors 86 and 92 are connected to a reference voltage. Vk, and the gates of the transistors 84 and 94 are connected to a voltage source Vdd. The high-level voltage value of the input voltage Vi η is Vdd, and the low-level voltage value is the ground voltage (0 volts). The operation of the potential conversion circuit 80 is detailed as follows. If the high-level voltage value Vdd of the input voltage Vi η is 3.3V, the reference voltage Vk is 3.3V, the voltage source Vn is 10V, and the breakdown voltage is 10 volts. When the input voltage V i η is at a high level (3.3 volts), transistor 9 4 is non-conducting, while transistors 8 2 and 8 4 are conducting and the voltage at terminal B approaches the ground. Voltage (0 volts) due to the gate connection of transistors 8 6, 9 2

530419 V. Description of the invention (7) Connected to the reference voltage Vk (3.3 volts), so transistor 8 6 is non-conducting, so the voltage at terminal B (0 volts) will not be transmitted to terminal C, and when When the source (terminal C) voltage of transistor 86 is high enough to exceed the sum of its gate voltage (3.3 volts) and its threshold voltage Vt, transistor 86 will be turned on until transistor 8 6's The source voltage is gradually adjusted to be less than the sum of its gate voltage and its threshold voltage. Therefore, the transistor 90 is turned on and the voltage at the terminal d approaches 10 volts. For the transistor 90, the reverse voltage between the gate and the pole of the transistor 90 approaches 6 · 6 volts, so no collapse effect will occur. In the same way, the reverse voltage between the gate and the drain of the transistor 8 8 approaches 6. 6 volts, so there will be no collapse effect. Finally, because the voltage at the terminal D approaches 10 volts, The crystal 92 is turned on so that the voltage of the terminal A approaches 10 volts. As described above, 'this embodiment avoids the transmission of 0 volts from the terminal B to the terminal (; and causes the transistors 8.8 and 90 to collapse. When the input voltage vi is at a low level (0 volts), transistor 8 2 is non-conducting, while transistor 9 4 is conducting, and the electricity at terminal A repeatedly approaches the ground voltage (0 volts). The gates of 9 and 2 are connected to the reference voltage V k (3.3 volts), so the electricity at terminal a (0 volts) will not be transmitted to terminal D, and when the source of transistor 9 2 (terminal D) When the voltage rises above the sum of its gate voltage (3.3 volts) and its critical voltage Vt, the transistor 9 2 will be turned on until the voltage The source voltage of the body 92 is gradually adjusted to be less than the sum of its gate voltage and its critical voltage. Therefore, the electric soil body 88 is turned on and the voltage at the terminal C approaches 10 volts. For the transistor 88 and a, the gate The reverse voltage between the pole and the drain approaches 6. 6 volts, so there is no collapse effect. Similarly, the reverse voltage between the gate and the drain of transistor 90 approaches 6.6 volts, so it does not Will have a crash effect, most

Page 11 530419, description of the invention (8) 2. As the voltage at terminal c approaches 丨 0 volts, the voltage at point B approaches 10 volts, as described above; this body ;; conduction *, eight. The volts are transmitted to The terminal D causes the transistor: :: to avoid terminal f. In addition, because the transistors 84 and 94 are at 9: 9, they will collapse to the extreme point .... Volts), greater than the rest; ;; = 的 本本 公 本 办 丨 tb Then, the contact voltage> Beijing voltage 'so the semiconductor power:] == 94 :, using the n-type metal oxygen conductor shown in Figure 4 Structure has high breakdown voltage characteristics. Electricity: The 100 nl bit conversion circuit 100 of the second potential conversion circuit of the present invention includes a plurality of transistors 84, 86, 88, 90, 92, 94, 1〇 2 and a reverser (mverter) 104, where the transistor 86, ⑽, 90, 92 series = =, the transistor ",", 104 series is n-type metal emulsion + conductor transistor 胄 'Please Note that the transistors 84 and 94 are η-type metal oxide semiconductor transistors 60 and the transistors 82 and 10 2 are conventional η-type metal oxides. Transistor transistor structure. Sources of transistors 88 and 90 are connected to voltage source Vn, while transistors 88 and 90 are connected in a staggered coupling manner. Gates of transistors 86 and 92 are connected to a reference voltage Vk. The gates of the transistors 84 and 94 are connected to a voltage source Vdd. The 咼 level voltage value of the input voltage vin is Vdd, and the low level voltage value is the ground voltage (0 volts), and the inverter 104 is connected. And the gate of transistor 82, 102. The operation of the potential conversion circuit 100 is detailed as follows. If the high-level voltage value of the input voltage Vin is ¥ (1 (1 is 3.3 volts, and the reference voltage ^ is 33 volts, The voltage source "is 10 volts, and the breakdown voltage of the oxide layer and the breakdown voltage of the interface are 丨 0 volts.

530419 V. Description of the invention (9) When the input voltage V i η is at a low level (0 volts), the transistor 9 is not conductive, while the transistors 82 and 84 are conductive and the terminal B is The voltage approaches the ground voltage (0 volts). Since the gates of the transistors 8 6, 9 2 are connected to the reference voltage Vk (3.3 volts), the voltage at the terminal B (0 volts) will not be transmitted to the terminal C When the source (terminal C) voltage of transistor 86 rises above the sum of its gate voltage (3_3 volts) and its threshold voltage V t, transistor 86 will be turned on until transistor 8 6's The source voltage is gradually adjusted to be less than the sum of its gate voltage and its threshold voltage. Therefore, the transistor 90 is turned on so that the voltage at the terminal D approaches 10 volts. For the transistor 90, the reverse voltage between the gate and the drain approaches 6.6 volts, so there is no collapse effect. In the same way, the reverse voltage between the gate and the drain of the transistor 8 8 approaches 6.6 volts, so there will be no collapse effect. Finally, because the voltage at the terminal D approaches 10 volts, The crystal 92 is turned on so that the voltage at the terminal A approaches 10 volts. As described above, this embodiment prevents the 0 volts at the terminal B from being transmitted to the terminal C and cause the transistors 88 and 90 to collapse.时 When the input voltage yin is at a high level (3.3 volts), the transistor 82 is non-conducting, and the transistors 94 and 102 are turned on so that the voltage at the terminal A approaches the ground voltage (0 volts). The gates of the transistors 86 and 92 are connected to the reference voltage vk (3.3 volts) ', so the voltage (0 volts) at the terminal A will not be transmitted to the terminal ρ, and when the source of the transistor 9 2 (terminal D) When the voltage rises above the sum of its gate voltage (3.3V) and its critical voltage Vt, transistor 92 will be turned on until the source voltage of transistor 92 is gradually adjusted to be less than its gate voltage and its critical voltage So far. Therefore, the transistor 88 is turned on and the voltage at the terminal C approaches 10 volts. 'For the transistor 88, the inverse between the gate and the drain

530419 V. Description of the Invention (ίο) Directional voltage approaches 6. 6 volts, so no collapse effect will occur. Similarly, the reverse voltage between the gate and drain of transistor 90 will approach 66 volts, so There will be no collapse effect. Finally, because the voltage at the terminal C approaches 10 volts, the transistor 86 is turned on and the voltage at the terminal B approaches 10 volts, as described above. 'This embodiment avoids the terminal A The transmission of 0 volts to the terminal j) caused the collapse of the electric body 8.8,90. In addition, because the drain voltages of the transistors 8 4 and 9 4 that must be withstood during operation are greater than the breakdown voltage of the basin junction, in this embodiment, the transistors 84 and 94 are used in FIG. Depending on the structure of the n-type metal oxide semiconductor transistor 60, it has a relatively breakdown voltage characteristic. Please refer to 5 0 because the circuit will collapse to a high potential (circuit, and the electrical circuit, that is, circuit 80 or potential, for example, volts, and low, the output voltage drop is less than Vout as the input voltage Vin, the low level of the circuit Figures 2, 5, and 6 show that a low potential (Vdd) cannot be smoothly converted to Vn due to the known collapse effect of the potential conversion circuit. However, the potential conversion circuit 50 can be used as the first-stage bit conversion circuit 80. Or the potential conversion circuit 100 is used as the second stage, and the output voltage of the potential conversion circuit 50 is used as the input voltage of the potential conversion circuit 100 to perform further. The high level of the input voltage Vln of == is 3 · 3 ^ is The ground voltage, and the voltage source Vn is 5 volts, so out is 5 volts or 0 volts, and the gate sinks and collapses the voltage, and then the potential conversion circuit _ = one / power ^ and the potential conversion work, please Note that this potential (Vdd) is $ 5 volts, so that the potential conversion circuit 80 or 530419 V. Description of the invention (11) ^ ---- The output low level of the potential conversion circuit 100 is the ground voltage (0 volts) 〇 South level of Ut is 1 〇 The purpose and the reduction of the gate of the transistor ^ can also achieve the scope of the required potential conversion. The voltage across the pole to the drain is controlled by the transistor compared to the voltage Vk of the conventional technology. 6. The collapse effect, in the process, in the drain conversion circuit 8 0, the voltage difference between the potential conversion circuit and the collapse voltage that does not require an extra special process to complete the collapse-the reference voltage is too high to avoid the potential through the oxide layer process Based on the electric program transistor of the bottom, the electric potential conversion circuit 80, i 00 of the present invention uses the transistor 8 6, 9 2 to be on or off, so as to avoid grounding the gate of the transistor 8 8, 9 0 which is transmitted. Cause and insert an n-type well structure between the end of the general metal oxide semiconductor transistor and the substrate to raise the breakdown voltage of the 100 transistors 84 and 94 to avoid the 80 and 100 because of the large drain-to-base collapse In addition, the process of implanting an n-well structure can be formed by using general metal oxide semiconductors, which not only can greatly improve metal oxide semiconductors but also has low cost. The above description is only a preferred embodiment of the present invention. according to Patent disclosure range of modifications and alterations made, Han also belong to the present invention cover the scope of the patent.

Page 15 530419 Brief description of the drawings Brief description of the drawings Figure 1 is a schematic diagram of the charge distribution of the oxide layer of a conventional metal oxide semiconductor transistor. Fig. 2 is a schematic diagram showing the structure of the metal oxide semiconductor transistor shown in Fig. 1. FIG. 3 is a schematic diagram of a conventional potential conversion circuit. FIG. 4 is a schematic structural view of an n-type metal oxide semiconductor transistor according to the present invention. FIG. 5 is a schematic circuit diagram of a first potential conversion circuit according to the present invention. FIG. 6 is a circuit diagram of a second potential conversion circuit according to the present invention. Explanation of symbols in the drawings 10 '52, 54, 56, 58, 82, 84 > 86, 88, 90, 92, 9 4, 1 0 2 Metal oxide semiconductor transistor 11 Metal layer 1 2, 3 3 37, 6 7 Oxide layer 13, 38, 68 Substrate 14 Interface trapped charge 16 Fixed oxide layer charge 18 Oxide layer trapped charge 20 Movable charge 2 2, 6 0 η-type metal oxide semiconductor transistor

Page 16 530419 Brief description of drawings 24 26 '32' 62 28, 3 [64 30 ^ 36 ^ 66 40, 70 50 '80 > 100 104 P-type metal oxide semiconductor transistor gate source drain n-type well Inverter for potential conversion circuit

Page 17

Claims (1)

530419 6. Scope of patent application 1. A potential shift circuit for converting an input voltage into an output voltage. The potential conversion circuit includes: at least one complementary metal oxide semi conductor transistor It is free from a p-substrate, which includes a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor. The n-type metal oxide semiconductor transistor includes: a gate; The drain electrode, on the bottom of the complex white, a first -N '+ for two η-type wells (niell) formed adjacent to the ρ-type well; and a hetero-region' is provided in the η-type well and is connected to The η is a source electrode, and its package is on the bottom. 3 A second N + doped region is formed on the P-type base 2. The potential conversion circuit as described in the patent application includes: Le, which includes the first and second complementary metals 5, and a semiconductor transistor Emulsified semiconductor transistor, the two complementary metal oxygen interconnected to provide the f-type metal oxide semiconductor transistor gate system phase first and second p-type metal f voltage test; and the source of the semiconductor transistor The semi-bulk transistor is connected to a power supply, and the gate electrode of the first P-oxide semiconductor transistor is connected to the second complementary metal. In the first P-type metal oxide, the light electrode of the metal oxide semiconductor transistor is connected to the first electrode of the conductive transistor. Page 18, 530419 VI. Patent application: The P-type metal oxide semiconductor transistor is a drain of a complementary metal oxide semiconductor transistor. The drain of the first p-type metal oxide semiconductor transistor is connected to the first complementary metal oxide semiconductor. The source of the p-type metal oxide semiconductor transistor of the transistor. The drain of the second p-type metal oxide semiconductor transistor is connected to the source of the p-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor. . 3. The potential conversion circuit as described in item 2 of the patent application scope, further comprising a first n-type metal oxide semiconductor transistor, the drain of which is connected to the second complementary metal oxide semiconductor transistor, the n-type metal oxide The gate of the source of the semiconductor transistor is connected to the source of the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor, and the source of the first n-type metal oxide semiconductor transistor is grounded. 4. The potential conversion circuit described in item 3 of the scope of patent application, further comprising an input terminal connected to the gate of the first n-type metal oxide semiconductor transistor for inputting the input voltage to control the first Whether the n-type metal oxide semiconductor transistor is conducting. 5. The potential conversion circuit as described in item 4 of the scope of the patent application, wherein the gates of the n-type metal oxide semiconductor transistor of the first and second complementary metal oxide semiconductor transistors are connected to a control voltage for use in accordance with The control voltage and the input voltage determine whether the n-type metal oxide semiconductor transistor of the two complementary metal oxide semiconductor transistors is on. Page 19, 530419 VI. In the scope of the patent application, the description of the road power transposition is described in item 5. Please refer to the Fanli Special Fund for mutual assistance. The 6th body guide semi-oxygen is a gold type η body crystal ^ g body. Conductive semi-oxygen type is a body crystal of type η system η, body crystal, crystal electric body, electric conductor, semi-conductive semi-halogenated oxide, oxygen-based metal, gold type, ptin 1 Mnr > Second, second, first, and second, the body is conductive and conductive to conduct electricity. The body oxygen crystal is a conductive gold when it is not gold. The body is conductive and semiconductive. The oxygen day is 0B. The body oxygen crystal is an electro-gold body type guide η semi-unified. The first oxygen pass is a semi-integrated interconductor with gold non-physical supplements. The crystal oxygen 7. The potential conversion circuit described in item 2 of the patent application scope, which further includes first and second n-type metals. Oxide semiconductor transistor, the gates of the two n-type metal oxide semiconductor transistors are connected to each other via an inverter, and the drain of the first n-type metal oxide semiconductor transistor is connected to the first complementary metal oxide semiconductor The source of the n-type metal oxide semiconductor transistor of the crystal, and the drain of the second n-type metal oxide semiconductor transistor is connected to the source of the n-type metal oxide semiconductor transistor of the second complementary metal oxide semiconductor transistor. The source of the two n-type metal oxide semiconductor transistor is grounded. 8. The potential conversion circuit described in item 7 of the scope of patent application, further comprising an input terminal connected to the gate of the first n-type metal oxide semiconductor transistor for inputting the input voltage to control the first Is the n-type metal oxide semiconductor transistor or the second n-type metal oxide semiconductor transistor conductive? Page 20 530419 VI. Scope of patent application 9. The potential conversion circuit according to item 8 in the scope of the patent application, wherein the gates of the n-type metal oxide semiconductor transistor of the first and second complementary metal oxide semiconductor transistors are connected to a control voltage for The control voltage and the input voltage determine whether the n-type metal oxide semiconductor transistor of the two complementary metal emulsified semiconductor transistors is on. 10. The potential conversion circuit according to item 9 of the scope of the patent application, wherein when the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor are conducting, The n-type metal oxide semiconductor of the second complementary metal oxide semiconductor transistor and the second n-type metal oxide semiconductor transistor system are non-conductive, and when the n-type metal oxide semiconductor of the second complementary metal oxide semiconductor transistor and the When the second n-type metal oxide semiconductor transistor is turned on, the n-type metal oxide semiconductor transistor of the first complementary metal oxide semiconductor transistor and the first n-type metal oxide semiconductor transistor system are non-conductive. 1 1. The potential conversion circuit described in item 1 of the scope of patent application, further comprising an output terminal provided in the n-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor in the complementary metal oxide semiconductor transistor To output the output voltage. Page 21