JP2004129019A - Internal negative power supply generation circuit and semiconductor memory having the generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an internal negative power supply from becoming deeper by an increase of an external power supply. <P>SOLUTION: An internal negative power supply generation circuit has a charge pump circuit generating a negative power supply lower than a grounded power supply at a negative power supply terminal by receiving an external power supply and the grounded power supply and by absorbing a charge from the negative power supply terminal, and a charge pump control circuit monitoring a potential of the negative power supply terminal and controlling the charge pump circuit to be an operation state and a non-operation state so as to keep the negative power supply potential a first level when the external power supply is a predetermined rated potential. When the external power supply increases higher than the rated potential, the charge pump control circuit controls the charge pump circuit so as to keep the negative power supply potential a second level which is shallower than the first level. When the external power supply increases higher than the rated potential, the charge pump control circuit controls the negative power supply potential to be the second level which is shallower (higher) than the normal first level, whereby a cell transistor, a transistor of a word driver, and the like are prevented from reaching a gate insulation film breakdown. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an internal negative power supply generation circuit, and more particularly, to a circuit for generating an internal negative power supply having a shallower level in response to a rise in an external power supply, and a semiconductor memory having the same.
[0002]
[Prior art]
The semiconductor memory generates an internal positive power supply lower than an external power supply for power saving, and uses it as a power supply for the memory cell array. For example, in a dynamic RAM, a voltage level in a memory cell is controlled to a ground voltage or an internal positive power supply voltage. In a semiconductor memory, a back bias power supply is generated to absorb a current leaking to the substrate side. The back bias power supply is a negative power supply lower than the ground voltage. By applying the back bias power to the substrate, the threshold value of the internal transistor is prevented from being lowered.
[0003]
On the other hand, in the dynamic RAM, as the capacity and the miniaturization are increased, the size of the cell transistor is miniaturized, the threshold voltage is lowered, and the sub-threshold leakage current in an off state tends to be remarkable. This increase in the leak current of the cell transistor is undesirable because it causes the refresh cycle to be shortened.
[0004]
In order to prevent such a sub-threshold leakage current, the off-state word line potential of the N-type cell transistor may be changed from the conventional ground potential to a negative potential. By setting the word line potential to a negative potential, a cell transistor having a low threshold voltage is reliably turned off to prevent the leak current. Alternatively, as another leakage current prevention method, it is conceivable to control the word line potential to a negative potential (ON state) and an external positive power supply potential (OFF state) using a P-type cell transistor. By controlling to the internal positive power supply potential, the P-channel type cell transistor is reliably turned off, and the above-described leakage current is prevented.
[0005]
In order to supply such a negative potential, it is necessary to internally generate a negative power supply. Such an internal negative power supply is generated by a charge pump circuit, similarly to the back bias power supply. That is, by absorbing the charge by the clock generated by the oscillation circuit, a power supply having a negative potential lower than the ground potential is generated. A charge pump control circuit for monitoring the internal negative power supply potential is provided, and the internal negative power supply potential is maintained at a constant value by controlling the operation of the oscillation circuit of the charge pump circuit. The above conventional example is described in, for example, Patent Document 1 below.
[0006]
[Patent Document 1]
Satoshi Eto et al. , "A1 Gb SDRAM with Ground Level Pre-charged Bit Line and Non-Boosted 2.1V Word Line", ISSCC Digest of Technical Papers, pp. 82-83. , 1998
[0007]
[Problems to be solved by the invention]
However, if the potential of the external power supply fluctuates higher than the rated potential, the potential difference between the external power supply potential and the internal negative power supply potential increases, and the gate insulating film of the word driver transistor may be destroyed. Also, when the cell transistor is a P-type transistor, the potential difference between the external power supply potential and the negative power supply potential may be widened, which may cause the gate insulating film of the cell transistor to be destroyed. When the external power supply rises, the internal positive power supply potential generated from the external power supply also rises slightly, and when the internal negative power supply potential is kept constant from the ground potential, the potential difference between the internal positive power supply potential and the negative power supply potential also widens. Therefore, there is a possibility that the gate insulating film of the internal transistor is broken. Further, when the external power supply rises, the cycle of the oscillator of the circuit that generates the boosted power supply becomes shorter, and the level of the boosted power supply rises. This leads to the risk that the gate insulating film of the transistor of the word driver is broken when the word line is driven by the boost power supply.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a negative power supply generating circuit for generating a shallower negative power supply in accordance with an increase in the potential of an external power supply, and a semiconductor memory having the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, one aspect of the present invention is to supply a negative power supply to an external power supply and a ground power supply, and to generate a negative power supply lower than the ground power supply at the negative power supply terminal by absorbing a charge from the negative power supply terminal. A charge pump circuit,
The potential of the negative power supply terminal is monitored, and when the external power supply has a predetermined rated potential, the charge pump circuit is controlled between an operating state and a non-operating state so as to maintain the negative power supply potential at a first level. A charge pump control circuit,
The charge pump control circuit controls the charge pump circuit so as to maintain the negative power supply potential at a second level shallower than the first level when the external power supply rises higher than a rated potential. Features.
[0010]
According to the aspect of the present invention, the charge pump control circuit controls the negative power supply potential to the second level shallower (higher) than the normal first level when the external power supply rises above the rated potential. In addition, it is possible to prevent a cell transistor, a transistor of a word driver, and the like from being damaged by a gate insulating film.
[0011]
According to a preferred embodiment of the present invention, the charge pump control circuit includes a reference voltage generation circuit that is supplied with an external power supply and generates a reference voltage that increases in accordance with the rise of the external power supply. When the negative power supply potential rises above a predetermined level with respect to the reference voltage, activates the charge pump circuit; when the negative power supply potential falls below a predetermined level, deactivates the charge pump circuit; The charge pump circuit switches between an operating state and a non-operating state when the negative power supply potential becomes a level shallower than the predetermined level.
[0012]
Since the reference voltage generation circuit generates the reference voltage from the external power supply and the ground power supply, when the external power supply rises, the reference voltage also rises, and accordingly, the negative power supply potential for switching the operation state and the non-operation state of the charge pump circuit. The level rises to generate a shallower level of negative power supply potential.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.
[0014]
FIG. 1 is a diagram showing a power generation circuit group of a semiconductor memory. The dynamic semiconductor memory drives the word line potential to a boosted power supply Vpp higher than the external power supply VDD in order to sufficiently conduct the cell transistors. In addition, an internal positive power supply Vii lower than the external power supply VDD is used as a cell array power supply for power saving. Then, in the present embodiment, an internal negative power supply VNN lower than the ground power supply is generated. This internal negative power supply VNN is a negative power supply different from the back bias power supply applied to the semiconductor substrate.
[0015]
The boosted power supply generating circuit 1 that generates the boosted power supply Vpp has an oscillation circuit OSC1 and a Vpp pump circuit 10 that supplies a charge supplied from the external power supply VDD to the boosted power supply terminal Vpp by a clock CLK1 generated by the oscillator OSC1. Then, the boosted power supply Vpp is set higher than the external power supply VDD. The boosted power supply Vpp is monitored by a boosted power supply level monitoring circuit (not shown), and the boosted power supply level monitoring circuit controls the oscillation circuit OSC1 such that the level of the boosted power supply Vpp is maintained at a predetermined level higher than the external power supply VDD. . When the level of the external power supply VDD rises, the cycle of the oscillation circuit becomes shorter, the pumping operation of the pump circuit 10 becomes active, and the boosted power supply level tends to rise.
[0016]
The internal positive power supply Vii is generated by the internal positive power supply generation circuit 2. The internal positive power supply generation circuit 2 generates a constant gate voltage Vg from the external power supply VDD, and applies the gate voltage Vg to the gate. The internal positive power supply generation transistor 14 has a drain connected to the external power supply VDD and an internal positive power supply Vii generated from the source. The internal positive power supply Vii is maintained at a constant level lower than the gate voltage Vg by the threshold voltage of the transistor 14, and supplies current from the external power supply VDD. When the internal positive power supply Vii decreases, the transistor 14 becomes more conductive, and current is supplied from the external power supply VDD, thereby preventing the level of the internal positive power supply Vii from lowering. Further, when the level of the internal positive power supply Vii rises to some extent such as when the memory enters a sleep state, the transistor 14 becomes more non-conductive, the current supplied from the external power supply VDD decreases, and the rise of the internal positive power supply Vii is suppressed. You.
[0017]
Next, an internal negative power supply generation circuit 3 for generating an internal negative power supply VNN includes an oscillation circuit OSC2 for generating a clock CLK2, and a VNN pump circuit 16 for extracting a charge from the internal negative power supply terminal VNN to the ground power supply Vss by the clock CLK2. And a charge pump control circuit 18. The charge pump control circuit 18 monitors the level of the internal negative power supply VNN, activates the oscillation circuit OSC2 when the level of the internal negative power supply VNN becomes shallower than a predetermined level, and activates the oscillation circuit when the level of the internal negative power supply VNN becomes deeper than the predetermined level. Inactive. As described above, the internal negative power supply generation circuit 3 controls the pumping operation of the pump circuit 16 by controlling the operation state of the oscillation circuit OSC2 according to the level of the internal negative power supply VNN, and controls the internal negative power supply VNN to a predetermined level. Maintain at a negative level. This detailed circuit will be described later.
[0018]
FIG. 2 is a diagram showing the relationship between power supplies in a semiconductor memory. The horizontal axis indicates time, and the vertical axis indicates voltage level. At time zero, the external power supply VDD is not turned on. When the external power supply VDD is turned on at time zero, the external power supply VDD rises and rises to a predetermined rated voltage level. With the rise of the external power supply VDD, both the internally generated boosted power supply Vpp and the internal positive power supply Vii rise, and the boosted power supply Vpp becomes a predetermined level higher than the external power supply VDD. It rises to a level lower than the external power supply VDD. Further, the internal negative power supply VNN becomes lower than the ground power supply Vss and rises to a predetermined negative potential level with the rise of the external power supply VDD. That is, when the external power supply VDD is turned on, a boosted power supply Vpp, an internal positive power supply Vii, and an internal negative power supply VNN are generated inside the semiconductor memory.
[0019]
FIG. 3 is a diagram illustrating an example of a semiconductor memory. In this semiconductor memory, a memory cell including a cell transistor MC and a capacitor Cm is provided at an intersection of a word line WL and a bit line BL. The cell transistor MC is an N-channel transistor, the word line WL is driven by the boosted power supply Vpp or the internal negative power supply VNN by the transistors 20 and 21 of the word driver WD, and the bit line BL is driven by the sense amplifier SA to the internal positive power supply Vii or ground. Driven by power supply Vss. By driving the word line WL connected to the gate of the cell transistor MC to the boosted power supply Vpp, the cell transistor MC is sufficiently turned on. By driving the word line WL to the internal negative power supply VNN, the cell transistor MC is completely turned off. It becomes non-conductive. That is, by setting the level of the non-selected word line to a negative potential, the sub-threshold leakage current of the cell transistor in the non-selected state can be suppressed.
[0020]
FIG. 4 is a diagram illustrating another example of the semiconductor memory. In this example, the cell transistor MC is formed of a P-channel transistor, and the word line WL is driven to the external power supply VDD or the internal negative power supply VNN by the word driver WD. The bit line BL is driven to the internal positive power supply Vii or the ground power supply Vss by the sense amplifier SA. When the cell transistor MC is a P-channel transistor, the word line WL can be set to the external power supply VDD and the cell transistor can be completely turned off in a non-selected state. In the selected state, the cell transistor can be made more conductive by setting the word line WL to the internal negative power supply VNN.
[0021]
In the example of FIG. 3, a boosted power supply level selection signal RD is applied to the gate of the transistor 21 of the word driver WD, and a boosted power supply Vpp and an internal negative power supply VNN are applied between the gate and source of the transistor 21. You. An internal negative power supply VNN and an internal positive power supply Vii are applied between the gate and the drain of the cell transistor MC. In the example of FIG. 4, the external power supply VDD and the internal negative power supply VNN are applied between the gate and the source of the transistor 23 of the word driver, and the internal negative power supply VNN and the internal positive power supply are applied between the gate and the drain of the cell transistor MC. The power supply Vii is applied.
[0022]
As described above, the internal negative power supply VNN is employed to prevent a sub-threshold leakage current. However, the voltage difference between the internal negative power supply VNN and the external power supply VDD, the internal negative power supply VNN and the internal positive power supply Vii, and the booster When the voltage difference from the power supply Vpp increases, the gate insulating film of the internal transistor may be broken.
[0023]
FIG. 5 is a diagram illustrating an example of the internal negative power supply generation circuit. The VNN pump circuit 16 includes a pump capacitor Cp, a transistor 25 provided between the ground power supply Vss and the node 24 of the pump capacitor Cp, and a transistor 26 provided between the internal negative power supply VNN and the node 24. And The gates and the drains of the transistors 25 and 26 are both connected, and operate as diodes. The VNN pump circuit 16 and the oscillator OSC2 form a charge pump circuit.
[0024]
In this charge pump circuit, in response to the rise of the clock CLK2 generated by the oscillator OSC2, the node 24 also rises due to the capacitive coupling of the capacitor Cp, the transistor 26 becomes non-conductive in the reverse direction, and the ground power supply Vss Charge is extruded. In response to the subsequent fall of the clock CLK2, the transistor 25 is turned off in the reverse direction, so that electric charge is drawn from the negative power supply terminal VNN via the transistor 26. By repeating this, the potential of the negative power supply VNN becomes lower than the ground power supply Vss. When the oscillator OSC2 is in the operating state, the internal negative power supply VNN is made lower than the ground power supply by the above-described pumping operation using the clock CLK2. However, when the oscillator OSC2 is in the non-operating state, the clock CLK2 stops and the pumping operation stops.
[0025]
The charge pump control circuit 18 includes a three-stage CMOS inverter. The P-channel transistor 30 of the first-stage CMOS inverter has a source connected to the external power supply VDD, a gate connected to the reference node S39, and a drain connected to the N-channel transistor 31. Is done. The N-channel transistor 31 has a source connected to the internal negative power supply VNN and a gate connected to the reference node S39. The reference node S39 is connected to the ground power supply Vss. The output S18 of the final-stage CMOS inverter is supplied to the oscillator OSC2 as a control signal.
[0026]
FIG. 6 is an operation waveform diagram showing the operation of the charge pump control circuit 18. The horizontal axis indicates time, and the vertical axis indicates voltage. At time zero, when the external power supply VDD rises, the P-channel transistor 30 becomes conductive accordingly, and the node 36 rises with the rise of the external power supply VDD. At this time, the node 37 goes low and the control node S18 goes high, the oscillator OSC2 is controlled to an operating state, and the pumping operation of the pump circuit 16 lowers the internal negative power supply VNN to a level lower than the ground potential.
[0027]
Since the gate of the N-channel transistor 31 of the first-stage CMOS inverter is connected to the ground potential and the source is connected to the internal negative power supply VNN, when the internal negative power supply VNN falls to a predetermined level with respect to the ground potential of the reference node S39, The transistor 31 is turned on. As a result, node 36 is at a level determined by the on-resistance ratio of transistors 30 and 31. In this example, the transistors are designed such that when both transistors conduct, node 36 is at ground level. With the switching of the node 36 to the ground level, the CMOS inverters of the second and third stages are inverted, the node 37 goes to H level to follow the external power supply VDD, and the control node S18 goes to L level. Flip to Due to the inversion of control node S18, oscillator OSC2 is controlled to a non-operating state, and the level of internal negative power supply VNN is maintained at a level lower than the ground potential by a predetermined level.
[0028]
However, when the internal negative power supply VNN becomes shallower than a predetermined level due to the operation of an internal circuit or the like, the transistor 31 is turned off again, the control node S18 goes to the H level, the oscillator OSC2 is activated, and the pumping operation is restarted. Thus, the operation of extracting charges is repeated until the internal negative power supply VNN falls to a predetermined level.
[0029]
A problem of the pump control circuit 18 shown in FIG. 5 is that the reference node S39 is connected to the ground potential Vss, so that when the external power supply VDD rises above the rated level, the internal negative power supply VNN switches between the conductive state and the non-conductive state when the transistor 31 switches to the conductive state. The level is going to be deeper. That is, when the external power supply VDD rises, the transistor 30 becomes conductive more deeply, and its on-resistance decreases. Therefore, the level of the node 31 will not be inverted unless the internal negative power supply VNN is at a deeper level and the transistor 31 is made deeper to conduct. That is, as the external power supply VDD increases, the internal negative power supply VNN is controlled to a deeper level.
[0030]
Furthermore, when the external power supply VDD rises above the rated level, the oscillation frequency of the oscillator OSC2 increases, the pumping operation becomes more active, and the level of the internal negative power supply VNN becomes deeper.
[0031]
An increase in the external power supply VDD causes a slight increase in the levels of the internally generated boosted power supply Vpp and the internal positive power supply Vii. In conjunction with the decrease in the internal negative power supply VNN, the voltage difference between Vpp and VNN and the voltage difference between Vii and VNN become larger, and the gate insulating film of the internal transistor is destroyed.
[0032]
FIG. 7 is a diagram showing an internal negative power supply generation circuit according to the present embodiment. FIG. 8 is an operation waveform diagram thereof. The internal negative power supply generating circuit of the present embodiment has the same oscillator OSC2 as in FIG. 5, a pump circuit 16, and a control circuit 18 thereof, and further sets the reference node level S39 in response to the rise of the external power supply VDD. It has a reference voltage generating circuit 50 for raising.
[0033]
Although the reference node S39 is fixed to the ground power supply Vss in the circuit of FIG. 5, in FIG. 6, since the level between the external power supply VDD and the ground power supply Vss is divided by the resistors R3 and R4, the external power supply VDD is used. Rise above the ground level as the rises above the rated level.
[0034]
As shown in the operation waveform diagram of FIG. 8, when the power supply VDD is turned on, the power supply VDD rises, the nodes 36 and the control node S18 also rise, and the oscillator OSC2 enters an operating state, and the internal negative power supply VNN is activated by the pumping operation. Decreases. Eventually, the transistor 31 becomes conductive, the node 36 goes down to the ground level, the control node S18 goes low, the oscillator goes into an inactive state, and the level drop of the internal negative power supply VNN stops. Up to this point, it is the same as the circuit of FIG. In this state, the reference node level generation circuit 50 determines that the voltage V1 obtained by dividing the external power supply VDD by the resistors R1 and R2 is lower than the reference voltage Vref, the output N40 of the comparator 40 is H level, and the output N41 of the inverter 41 is L level. , And the transistor 42 is off. Therefore, the level of reference node S39 is maintained at the level of ground power supply Vss.
[0035]
At a certain time, when the external power supply VDD rises above the rated voltage, the voltage V1 divided by the resistors R1 and R2 rises, the output of the comparator 40 is inverted, and the output N41 of the inverter 41 becomes H level, The channel transistor 42 is turned on. Therefore, the reference node S39 has the external power supply VDD at a voltage division level based on the on-resistance of the transistor 42 and the resistors R3 and R4, and rises to the positive voltage side following the rise of the external power supply VDD. As the reference node S39 rises, the internal negative power supply level at which the transistor 31 of the control circuit 18 is inverted rises. Specifically, the internal negative power supply level increases from the increased level of reference node S39 to a level lower by the threshold voltage of transistor 31. That is, when the external power supply VDD rises, the level of the internal negative power supply VNN is controlled to be shallower accordingly. Accordingly, it is possible to suppress or prevent the internal transistor from being caused to have gate insulation breakdown due to the level of the internal negative power supply VNN becoming too deep.
[0036]
FIG. 9 is a diagram showing another internal negative power supply generating circuit according to the present embodiment. FIG. 10 is an operation waveform diagram thereof. The internal negative power supply generation circuit of FIG. 9 has the same oscillator OSC2, pump circuit 16, and control circuit 18 as those of FIG. 7, and the reference node level generation circuit 50 is different from that of FIG. The reference node level generating circuit 50 includes a plurality of diode-connected transistors 51 to 53 and a resistor R5 connected in cascade between an external power supply VDD and a ground power supply Vss, and a connection point between the resistor R5 and the transistor 53. Are connected to the reference node S39.
[0037]
The operation of the reference node level generation circuit 50 is simple. When the external power supply VDD rises, the level of the reference node S39 is maintained at a level lower than the external power supply VDD by the total value nVth of the threshold voltages of the transistors 51 to 53. You. Therefore, as shown in FIG. 10, when the external power supply VDD rises above the rated level, the reference node S39 also rises at the level of VDD-nVth accordingly. As the level of the reference node S39 rises, the level of the internal negative power supply VNN is controlled so as to be shallower. That is, the internal negative power supply VNN is maintained at a level lower than the reference node S39 by the threshold voltage of the transistor 31. As a result, the voltage difference dV between the external power supply VDD and the internal negative power supply VNN is suppressed to a predetermined level difference or less.
[0038]
Thus, even if the external power supply VDD rises, the internal negative power supply VNN is prevented from becoming deeper, and the level difference dV between the external power supply VDD and the internal negative power supply VNN is also prevented from increasing beyond a predetermined level. Controlled. Therefore, the transistor inside the semiconductor memory is prevented from being damaged by the gate insulating film.
[0039]
【The invention's effect】
As described above, according to the present invention, the internal negative power supply is prevented from becoming deeper due to the rise of the external power supply.
[Brief description of the drawings]
FIG. 1 is a diagram showing a power generation circuit group of a semiconductor memory.
FIG. 2 is a diagram showing a relationship between power supplies in a semiconductor memory;
FIG. 3 is a diagram illustrating an example of a semiconductor memory.
FIG. 4 is a diagram showing another example of the semiconductor memory.
FIG. 5 is a diagram illustrating an example of an internal negative power supply generation circuit.
6 is an operation waveform diagram of FIG.
FIG. 7 is a diagram showing an internal negative power supply generation circuit according to the present embodiment.
8 is an operation waveform diagram of FIG.
FIG. 9 is a diagram showing another internal negative power supply generation circuit according to the present embodiment.
FIG. 10 is an operation waveform diagram of FIG.
[Explanation of symbols]
3 Internal negative power supply generation circuit, OSC2 oscillator, 16 pump circuit, 18 charge pump control circuit, 50 reference voltage generation circuit

Claims (7)

A charge pump circuit that is supplied with an external power supply and a ground power supply, and generates an internal negative power supply lower than the ground power supply at the negative power supply terminal by absorbing a charge from the negative power supply terminal;
The potential of the negative power supply terminal is monitored, and when the external power supply has a predetermined rated potential, the charge pump circuit is controlled between an operating state and a non-operating state so as to maintain the negative power supply potential at a first level. A charge pump control circuit that performs
The charge pump control circuit controls the charge pump circuit so as to maintain the negative power supply potential at a second level shallower than the first level when the external power supply rises higher than a rated potential. Characteristic internal negative power supply generation circuit. In claim 1,
The charge pump control circuit includes a reference voltage generation circuit that is supplied with the external power and generates a reference voltage that increases in accordance with an increase in the external power,
The charge pump control circuit activates the charge pump circuit when the internal negative power supply potential rises above a predetermined level with respect to the reference voltage, and when the negative power supply potential becomes lower than the predetermined level, Setting the pump circuit to a non-operating state, further switching the charge pump circuit between an operating state and a non-operating state when the reference voltage rises and the negative power supply potential becomes a level shallower than the predetermined level. Internal negative power supply generation circuit. In claim 2,
The charge pump control circuit sets an output level to a first level when the internal negative power supply potential is lower than the predetermined level with respect to the reference voltage, and sets the internal negative power supply potential to the predetermined level with respect to the reference voltage. An internal power supply generating circuit, comprising: a CMOS inverter for setting an output level to a second level when the level is higher than the level. In claim 2,
The reference voltage generation circuit includes a comparator that inverts in response to a rise in the external power supply, an output transistor that conducts by inverting the comparator, and a plurality of impedance units connected to the external power supply via the output transistor. And wherein the reference voltage is generated at a connection point of the plurality of impedance means. In claim 2,
The internal power supply generation circuit according to claim 1, wherein the reference voltage generation circuit includes a predetermined number of diode circuits once connected to the external power supply, and outputs the reference voltage to the other end of the diode circuit. In claim 1,
The internal power generation circuit according to claim 1, wherein the charge pump circuit includes an oscillator and a pump circuit that absorbs a charge from the negative power supply terminal according to a clock generated by the oscillator. In a semiconductor memory having a plurality of word lines, a plurality of bit lines, and memory cells provided at intersections thereof,
An internal power supply generation circuit according to any one of claims 1 to 6,
And a word driver for driving the word line to the internal negative power supply.

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