CN115424643A

CN115424643A - Fast switching word line driving circuit suitable for wide power supply voltage range

Info

Publication number: CN115424643A
Application number: CN202211064463.5A
Authority: CN
Inventors: 周雪萌; 韩雁; 倪明
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2022-09-01
Filing date: 2022-09-01
Publication date: 2022-12-02

Abstract

The invention discloses a fast switching word line driving circuit suitable for a wide power supply voltage range, which comprises a working mode and a standby mode. The working mode comprises a working mode charge pump power stage, a dynamic frequency modulation voltage stabilizing circuit, a power supply voltage detection module, a fast switching pre-charging module, two level shift circuits and a level transmission circuit; the standby mode includes a standby mode charge pump power stage and a SKIP modulation voltage regulator circuit. In addition, an ultra low power voltage reference source continuously provides a reference voltage in two modes. The power supply voltage detection module added in the working mode can reduce the overshoot and ripple of the output word line voltage in a wide power supply voltage range, and avoid unnecessary power loss; the added fast switching pre-charging module optimizes the switching time from the standby mode to the working mode according to the special requirement of the NOR Flash fast random reading.

Description

Fast switching word line driving circuit suitable for wide power supply voltage range

Technical Field

The invention relates to the technical field of nonvolatile memories, in particular to a fast switching word line driving circuit suitable for a wide power supply voltage range.

Background

The semiconductor memory is mainly divided into a volatile memory and a nonvolatile memory, the most popular nonvolatile memory is a Flash memory, and the Flash memory is divided into NOR Flash and NAND Flash, and compared with the mainstream NAND FLASH, NOR Flash, although the Flash memory has the defects of small capacity density, low writing and erasing speed, high price and the like, the Flash memory is difficult to eliminate by the market due to the fact that the Flash memory has higher reading speed, higher reliability and longer service life, and particularly, the NOR Flash is paid attention again due to the rapid development in the fields of 5G, the internet of things, bluetooth earphones, AMOLED screens, smart cars and the like in recent years.

Bias voltage is applied to a control grid electrode and a drain electrode of a NOR Flash storage unit in both writing and erasing operations of the NOR Flash storage unit, so that electrons can be injected into or extracted from a floating gate; the reading operation is to apply voltage on the control grid, and the on-off state of the channel can be used as the basis for judging the data values of '0' and '1'; the bias applied to the control gate is called the word line voltage and the bias applied to the drain is called the bit line voltage.

Because the NOR Flash only provides a single power supply voltage outside, and various operations of the memory need to provide different word line and bit line voltages, a boosting system on a chip is needed, and the charge pump is very suitable for the floating gate memory due to the advantages of low integration difficulty, moderate ripple, high efficiency and the like.

Nowadays, the fluctuation range for common supply voltages is generally maintained

. The design of the charge pump stage number usually needs to ensure that the target word line voltage value can be output under the lowest power supply voltage, so for a higher power supply voltage input, the fixed charge pump stage number inevitably causes a larger overshoot voltage and ripple of the output voltage, both of which can generate adverse effects on operations of the NOR Flash and also cause unnecessary power consumption waste.

The NOR Flash has the characteristic of fast random reading, so that when the NOR Flash is quitted from a standby mode and is recovered to a working mode needing to be read, the access time of a memory cannot be lost, and the time of tens of microseconds is needed for generating stable word line voltage by a reference voltage source, a charge pump and a voltage stabilizing circuit, so that the nanosecond-level random reading time of the NOR Flash cannot be met. In the standby mode, the word line voltage node is also required to be at a high voltage with a certain accuracy to meet the requirement of the word line voltage in the read operation. Of note are: when the word line voltage is restored to the working state from the standby state, because two different feedback loops charge the output node, some spurious transients will occur on the output node during switching, so that nanosecond-level access time is difficult to meet, and therefore the influence of the spurious transients needs to be reduced to the minimum at the moment of switching.

Disclosure of Invention

In order to enable the word line driving circuit to provide stable output voltage under a wide input power supply voltage range and not lose access time when the standby mode is recovered to the working mode, the invention provides a fast switching word line driving circuit suitable for the wide power supply voltage range.

A fast switching word line driver circuit for a wide range of power supply voltages,

the method comprises two modes of a working mode and a standby mode;

the circuit under the operating mode includes: the power stage of the charge pump in the working mode, the dynamic frequency modulation voltage stabilizing circuit, the power supply voltage detection module, the fast switching pre-charging module, the ultra-low power consumption voltage reference source, the level shift circuit 1, the level shift circuit 2, the level transmission circuit and the PMOS high-voltage device M1; a working mode charge pump power stage comprising a three-level cross-coupled charge pump and a one-level gated cross-coupled charge pump for generating a high voltage;

the dynamic frequency modulation voltage stabilizing circuit sequentially comprises a voltage-controlled oscillator, a non-overlapping clock generating circuit module, an error amplifier EA and resistor voltage dividers R1 and R2 and is used for outputting high voltage generated by the charge pump under all PVTs stably and with low ripple waves;

the power supply voltage detection module sequentially comprises a resistance voltage divider R3, a resistance voltage divider R4, a comparator COM1, a two-stage rectification inverter and an NMOS device M2 and is used for detecting input power supply voltage and generating signals CP _ ON and CP _ OFF;

the fast switching pre-charging module sequentially comprises a transmission gate, a buffer, an RC delay circuit, three inverters and an NAND gate, and is used for pre-charging the sampling point VFB _ ACT to the reference voltage VREF at the moment when the standby mode is restored to the working mode;

the ultra-low power consumption voltage reference source is used for providing reference voltage VREF for the error amplifier EA and the comparator COM 1;

the level shift circuit 1 is used for converting signals CP _ ON and CP _ OFF generated by the power supply voltage detection module into voltage signals CP _ ON _ HV and CP _ ON _ LHV with high level Vwl so as to control the ON-OFF of the gated cross-coupled charge pump and the level transmission circuit;

the level shift circuit 2 is used for converting enable signals ACT _ EN and ACT _ EN _ L into voltage signals ACT _ EN _ HV and ACT _ EN _ LHV with high level Vwl, and the ACT _ EN _ LHV signals are used for controlling the on-off of the PMOS high-voltage device M1;

the level transmission circuit is controlled by a signal CP _ ON _ HV and is used for transmitting the output voltage of the front three-stage cross-coupled charge pump;

the PMOS high-voltage device M1 is used as a switching tube and is controlled by a signal ACT _ EN _ LHV, and is used for switching on and off the current of the R1 and R2 branches;

the circuit in standby mode includes: the system comprises a standby mode charge pump power stage, an SKIP modulation voltage stabilizing circuit and an ultra-low power consumption voltage reference source;

a standby mode charge pump power stage comprising a DICKSON charge pump for generating a high voltage;

the SKIP modulation voltage stabilizing circuit sequentially comprises a current starvation type oscillator, a non-overlapping clock generating circuit, a comparator COM2, a subtraction counter, a rectifying inverter, a NOR gate and a diode voltage divider feedback circuit consisting of PMOS (P-channel metal oxide semiconductor) tubes M3-M10, and is used for maintaining output voltage in a standby mode;

and the ultra-low power consumption voltage reference source is used for providing a reference voltage VREF for the comparator COM2 and providing a bias voltage VBIAS for the current starvation type oscillator.

The gated cross-coupled charge pump in the working mode is provided with an NMOS high-voltage switching tube controlled by a control signal CP _ ON _ HV and a signal CP _ OFF _ HV to transmit or block clock signals ACT _ CLK and ACT _ CLKB.

The fast switching pre-flushing module performs RC delay on a signal ACT _ EN, and then generates pulse signals BUF and BUF _ L which are triggered simultaneously with the rising edge of the signal ACT _ EN and have the pulse width of tens of ns through a logic gate and a rectification inverter so as to control the self-bias current of a buffer and the on-off of a transmission gate.

In the error amplifier EA in the operating mode, the bias current of the comparator COM1 is provided by the reference current source in the operating mode controlled by the enable signals ACT _ EN and ACT _ EN _ L.

The bias current of the comparator COM2 in the standby mode is provided by a reference current source in the standby mode controlled by the enable signals STB _ EN and STB _ EN _ L.

In the standby mode, the PMOS devices M3 to M10 are high-voltage PMOS devices with the same width-length ratio and connected by diodes, the MOS tube works in a subthreshold region, and the static power consumption is in the nA level.

The PMOS device, the NMOS device, the MOS device, the switch MOS tube and the switch tube are all metal oxide semiconductor MOS transistors.

The high-voltage PMOS device, the high-voltage NMOS device and the high-voltage switch MOS tube are all lateral diffusion metal oxide semiconductor MOS transistors.

Compared with the prior art, the invention has the following beneficial technical effects:

in the working mode, aiming at wide power supply voltage input of 1.5 to 2.1V, the power level of the charge pump with the fixed series is adjusted to be the power level of the charge pump combined by the three-stage fixed charge pump and the one-stage gate-controlled charge pump, a power supply voltage detection module is added, and whether the gate-controlled charge pump works or not is determined by detecting the power supply voltage.

Meanwhile, the NOR Flash memory has high reading speed, and the random reading time is ns level, so that the access time is not allowed to be lost when the NOR Flash memory is recovered from a standby mode to a working mode.

Drawings

FIG. 1 is a schematic diagram of a fast switching word line driver circuit suitable for a wide power supply voltage range in accordance with the present invention.

Fig. 2 is a circuit schematic diagram of a gated cross-coupled charge pump in a charge pump power stage of the wordline driver circuit of the present invention in an operating mode.

Fig. 3 is a comparative diagram of overshoot voltages of a conventional word line driver circuit and an improved driver circuit of the present invention at different power supply voltages. Fig. 4 is a comparison diagram of output voltage ripples of a conventional word line driving circuit and an improved driving circuit in the invention under different power supply voltages.

FIG. 5 is a diagram showing the simulation result of the spark simulation when the word line driving circuit is restored to the operating mode in the standby mode.

Detailed Description

The invention is further described with reference to the following figures and detailed description, but the examples are not meant to be limiting.

Referring to the first drawing, a fast switching word line driver circuit suitable for a wide power supply voltage range according to the present invention includes two modes, i.e., an operating mode and a standby mode.

The circuit in the working mode comprises:

a working mode charge pump power stage comprising a three-level cross-coupled charge pump and a one-level gated cross-coupled charge pump for generating a high voltage;

the dynamic frequency modulation voltage stabilizing circuit sequentially comprises a voltage-controlled oscillator, a non-overlapping clock generating circuit module, an error amplifier EA and resistor voltage dividers R1 and R2, and is used for outputting the high voltage generated by the charge pump stably under all PVTs and with low ripples;

the power supply voltage detection module sequentially comprises a resistance voltage divider R3 and R4, a comparator COM1, a two-stage rectification inverter and an NMOS device M2 and is used for detecting input power supply voltage and generating signals CP _ ON and CP _ OFF;

and the PMOS high-voltage device M1 serving as a switching tube is controlled by a signal ACT _ EN _ LHV and is used for switching on and off the current of the branches of the resistors R1 and R2.

The circuit in standby mode comprises:

The fast switching word line driving circuit suitable for the wide power voltage range is characterized in that the fast switching pre-flushing module carries out RC delay on a signal ACT _ EN, and pulse signals BUF and BUF _ L which are triggered simultaneously with the rising edge of the ACT _ EN signal and have the pulse width of tens of ns are generated through a logic gate and a rectification inverter so as to control the buffer self-bias current and the on-off of a transmission gate.

According to the fast switching word line driving circuit applicable to the wide power supply voltage range, the error amplifier EA and the comparator COM1 in the working mode are provided with the bias current by the reference current source in the working mode controlled by the enable signals ACT _ EN and ACT _ EN _ L.

In the fast switching word line driving circuit applicable to a wide power supply voltage range, the bias current of the comparator COM2 in the standby mode is provided by the reference current source in the standby mode controlled by the enable signals STB _ EN and STB _ EN _ L.

The fast switching word line driving circuit applicable to the wide power voltage range is characterized in that in the standby mode, the PMOS devices M3-M10 are high-voltage PMOS devices which are connected by diodes and have the same width-length ratio, the MOS tube works in a subthreshold region, and the static power consumption is in the nA level.

The word line driving circuit suitable for fast switching of the wide power voltage range is characterized in that a PMOS device, an NMOS device, an MOS device, a switch MOS tube and a switch tube are all metal oxide semiconductor MOS transistors.

The fast switching word line driving circuit applicable to the wide power voltage range is characterized in that the high-voltage PMOS device, the high-voltage NMOS device and the high-voltage switch MOS transistor are all laterally diffused Metal Oxide Semiconductor (MOS) transistors.

The following describes an implementation method of the whole word line driving circuit:

when the word line driving circuit receives a command to start, the circuit enters an operating mode. The ACT _ EN signal is at a high level, the power supply voltage detection module starts to work, when the power supply voltage is higher than the rated voltage, CP _ OFF generated after the power supply voltage is divided by the resistor divider R3 and R4 and passes through the comparator COM1 together with the reference voltage VREF is at a high level, CP _ ON is at a low level, the two signals are converted into CP _ OFF _ HV and CP _ ON _ HV after passing through the level shift circuit 1, so that the gated cross-coupled charge pump is turned OFF, the level transmission circuit is controlled by the signal CP _ ON _ HV to be turned ON, and the output of the first three stages of cross-coupled charge pumps is pulled to Vwl; ON the contrary, when the power voltage is lower than the rated voltage, CP _ OFF is low level, CP _ ON is high level, the gated cross-coupled charge pump will be turned ON, and the four-stage charge pump works simultaneously to generate the output voltage Vwl. Meanwhile, since normal fluctuation of the power supply voltage is also a noise manifestation, the comparator COM1 adopts a hysteresis comparator to ensure that the circuit has a good noise margin. Finally, the output voltage Vwl regulates the high voltage generated by the charge pump through a dynamic frequency modulation system, so that the output voltage Vwl is stabilized at Vwl = VREF

(R1+R2)/R2。

After the working mode is finished, the circuit enters a standby mode, the working enabling signal ACT _ EN is changed into low level, the standby enabling signal STB _ EN is changed into high level, the DICKSON charge pump in the standby mode starts to work, and the output voltage node is continuously charged after being regulated by the SKIP modulation voltage stabilizing circuit, so that the output voltage is continuously kept near the voltage required by the reading operation. It is worth noting that the ultra-low power consumption reference voltage source, the current starvation oscillator, the MOS transistors in the comparator COM2 and the diode dividers M3 to M10 all work in the sub-threshold region because the standby mode must keep low power consumption.

After the standby mode lasts for a period of time, the system receives an instruction to work, and the system is recovered from the standby mode to enter the working mode. At this time, the operation mode enable signal ACT _ EN is restored to the high level, the standby mode enable signal STB _ EN becomes the low level, and since the NOR Flash needs to satisfy the ns-level random reading time, that is, the instant when the ACT _ EN signal is switched to the high level, the oscillator in the operation mode can make the output voltage satisfy the stable and accurate voltage value required by the reading operation within several working cycles. In the standby mode, since the high level of the signal ACT _ EN _ LHV is raised to Vwl after passing through the level shift circuit 2, the MOS transistor M1 is turned off, the resistor voltage division point VFB _ ACT is discharged to the ground potential, and once the operating mode is entered, the VFB _ ACT point needs to be recharged to the VREF voltage again, so that the feedback loop reaches a stable state. At the moment of the recovery from standby mode to active mode, the error amplifier will detect a high error input (stable reference voltage and ground voltage), which will cause the vco to generate an excessive frequency to charge the charge pump, causing spurious transients in the output word line voltage Vwl, which inevitably results in lost access time.

In order to solve the problem, the invention adds a fast switching pre-charging module for the moment when the standby mode is recovered to the working mode. The specific working mechanism is that the signal ACT _ EN is subjected to RC delay, and pulse signals BUF and BUF _ L which are triggered simultaneously with the rising edge of the ACT _ EN signal and have the delay of tens of ns are generated through a logic gate and a rectification inverter so as to control the buffer self-bias current and the on-off of a transmission gate; at the moment of entering a working mode, the buffer and the transmission gate force the point VFB _ ACT to be charged to the reference voltage VREF, so that a loop can be quickly stabilized, an output node can output an accurate voltage value within a plurality of clock cycles, redundant switching power consumption cannot be generated, and the requirement of ns-level access time can be met. The BUF signal will turn off the buffer and transmission gate to stop charging the point VFB _ ACT after the loop has stabilized.

Fig. 2 is a circuit diagram of a gated cross-coupled charge pump in a charge pump power stage of the wordline driver circuit of the present invention in an operating mode. The reason for choosing cross-coupled charge pumps is: compared with other types of charge pumps, the charge pump has the advantages of simple structure, small output voltage ripple, no port voltage of each switching tube exceeding the power supply voltage VDD, suitability for low-voltage processes and the like. The NMOS devices MN1 and MN2 and the PMOS devices MP1 and MP2 of the switching tubes are alternately conducted under the drive of two inverted clock signals to charge the pump capacitors C1 and C2 so as to realize the lifting of the output voltage Vout, and the PMOS devices MP10 and MP20 are added to ensure that the substrate potentials of the MP1 and MP2 are always in a high level, so that the reverse leakage current is inhibited to improve the pump efficiency. Once the clock signal can not be input into the capacitor, the charge pump can not carry out boosting operation, so that NMOS high-voltage switch tubes MN3 and MN5 of which the grid voltages are controlled by the signal CP _ ON _ HV and NMOS high-voltage switch tubes MN4 and MN6 of which the grid voltages are controlled by the signal CP _ OFF _ HV are added to the clock signals CLK and CLKB ON the basis of the original charge pump, and therefore the power supply voltage detection module realizes the control of the ON-OFF of the gated cross-coupled charge pump.

Fig. 3 is a schematic diagram showing the overshoot voltage comparison of the conventional word line driving circuit and the improved driving circuit of the present invention under different power supply voltages. It has been found that the overshoot voltage is significantly improved over the entire supply voltage range, especially for supply voltages above 1.8V, since the gated cross-coupled charge pump is turned off at supply voltage inputs above 1.8V, so that only the first three charge pumps are operating, thus optimizing the output voltage overshoot.

Fig. 4 is a schematic diagram showing the comparison of output voltage ripples of the conventional word line driving circuit and the improved driving circuit of the present invention under different power supply voltages. For a load circuit driven by a charge pump, voltage ripples are a noise expression, if the voltage ripples are too large, the load circuit cannot work normally, and for a Flash memory, erasing and programming of a storage unit can be influenced, and a threshold voltage deviates from an expected value, so that data reading errors occur. For a purely capacitive load in the present invention, the ripple is derived from the ripple caused by the charging and discharging of the unregulated charge pump and the ripple at the output of the charge pump caused by the variation of the output of the error amplifier, so the formula of the ripple can be expressed as:

（1）；

where Vr is the voltage ripple and where,

is the output current of the charge pump and,

is the current that is consumed by the load,

in order to be a delay of the charge pump,

is negativeAnd a load capacitor. Since the present invention is directed to a purely capacitive load, only the resistor voltage division will bring a small part of the current, which is much smaller than the charge current of the charge pump, so that it can be ignored, and therefore the above formula can be approximated as

（2）；

According to the model of the charge pump

（3）；

Wherein

Is the output resistance of the charge pump, and is obtained by substituting equation (3) into equation (2)

（4）；

It can be seen that the ripple voltage is proportional to the difference between the maximum value of the output voltage of the charge pump and the regulated voltage value, so that the overshoot voltage is optimized. As can be seen from the fourth diagram, the improved structure of the present invention optimizes the voltage ripple at different power supply voltages compared to the conventional structure.

FIG. 5 is a diagram showing the simulation result of the spark simulation transient when the word line driving circuit is restored to the operating mode in the standby mode. When the working mode enable signal ACT _ EN is randomly triggered to become high level, the standby mode is ended, and the system enters the working mode. The invention generates BUF signal pulse (about 10ns low level) triggered simultaneously with the rising edge of the ACT _ EN signal through RC time delay and a logic gate, and the BUF signal pulse is used for controlling a buffer and a transmission gate, so that at the moment of entering a working mode, a resistor voltage division sampling point VFB _ ACT is forced to be charged to a reference voltage VREF, the output VOUT _ EA of an error amplifier can be rapidly switched to control the frequency of a voltage-controlled oscillator, a loop can be rapidly stabilized, and the output voltage can be stabilized to an accurate voltage value VOUT within a few oscillation cycles of a clock signal ACT _ CLK. After the output voltage is stable, the BUF signal becomes high level, the buffer and the transmission gate are turned off, and the sampling point VFB _ ACT is not charged any more. It can be seen from the figure that about 12ns is required from the rise of the signal ACT _ EN to the high level to the stabilization of the output voltage, the access time is hardly lost, the stray transient state and the power consumption loss caused by switching are not caused, and the requirement of the NOR Flash for fast random reading is completely met.

The embodiments in the above description can be further combined or replaced, and the embodiments are only described as preferred examples of the present invention, and do not limit the concept and scope of the present invention, and various changes and modifications made to the technical solution of the present invention by those skilled in the art without departing from the design concept of the present invention belong to the protection scope of the present invention. The scope of the invention is given by the appended claims and any equivalents thereof.

Claims

1. A fast switching word line driver circuit for a wide range of power supply voltages,

the method comprises two modes of a working mode and a standby mode;

the circuit in the working mode comprises: the power stage of the charge pump in the working mode, the dynamic frequency modulation voltage stabilizing circuit, the power supply voltage detection module, the fast switching pre-charging module, the ultra-low power consumption voltage reference source, the level shift circuit 1, the level shift circuit 2, the level transmission circuit and the PMOS high-voltage device M1; a working mode charge pump power stage comprising a three-level cross-coupled charge pump and a one-level gated cross-coupled charge pump for generating a high voltage;

the ultra-low power consumption voltage reference source is used for providing a reference voltage VREF for the error amplifier EA and the comparator COM 1;

and the ultra-low power consumption voltage reference source is used for providing a reference voltage VREF for the comparator COM2 and providing a bias voltage VBIAS for the current starvation oscillator.

2. A fast switching word line driver circuit for a wide range of supply voltages as recited in claim 1 wherein: the gated cross-coupled charge pump in the working mode is provided with an NMOS high-voltage switching tube controlled by a control signal CP _ ON _ HV and a signal CP _ OFF _ HV to transmit or block clock signals ACT _ CLK and ACT _ CLKB.

3. A fast switching wordline driver circuit according to claim 1 adapted for a wide supply voltage range, wherein: the fast switching pre-flushing module delays the signal ACT _ EN by RC, and generates pulse signals BUF and BUF _ L with the pulse width of tens of ns, which are triggered simultaneously with the rising edge of the signal ACT _ EN, through a logic gate and a rectifying inverter so as to control the self-bias current of a buffer and the on-off of a transmission gate.

4. A fast switching wordline driver circuit according to claim 1 adapted for a wide supply voltage range, wherein: in the error amplifier EA in the operating mode, the bias current of the comparator COM1 is provided by the reference current source in the operating mode controlled by the enable signals ACT _ EN and ACT _ EN _ L.

5. A fast switching wordline driver circuit according to claim 1 adapted for a wide supply voltage range, wherein: the bias current of the comparator COM2 in the standby mode is provided by a reference current source in the standby mode controlled by the enable signals STB _ EN and STB _ EN _ L.

6. A fast switching wordline driver circuit according to claim 1 adapted for a wide supply voltage range, wherein: in the standby mode, the PMOS devices M3 to M10 are high-voltage PMOS devices with the same width-length ratio and connected by diodes, the MOS tube works in a subthreshold region, and the static power consumption is in the nA level.

7. A fast switching word line driver circuit for a wide range of supply voltages as recited in claim 1 wherein: the PMOS device, the NMOS device, the MOS device, the switch MOS tube and the switch tube are all metal oxide semiconductor MOS transistors.

8. A fast switching word line driver circuit for a wide range of supply voltages as recited in claim 1 wherein: the high-voltage PMOS device, the high-voltage NMOS device and the high-voltage switch MOS tube are all lateral diffusion metal oxide semiconductor MOS transistors.