JP2004129013A - Method and device for modulation, method and device for demodulation, and modulation and demodulation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To a modulating method and device for realizing transmission with transmitting power smaller than that of 2<SP>(n + 1)</SP>phase modulation by using, for example, bandwidth between A and A/2 to be able to obtain an equivalent coding error rate in the case of requiring A bandwidth in 2<SP>n</SP>phase modulation and half of A bandwidth in 2<SP>(n + 1)</SP>phase modulation. <P>SOLUTION: In this modulating method for making a binary signal of length b for the number N of phases (integer other than power of 2) of phase modulation correspond to an N-ary phase signal of length n and transmitting the binary signal of length b, the average error rate of each bit of the binary signal of length b is associated with all errors of distance 1 of the N-ary phase signal of length n so as to minimize the average error rate. In the case of a three-phase phase modulation system, a data converting part 101 for converting a binary signal of length 3 into a ternary signal of length 2 allocates ternary signals of length 2 (0, 0), (0, 1), (0, 2), (1, 0), (1, 1), (1, 2), (2, 0) and (2, 1) to binary signals of length 3 (0, 0, 0), (0, 0, 1), (0, 1, 1), (1, 1, 0), (1, 1, 1), (0, 1, 0), (1, 0, 0) and (1, 0, 1), respectively. <P>COPYRIGHT: (C)2004,JPO

Description

のうちのいずれかの組が割り当てられる。
【００１７】
かかる本発明によれば、２相位相変調では１００ＭＨｚの帯域幅を、４相位相変調では５０ＭＨｚの帯域幅を必要とする場合に、たとえば、約６７ＭＨｚの帯域幅を用いて、同等の符号誤り率を得るために、４相位相変調よりも、約１．３ｄＢだけ少ない送信電力で実現する。
【００１８】
本発明の他のアスペクトに係る変調装置は、位相変調の相数Ｎに対する長さｂの二値信号を入力し、予め定められた変換規則を参照して、長さｎのＮ値信号に変換するデータ変換回路（例えば図３の１０１）と、前記データ変換回路からのｎ個のＮ値信号の並列出力を多重化して出力する並列直列変換回路（例えば図３の１０２）と、前記並列直列変換回路の出力を順次入力しＮ相位相変調して出力する位相変調器（例えば図３の１０３）と、を備えている。長さｎのＮ値位相信号の全ての距離１の誤りに対して、長さｂの二値信号の各ビットの平均誤り率を小さくするように、長さｂの二値信号と長さｎのＮ値信号との対応付けが行われる。
【００１９】
本発明の他のアスペクトに係る復調装置は、Ｎ相位相変調された変調波を入力しｎ個のＮ値信号を出力する位相復調器（例えば図８の２０１）と、前記位相復調器からのｎ個のＮ値信号の出力を並列化して出力する直列並列変換回路（例えば図８の２０２）と、長さｎのＮ値信号を入力し、長さｎのＮ値信号と、位相変調の相数Ｎに対する長さｂの二値信号との対応関係を規定した変換規則を参照して、長さｂの二値信号に変換するデータ逆変換回路（例えば図８の２０３）と、を備えている。本発明においては、長さｎのＮ値信号の全ての距離１の誤りに対して、長さｂの二値信号の各ビットの平均誤り率を小さくするように、長さｂの二値信号と長さｎのＮ値信号との対応付けが行われる。
【００２０】
本発明に係る変復調システムは、上記した変調装置と復調装置を備えて構成される。
【００２１】
【発明の実施の形態】
本発明の実施の形態について図面を参照して以下に説明する。図１は、本発明の一実施の形態を説明するための図である。図１には、３相位相変調方式における長さ３（３ビット）の二値信号を、長さ２の三値信号に対応させて伝送する位相変調方式において、二値信号と三値信号の関係が示されている。
【００２２】
第１列の「二値信号（ｂ_２，ｂ_１，ｂ_０）」に対して、第２列に示す「三値信号（ｔ_１，ｔ_０）」が割り当てられている。長さ３の二値信号（０，０，０）、（０，０，１）、（０，１，１）、（１，１，０）、（１，１，１）、（０，１，０）、（１，０，０）、（１，０，１）に対して、長さ２の三値信号（０，０）、（０，１）、（０，２）、（１，０）、（１，１）、（１，２）、（２，０）、（２，１）がそれぞれ割り当てられている。なお、三値信号の送信されない信号である（２，２）は、二値信号で（１，１，１）としている。
【００２３】
物理的伝送路では、三値信号が伝送されており、符号誤りは、第１次的には、三値信号の上で起きる。
【００２４】
図１において、たとえば、三値信号（ｔ_１，ｔ_０）＝（０，０）について、「三値信号の＋１誤り」の欄の「誤り後の値上ｔ_１、下ｔ_０」に示すように、ｔ_１に「＋１誤り」があると、三値信号（ｔ_１，ｔ_０）＝（１，０）、「二値信号の誤り後の値」は（１，１，０）、「二値信号の誤りの値」は（１，１，０）から本来の二値信号（０，０，０）を差し引いた（１，１，０）となり、ｔ_０に「＋１誤り」があると、三値信号（ｔ_１，ｔ_０）＝（０，１）、「二値信号の誤り後の値」は（０，０，１）、「二値信号の誤りの値」は（０，０，１）から（０，０，０）を差し引いた（０，０，１）となる。以下の行についても同様とされ、最下行の三値信号（ｔ_１，ｔ_０）＝（２，１）について、「三値信号の＋１誤り」の欄の「誤り後の値上ｔ_１、下ｔ_０」に示すように、ｔ_１に「＋１誤り」があると、三値信号（ｔ_１，ｔ_０）＝（０，１）、「二値信号の誤り後の値」は（０，０，１）、「二値信号の誤りの値」は（０，０，１）から本来の二値信号（１，０，１）を差し引いた（１，０，０）となり、ｔ_０に「＋１誤り」があると、三値信号（ｔ_１，ｔ_０）＝（２，２）、「二値信号の誤り後の値」は（１，１，１）、「二値信号の誤りの値」は（１，１，１）から（１，０，１）を差し引いた（０，１，０）となる。
【００２５】
三値信号（ｔ_１，ｔ_０）＝（０，０）について、「三値信号の−１誤り」の欄の「誤り後の値上ｔ_１、下ｔ_０」に示すように、ｔ_１に「−１誤り」があると、三値信号（ｔ_１，ｔ_０）＝（２，０）、「二値信号の誤り後の値」は（１，０，０）、「二値信号の誤りの値」は（１，０，０）から本来の二値信号（０，０，０）を差し引いた（１，０，０）となり、ｔ_０に「−１誤り」があると、三値信号（ｔ_１，ｔ_０）＝（０，２）、「二値信号の誤り後の値」は（０，１，１）、「二値信号の誤りの値」は（０，１，１）から（０，０，０）を差し引いた（０，１，１）となる。他の行についても同様とされる。
【００２６】
図１に示す例では、長さ３（３ビット）の二値信号（１，１，１）を伝送する場合、三値信号としては、（１，１）が割り当てられる。三値信号（ｔ_１，ｔ_０）の始めの値であるｔ_１のみに、「＋１誤り」が生じた時、受信側での受信信号は、（２，１）となる。
【００２７】
このため、復調後の二値信号（図８の２４）として、３列の二値信号（（１，０，１）が出力され、二値信号（ｂ_２，ｂ_１，ｂ_０）のうちｂ_１にのみ、誤りを生じる。
【００２８】
図１に示した、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）と、長さ２の三値信号（ｔ_１，ｔ_０）の対応例の場合、伝送される三値信号の全ての誤りに対して、二値信号の平均誤り率は、最小化されている。すなわち最適な割り当てとされる。
【００２９】
つまり、三値信号の誤り率Ｐ_３に対して、二値信号の誤り率Ｐ_ｂは、以下に説明されるように、次式（１）で表される。
【００３０】
Ｐ_ｂ＝０．８７５Ｐ_３　　　　…（１）
【００３１】
ここで、図１において、長さ２の三値信号（ｔ_１，ｔ_０）のｔ_１の誤りに対して、二値信号（ｂ_２，ｂ_１，ｂ_０）のｂ_２、ｂ_１、ｂ_０に発生する符号誤りの総数は、「二値信号の誤り後の値」から、それぞれ、
ｔ_１の「＋１の誤り」に対して５、４、２個、
ｔ_１の「−１の誤り」に対して２、３、５個
である。
ｔ_１の「＋１の誤り」、「−１の誤り」を纏めると、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）の各ビットｂ_２、ｂ_１、ｂ_０に発生する符号誤りは、７、７、７個となる。
【００３２】
また、長さ２の三値信号（ｔ_１，ｔ_０）のｔ_０の誤りに対して、二値信号（ｂ_２，ｂ_１，ｂ_０）のｂ_２、ｂ_１、ｂ_０に発生する符号誤りは、それぞれ、
ｔ_０の「＋１の誤り」に対して５、４、１個、
ｔ_０の「−１の誤り」の対して２、３、６個
である。
ｔ_０の「＋１の誤り」と、「−１の誤り」を纏めると、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）の各ビットｂ_２、ｂ_１、ｂ_０に発生する符号誤りは、７、７、７個の誤りとなる。
【００３３】
したがって、その合計は、
７＋７＋７＋７＋７＋７＝４２　　…（２）
すなわち、４２個の誤りとなる。
【００３４】
三値符号の誤り率に対する二値信号の誤り率の比を求めるには、この「４２」を、
８ｘ２ｘ３＝４８　　　　　　　　…（３）
で除して、
４２／４８＝０．８７５　　　　　　…（４）
となる。
【００３５】
式（３）において、「８」は、三値信号の誤り位置の数、「２」は＋１、−１の誤りの場合の数、「３」は、二値信号のビット数に対応している。
【００３６】
図２は、３相位相変調方式における、長さ３（３ビット）の二値信号（（０，０，０），（０，０，１），（０，１，１），（１，１，０），（１，１，１），（０，１，０），（１，０，０），（１，０，１））
を長さ２の三値位相信号
（（０，０），（０，１），（０，２），（１，０），（１，１），（１，２），（２，０），（２，１））
に対応させて伝送する位相変調方式において、長さ３の二値信号と長さ２の三値信号の対応に関する、二値信号の平均誤り率（すなわち、長さ２の三値信号の全ての距離１の誤りに対して長さ３の二値信号の各ビットの平均誤り率）を最小化した場合の全ての対応（図１の対応関係を含む）を示したものである。なお、これらは、長さ２の三値信号（０，０）に対して、長さ３（３ビット）の二値信号を（０，０，０）とした場合であり、長さ３（３ビット）の二値信号を（０，０，１），　（０，１，０），　（０，１，１），　（１，０，０），　　（１，０，１），　（１，１，０），　（１，１，１）とした場合には、長さ２の三値信号に対応する長さ３（３ビット）の二値信号の全てに対して、（０，０，１），　（０，１，０），　（０，１，１），　（１，０，０），　　（１，０，１），　（１，１，０），　（１，１，１）のいずれかを排他的論理和で加えることとする。
【００３７】
図２には、第１列から第２４列の場合の対応関係が示されている。すなわち、長さ２の三値信号（ｔ_０，ｔ_１）の８個の組（（０，０）、（０，１）、（０，２）、（１，０）、（１，１）、（１，２）、（２，０）、（２，１））に対して、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）８個を１列として、

の第１乃至第２４の列からなる。図２の二値信号の第１列は図１の対応関係に相当する。長さ２の三値信号（０，０）、（０，１）、（０，２）、（１，０）、（１，１）、（１，２）、（２，０）、（２，１）に対して上記２４列のうち、いずれかの列の長さ３の二値信号（ｂ２，ｂ１，ｂ０）のそれぞれに、長さ３の二値信号（ｖ２，ｖ１，ｖ０）（ただし、（ｖ２，ｖ１，ｖ０）は、（０，０，１）、（０，１，０）、（０，１，１）、（１，０，０）、（１，０，１）、（１，１，０）、（１，１，１）のうちのいずれか）を加え、（ｂ２＋ｖ２，ｂ１＋ｖ１，ｂ０＋ｖ０）（ただし、演算記号＋は排他的論理和を表す）として、各ビットを割り当てることで、長さ３の二値信号と長さ２の三値信号との間での変換を行うようにしてもよい。
【００３８】
【実施例】
次に、上記した位相変調を行う装置の一実施例について説明する。以下では、３相位相変調における３桁（長さ３）の二値信号を２桁（長さ２）の三値信号に割り当てる構成について説明する。図３は、本発明に係る変調装置の一実施例の構成を示す図である。図３を参照すると、この変調装置は、３つの二値信号データを入力とし２つの三値信号を出力するデータ変換回路１０１と、データ変換回路１０１から並列に出力される２つの三値信号を入力し１本のシリアル信号に変換する並列直列変換回路１０２（多重化回路）と、並列直列変換回路１０２の出力を受けて、３相位相変調を行い変調波を出力する位相変調器１０３と、データ変換の制御を行う制御回路１０４とを備えている。データ変換回路１０１は、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）を入力し、長さ２の三値信号（ｔ_１，ｔ_０）を出力する。データ変換回路１０１内に、図２に示した、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）と長さ２の三値信号（ｔ_１，ｔ_０）間の対応関係（変換規則）を与えるルックアップテーブル等の記憶装置を備えた構成としてもよい。また、制御回路１０４は、データ変換回路１０１内のルックアップテーブルの内容（変換規則）を、適宜変更する構成としてもよい。あるいは、図２等に示した変換規則を格納した記憶装置を、制御回路１０４側に設ける構成としてもよい。データ変換回路１０１において行われる変換は、例えば、図２等に示した、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）と、長さ２の三値信号（ｔ_１，ｔ_０）の対応例にしたがって行われ、この場合、伝送される三値信号の全ての誤りに対して、二値信号の平均誤り率は、最小化されている。
【００３９】
図４は、本発明の一実施例の動作を説明するためのタイミング図である。まず、位相変調方式の動作について、図３及び図４を用いて説明する。入力のデータ列は、符号１１で示す３列の二値信号で表される。
【００４０】
３列の二値信号１１は、データ変換回路１０１で、各々三値を表す信号１２Ａ、１２Ｂに変換される。
【００４１】
三値の信号１２Ａ及び１２Ｂは、直列並列変換回路１０２で時間軸上で多重化され、三値を表す時間軸上で多重化された信号１３に変換される。
【００４２】
このとき、２系統あった三値の信号１２Ａ、１２Ｂは、時間多重されているために、時間軸上で圧縮され、１系統の信号１３となる。
【００４３】
三値を表す信号１３は、位相変調器１０３で変調され、３個の信号点（図４（Ｂ）参照）を有する位相変調波１４となる。
【００４４】
一方、入力された３列（長さ３）の二値信号と、３相位相変調された変調信号との対応については、例えば図５に例示されている対応関係に従って実行される。長さ３の二値信号と長さ２の三値信号の対応は、長さ３の二値信号（０，０，０），　（０，０，１），　（０，１，０），　（０，１，１），　（１，０，０），　（１，０，１），　（１，１，０），　（１，１，１）に対して、（０，０），　（０，１），　（０，２），　（１，０），　（１，１），　（１，２），　（２，０），　（２，１）が割り当てられる。なお、図５に示されている、二値信号と三値信号の対応は、図２に示した、最適化された対応以外のものも含まれ、三値信号に対して、二値信号を、自然２進信号として割り当てが行われている。本発明において、二値信号と三値信号の対応は、長さ２の三値信号の全ての距離１の誤りに対して、長さ３の二値信号の各ビットの平均誤り率を最小とする割り当て（図２の第１列から第２４列の割り当て）にのみ限定されるものでなく、平均誤り率を小さくする割り当ても含む。
【００４５】
すなわち、図５に示す例では、２つの変調シンボルの内、第１の変調シンボルは、「０」から「２」までの値を取る。
【００４６】
第１の変調シンボルが「０」から「１」までの間、第２の変調シンボルは「０」から「２」までの値を採り、第１の変調シンボルが「２」の時は第２の変調シンボルは「０」から「１」までの２つの値を採る。
【００４７】
このき、全信号種類は、
２ｘ３＋１ｘ２　　　　　　　…（５）
であり、「８」に等しい。
【００４８】
式（５）の第１項の「２ｘ３」の前半の「２」は、第１の変調シンボルが「０」から「１」までを取ることを示しており、後半「３」は、第１の変調シンボルのそれぞれに第２の変調シンボルが「０」から「２」までを取ることを表している。
【００４９】
また、式（６）の第２項の「１ｘ２」の前半の「１」は、第１の変調シンボルが「２」の一つの値を採ることを示しており、後半の「２」は、第２の変調シンボルが「０」から「１」までを取ることを表している。
【００５０】
更に、３列の二値信号である入力信号が、（０，０，０）から（１，１，１）まで変化した場合には、変調波の動作として、図５（Ａ）乃至図５（Ｈ）に示した信号図で規定される変調波が順次、出力される。
【００５１】
図５（Ａ）に示すように、３列の二値信号である入力信号（０，０，０）に対して、変調信号（変調波）は（０，０）であり、図５（Ｂ）に示すように、３列の二値信号である入力信号（０，０，１）に対して、変調信号は（０，１）であり、以下、図５（Ｈ）に示すように、３列の二値信号である入力信号（１，１，１）に対して、変調信号は（２，１）である。すなわち、入力信号の（０，０，０）から、（１，１，１）に対して、このとき、第１の変調シンボルが、「０」から「１」までの間は、第２の変調シンボルは、「０」から「２」までの値を取り、第１の変調シンボルが「２」の時は、第２の変調シンボルは、「０」から「１」までの値を取る。
【００５２】
このとき、全信号種類は、
２ｘ３＋１ｘ２　　　　　　　…（６）
であり、「８」に等しい。
【００５３】
以上説明したように、本実施例においては、３列の２値データ列を、２つの変調シンボル（信号）に対応させた後に、その２つの変調シンボルを、時間軸上で、多重化することで、１つの変調シンボルで、等価的に、１．５列の２値データ列を伝送している。
【００５４】
上記実施例で説明したように、三値信号に対する二値信号の割当を最適化（二値信号の各ビットの平均誤り率を最小化）することで、１０^−６の誤り率を得るのに、
Ｅｂ／Ｎｏ＝１０．２２（ｄＢ）　　　…（７）
（ただし、Ｅｂは１ビット当たりのエネルギー、Ｎｏは雑音電力密度を表す）
である。
【００５５】
一方、三値信号に対する二値信号の割当の最適化を行わない場合、最悪の場合には、三値信号の誤り率に対する二値信号の誤り率の比が１．３７５まで増加し、
Ｅｂ／Ｎｏ＝１０．３６（ｄＢ）　　　…（８）
まで増加する。
【００５６】
図６は、本発明と、比較例におけるＥｂ／Ｎｏに対するビット誤り率特性を示す図である。図６には、２−ＰＳＫ（Ｐｈａｓｅ　Ｓｈｉｆｔ　Ｋｅｙｉｎｇ）／４−ＰＳＫ（比較例）と、本発明に係る３−ＰＳＫの最良値と、３−ＰＳＫの最悪値のビット誤り率特性が示されている。
【００５７】
以上、３相位相変調における３桁の二値信号を２桁の三値信号に割り当てる場合に関して、具体的な実施例について説明した。
【００５８】
次に、本発明の別の実施例として、図７に示す変調方式に対して本発明を適用することが出来る。図７には、位相変調の相数Ｎ、二値の桁数ｂ、Ｎ値の桁数、桁数の比ｂ／ｎが一覧で示されている。例えば、３相位相変調（Ｎ＝３）においては、１１桁の二値信号を７桁の三値信号に割り当てる場合、１９桁の二値信号を、１２桁の三値信号に割り当てる場合等がある。
【００５９】
同様に、５相位相変調、６相位相変調、７相位相変調等の場合についても、図７に示す変換に対して本発明を適用することが出来る。例えば、位相変調の相数Ｎ＝５に対して、（二値信号の桁数ｂ、Ｎ値の桁数ｎ）は、（９、４）、（１６、７）、（２３、１０）等とされる。位相変調の相数Ｎ＝６に対して、（二値信号の桁数ｂ、Ｎ値の桁数ｎ）は、（５、２）、（１８、７）、（２３、９）等とされる。位相変調の相数Ｎ＝７に対して、（二値信号の桁数ｂ、Ｎ値の桁数ｎ）は、（８、３）、（１１、４）、（２５、９）等とされる。桁数の比ｂ／ｎは図７の右端の欄にそれぞれ記載された通りである。
【００６０】
本発明の他の実施例について説明する。上記のように変調されて送信された信号を受信し、変調信号を復調する復調装置は、例えば図８に示すような構成とされる。図８を参照すると、この復調装置は、変調波（変調信号）２１を３相位相復調し、三値を表す信号２２を出力する位相復調器２０１と、位相復調器２０１からの２つの三値を表す信号２２を直列並列変換して出力する直列並列変換回路２０２と、直列並列変換回路２０２から第一、第二の三値を表す信号２３Ａ、２３Ｂを入力し、例えば図１、図２に示した変換規則に従い、３列の二値信号２４を出力するデータ逆変換回路２０３と、データ逆変換を制御する制御回路２０４を備えて構成される。データ逆変換回路２０３内に、図２等に示した、長さ２の三値信号（ｔ_１，ｔ_０）と長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）間の対応関係（変換規則）を与えるルックアップテーブル等の記憶装置を備えた構成としてもよい。制御回路２０４は、データ逆変換回路２０３内の変換規則（ルックアップテーブルの内容）を適宜変更する構成としてもよい。あるいは、ルックアップテーブルを制御回路２０４側に設ける構成としてもよい。
【００６１】
本発明においては、図３に示した変調装置と、図８に示した復調装置とを備えた変復調システムを構成してもよい。図３のデータ変換回路１０１と、図８のデータ逆変換回路２０３では、長さ３の二値信号（ｂ_２，ｂ_１，ｂ_０）と長さ２の三値信号（ｔ_１，ｔ_０）との対応（変換規則）として、例えば図２に示した第１乃至第２４列のうちの一つが共通に用いられる。すなわち、二値信号と三値信号との割当を最適化することで、Ｅｂ／Ｎｏに対する、誤り率の値を改善することができる。
【００６２】
以上、本発明を上記実施例に即して説明したが、本発明は上記実施例の構成にのみ限定されるものでなく、本願特許請求の範囲の各請求項の範囲内で、当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
【００６３】
【発明の効果】
以上説明したように、本発明によれば、２^ｎ位相変調ではＡの帯域幅を、２^{（ｎ＋１）}位相変調ではＡの半分の帯域幅を必要とする場合に、たとえば、ＡとＡ／２の間の帯域幅を用いて同等の符号誤り率を得ることを可能とし、２^{（ｎ＋１ ）}位相変調よりも、少ない送信電力での伝送を実現することができる、という効果を奏する。
【００６４】
また、本発明は、二値信号をＮ値信号に割り当てる際の割り当てについて、Ｅｂ／Ｎｏに対する、誤り率の値を改善することができる、という効果を奏する。
【図面の簡単な説明】
【図１】本発明の一実施の形態を説明するための図である。
【図２】本発明の一実施の形態における二値信号と三値信号の対応を示す図である。
【図３】本発明の一実施例の変調装置の構成を説明するための図である。
【図４】（Ａ）は、本発明の一実施例の動作を説明するためのタイミング図、（Ｂ）は、３相位相変調における３個の信号点を示す図である。
【図５】本発明の一実施例を説明するための信号図である。
【図６】本発明の一実施例と比較例のビット誤り率特性を示す図である。
【図７】本発明の他の実施例を説明するための図である。
【図８】本発明の他の実施例をなす復調装置の構成を示す図である。
【符号の説明】
１１　３列二値信号
１２Ａ　第一の三値を表す信号
１２Ｂ　第二の三値を表す信号
１３　時間多重された三値を表す信号
１４　変調波（信号）
１０１　データ変換回路
１０２　並列直列変換回路
１０３　位相変調器
１０４　制御回路
２０１　位相復調器
２０２　直列並列変換回路
２０３　データ逆変換回路
２０４　制御回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a modulation method and apparatus, and in particular, for a predetermined integer value N other than a power of two, a binary signal having a predetermined length b corresponds to an N-valued phase signal having a predetermined length n. The present invention relates to a modulation method and an apparatus for transmitting the signal and a demodulation method and a demodulation apparatus.
[0002]
[Prior art]
Conventionally, particularly in phase modulation used in satellite communication, digital microwave communication, and the like, n such as two-phase modulation, four-phase modulation, or eight-phase modulation is defined as a positive integer and 2ⁿPhase modulation has been used.
[0003]
In satellite communication, digital microwave communication, and the like, generally, for simplicity of the circuit, two-phase modulation, four-phase modulation, eight-phase modulation, or the like, where n is a positive integer, 2ⁿPhase modulation is used.
[0004]
However, with recent advances in integrated circuit technology, the difficulty of implementation due to circuit complexity is being reduced.
[0005]
Further, there is an increasing demand for effective use of frequency and effective use of transmission power.
[0006]
In order to meet the demand for effective use of transmission power and frequency, modulation techniques generally use twoⁿA phase modulation method is used (for example, see Non-Patent Document 1).
[0007]
[Non-patent document 1]
"Modulation and demodulation of digital wireless communication" (Yoichi Saito, February 1996, published by the Institute of Electronics, Information and Communication Engineers)
[0008]
Therefore, 2ⁿIn the phase modulation, for example, when R (bps) (bit @ persecond) is transmitted as binary data, if n = 1, a two-phase phase modulation method is used, and one bit of information is transmitted in one symbol. The data is transmitted and transmitted using a bandwidth corresponding to R / 1 = R (Hz). That is, the occupied bandwidth B that requires a two-phase modulation signal with a transmission rate R (bps) that is ideally (rectangular) band-limited is R (Hz). When n = 2, four-phase modulation is performed, and transmission is performed using a bandwidth corresponding to R / 2 (Hz).
[0009]
As a result, for example, when the available bandwidth is 80 MHz and the required transmission capacity is 100 MHz bandwidth is required in the two-phase modulation, the bandwidth is 50 MHz in the four-phase modulation. Is required. If four-phase modulation is used and a bandwidth of 50 MHz is used, the available bandwidth is 80 MHz, so the bandwidth is left over.
[0010]
Furthermore, in order to realize the same code error rate in the four-phase phase modulation as compared with the two-phase phase modulation, the required C / N (carrier / noise ratio) requires about 3 dB more, so the transmission is required. There is also a problem that it is necessary to increase electric power.
[0011]
[Problems to be solved by the invention]
Therefore, the object of the present invention is toⁿ(N is a positive integer) In phase modulation, the bandwidth of A is 2^{(N + 1)}When half the bandwidth of A is required in the phase modulation, for example, it is possible to obtain the same code error rate using a bandwidth between A and A / 2,^{(N + 1)}It is an object of the present invention to provide a method, an apparatus and a system for realizing transmission with less transmission power than phase modulation.
[0012]
In addition, the present invention improves a value of a bit error rate (BER) with respect to Eb / No (Eb is energy per bit, No is noise power density) for allocation when a binary signal is allocated to an N-level signal. It is also an object to provide methods and apparatus and systems.
[0013]
[Means for Solving the Problems]
According to one aspect of the present invention, the present invention achieves the above object. In the present invention, N is a predetermined integer value other than a power of 2, and a binary signal having a predetermined length b with respect to the number N of phases of phase modulation. A modulation method for transmitting a signal corresponding to an N-valued phase signal having a predetermined length n, wherein a data converter for converting a binary signal having a length b into an N-valued phase signal having a length n has a length n For all the distance 1 errors of the N-valued phase signal, the binary signal of length b and the N value of length n are reduced so that the average error rate of each bit of the binary signal of length b is reduced. The association with the phase signal is performed.
[0014]
According to another aspect of the present invention, there is provided a modulation method for transmitting a binary signal having a length of 3 in a three-phase modulation method in correspondence with a ternary phase signal having a length of 2, and comprising a ternary signal having a length of 2 (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1), As binary signals of length 3, (0, 0, 0), (0, 0, 1), (0, 1, 1), (1, 1, 0), (1, 1, 1), (1, 0, 1, 0), (1, 0, 0), and (1, 0, 1) are converted to a binary signal of length 3 for all errors of distance 1 of the ternary signal of length 2. Are associated with each other so as to reduce the average error rate of each bit. According to the present invention, for all errors of distance 1 of a ternary signal of length 2, a length 3 ternary signal is set to minimize the average error rate of each bit of the length 3 binary signal. The value signal may be associated with the binary signal of length 3.
[0015]
According to another aspect of the present invention, there is provided a phase modulation method for transmitting a binary signal having a length of 3 in a three-phase phase modulation system in correspondence with a ternary signal having a length of 2, (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1) ), A binary signal of length 3 is assigned to (b)₂, B₁, B₀), V₂, V₁, V₀Is set to 0 or 1, a specific (v₂, V₁, V₀) And (b)₂+ V₂, B₁+ V₁, B₀+ V₀), Each bit may be assigned as a binary signal having a length of 3.
[0016]
According to another aspect of the present invention, in transmitting a binary signal of length 3 corresponding to the number of phases 3 of phase modulation in correspondence with a ternary phase signal of length 2, On the other hand, the data conversion unit for converting the ternary signal of length 2 into a ternary signal of length 2 is used as a correspondence between the binary signal of length 3 and the ternary signal of length 2 to obtain all distances of the ternary signal of length 2 In order to minimize the average error rate of each bit of a binary signal having a length of 3 for an error of 1, a binary signal having a length of 2 and a ternary signal having a length of 2 are associated with each other. It may be. In this case, a set of eight ternary signals of length 2 ((0,0), (0,1), (0,2), (1,0), (1,1), (1,2) ), (2,0), (2,1)), a set of 8 binary signals of length 3

Are assigned.
[0017]
According to the present invention, when a bandwidth of 100 MHz is required in the two-phase modulation and a bandwidth of 50 MHz is required in the four-phase modulation, for example, an equivalent code error rate is obtained using a bandwidth of about 67 MHz. , The transmission power is reduced by about 1.3 dB compared to the four-phase modulation.
[0018]
A modulation device according to another aspect of the present invention inputs a binary signal having a length b with respect to the number N of phases of phase modulation, and converts the binary signal into an N-value signal having a length n with reference to a predetermined conversion rule. A parallel-to-serial conversion circuit (e.g., 102 in FIG. 3) that multiplexes and outputs the parallel output of n N-valued signals from the data conversion circuit; And a phase modulator (for example, 103 in FIG. 3) that sequentially inputs the output of the conversion circuit, performs N-phase modulation, and outputs the result. For all distance 1 errors of the N-valued phase signal of length n, the binary signal of length b and the length n are set so as to reduce the average error rate of each bit of the binary signal of length b. Is associated with the N-value signal.
[0019]
A demodulation device according to another aspect of the present invention includes a phase demodulator (for example, 201 in FIG. 8) that receives a modulated wave subjected to N-phase modulation and outputs n N-ary signals, A serial-to-parallel conversion circuit (for example, 202 in FIG. 8) for parallelizing and outputting the output of n N-valued signals, an N-valued signal having a length of n, and an N-valued signal having a length of n A data inversion circuit (e.g., 203 in FIG. 8) for converting to a binary signal having a length b with reference to a conversion rule that defines a correspondence relationship between the number of phases N and a binary signal having a length b. ing. In the present invention, a binary signal of length b is set so that the average error rate of each bit of a binary signal of length b is reduced for all errors of distance 1 of an N-value signal of length n. Is associated with the N-value signal having the length n.
[0020]
A modulation / demodulation system according to the present invention includes the modulation device and the demodulation device described above.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of the present invention. FIG. 1 shows a phase modulation method of transmitting a binary signal having a length of 3 (3 bits) corresponding to a ternary signal having a length of 2 in the three-phase modulation method. The relationship is shown.
[0022]
The first column “Binary signal (b₂, B₁, B₀)), The “ternary signal (t) shown in the second column.₁, T₀) "Is assigned. Length 3 binary signals (0, 0, 0), (0, 0, 1), (0, 1, 1), (1, 1, 0), (1, 1, 1), (0, 0, 1) For (1,0), (1,0,0) and (1,0,1), a ternary signal of length 2 (0,0), (0,1), (0,2), ( (1,0), (1,1), (1,2), (2,0), (2,1). In addition, (2, 2) which is a signal to which a ternary signal is not transmitted is a binary signal (1, 1, 1).
[0023]
On the physical transmission path, a ternary signal is transmitted, and a code error occurs primarily on the ternary signal.
[0024]
In FIG. 1, for example, a ternary signal (t₁, T₀) = (0,0), the value “t after error” in the column “+1 error of ternary signal”₁, Lower t₀As shown in₁Has a +1 error, the ternary signal (t₁, T₀) = (1,0), “value after error of binary signal” is (1,1,0), and “error value of binary signal” is (1,1,0) from original binary signal. (1,0) obtained by subtracting (0,0,0), and t₀Has a +1 error, the ternary signal (t₁, T₀) = (0,1), “value after error of binary signal” is (0,0,1), and “value of error of binary signal” is from (0,0,1) to (0,0,1). 0) is subtracted (0, 0, 1). The same applies to the following rows, and the ternary signal (t₁, T₀) = (2,1), in the column of “+1 error of ternary signal”, “value t after error”₁, Lower t₀As shown in₁Has a +1 error, the ternary signal (t₁, T₀) = (0,1), “Value after error of binary signal” is (0,0,1), and “Error value of binary signal” is the original binary signal from (0,0,1). (1,0,1) minus (1,0,0), and t₀Has a +1 error, the ternary signal (t₁, T₀) = (2,2), “value after error of binary signal” is (1,1,1), and “error value of binary signal” is (1,0,1) from (1,1,1). 1) is subtracted (0, 1, 0).
[0025]
Ternary signal (t₁, T₀) = (0,0), the value “t after error” in the column “−1 error of ternary signal”₁, Lower t₀As shown in₁Has a -1 error, the ternary signal (t₁, T₀) = (2,0), “value after error of binary signal” is (1,0,0), and “error value of binary signal” is from (1,0,0). (1,0,0) obtained by subtracting (0,0,0), and t₀Has a -1 error, the ternary signal (t₁, T₀) = (0,2), “value after error of binary signal” is (0,1,1), and “error value of binary signal” is from (0,1,1) to (0,0,1). 0) is subtracted (0, 1, 1). The same applies to other rows.
[0026]
In the example shown in FIG. 1, when transmitting a binary signal (1, 1, 1) having a length of 3 (3 bits), (1, 1) is assigned as a ternary signal. Ternary signal (t₁, T₀T) which is the starting value of₁Only when an “+1 error” occurs, the received signal on the receiving side becomes (2, 1).
[0027]
Therefore, three columns of binary signals ((1, 0, 1)) are output as demodulated binary signals (24 in FIG. 8), and binary signals (b₂, B₁, B₀B)₁Only make an error.
[0028]
The binary signal of length 3 (b₂, B₁, B₀) And a ternary signal of length 2 (t₁, T₀2), the average error rate of the binary signal is minimized for all errors of the transmitted ternary signal. That is, the allocation is optimal.
[0029]
That is, the error rate P of the ternary signal₃, The error rate P of the binary signal_bIs represented by the following equation (1), as described below.
[0030]
P_b= 0.875P₃… (1)
[0031]
Here, in FIG. 1, a ternary signal (t₁, T₀) T₁Error, the binary signal (b₂, B₁, B₀B)₂, B₁, B₀The total number of code errors that occur from "Value after error of binary signal"
t₁5, 4, 2 for "+1 error"
t₁2, 3, 5 for "-1 error"
It is.
t₁Of the +1 error and the -1 error, the binary signal (b₂, B₁, B₀) Each bit b₂, B₁, B₀, And 7, 7, and 7 code errors.
[0032]
In addition, a ternary signal of length 2 (t₁, T₀) T₀Error, the binary signal (b₂, B₁, B₀B)₂, B₁, B₀The code errors that occur in
t₀5, 4, 1 for "+1 error",
t₀2, 3, 6 for "-1 error"
It is.
t₀Of the +1 error and the -1 error, the binary signal (b₂, B₁, B₀) Each bit b₂, B₁, B₀Are 7, 7, and 7 errors.
[0033]
Therefore, the sum is
7 + 7 + 7 + 7 + 7 + 7 = 42 (2)
That is, there are 42 errors.
[0034]
To determine the ratio of the error rate of the binary signal to the error rate of the ternary code, this "42" is
8x2x3 = 48 (3)
Divided by
42/48 = 0.875 (4)
Becomes
[0035]
In the equation (3), “8” is the number of error positions of the ternary signal, “2” is the number of errors of +1 and −1, and “3” is the number of bits of the binary signal. I have.
[0036]
FIG. 2 illustrates a binary signal ((0, 0, 0), (0, 0, 1), (0, 1, 1), (1, 1) having a length of 3 (3 bits) in the three-phase modulation scheme. 1,0), (1,1,1), (0,1,0), (1,0,0), (1,0,1)
Is the ternary phase signal of length 2
((0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1))
In the phase modulation method of transmitting the binary signal having the length 3 and the ternary signal having the length 2, the average error rate of the binary signal (that is, all the ternary signals having the length 2) This shows all correspondences (including the correspondence relationship of FIG. 1) when the error of distance 1 is minimized (the average error rate of each bit of the binary signal of length 3). Note that these are cases where a binary signal having a length of 3 (3 bits) is set to (0, 0, 0) for a ternary signal (0, 0) having a length of 2 and a length of 3 ( (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1 , (1, 0), (1, 1, 1), all the binary signals of length 3 (3 bits) corresponding to the ternary signals of length 2 are (0, 0). , (1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1) ) Is added by exclusive OR.
[0037]
FIG. 2 shows the correspondence between the first column to the 24th column. That is, a ternary signal of length 2 (t₀, T₁) ((0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), ( 2,1)), the binary signal (b₂, B₁, B₀) 8 rows as 1 row

In the first to twenty-fourth columns. The first column of the binary signal in FIG. 2 corresponds to the correspondence in FIG. Length 2 ternary signal (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), ( 2, 1), the length 3 binary signal (v2, v1, v0) is added to each of the length 3 binary signals (b2, b1, b0) of the 24 rows. (However, (v2, v1, v0) is (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1) ), (1,1,0), or (1,1,1)), and (b2 + v2, b1 + v1, b0 + v0) (where the operation symbol + represents an exclusive OR). By allocating bits, conversion between a binary signal having a length of 3 and a ternary signal having a length of 2 may be performed.
[0038]
【Example】
Next, an embodiment of the apparatus for performing the above-described phase modulation will be described. Hereinafter, a configuration in which a three-digit (length 3) binary signal in three-phase modulation is assigned to a two-digit (length 2) ternary signal will be described. FIG. 3 is a diagram showing a configuration of one embodiment of the modulation device according to the present invention. Referring to FIG. 3, the modulation device receives three binary signal data as inputs and outputs two ternary signals, and two ternary signals output in parallel from data conversion circuit 101. A parallel-to-serial conversion circuit 102 (multiplexing circuit) for inputting and converting it into one serial signal, a phase modulator 103 for receiving the output of the parallel-to-serial conversion circuit 102, performing three-phase modulation, and outputting a modulated wave; A control circuit 104 for controlling data conversion. The data conversion circuit 101 outputs a binary signal (b₂, B₁, B₀) And a ternary signal of length 2 (t₁, T₀) Is output. In the data conversion circuit 101, the binary signal (b₂, B₁, B₀) And a ternary signal of length 2 (t₁, T₀) May be provided with a storage device such as a look-up table for giving a correspondence (conversion rule) between the two. Further, the control circuit 104 may be configured to appropriately change the contents (conversion rules) of the lookup table in the data conversion circuit 101. Alternatively, a storage device storing the conversion rules shown in FIG. 2 and the like may be provided on the control circuit 104 side. The conversion performed in the data conversion circuit 101 is, for example, a binary signal (b₂, B₁, B₀) And a ternary signal of length 2 (t₁, T₀In this case, the average error rate of the binary signal is minimized for all errors of the transmitted ternary signal.
[0039]
FIG. 4 is a timing chart for explaining the operation of one embodiment of the present invention. First, the operation of the phase modulation method will be described with reference to FIGS. The input data sequence is represented by three columns of binary signals indicated by reference numeral 11.
[0040]
The three columns of binary signals 11 are converted by the data conversion circuit 101 into signals 12A and 12B each representing a ternary value.
[0041]
The ternary signals 12A and 12B are multiplexed on the time axis by the serial / parallel conversion circuit 102, and are converted into a signal 13 multiplexed on the time axis representing ternary values.
[0042]
At this time, since the ternary signals 12A and 12B having two systems are time-multiplexed, they are compressed on the time axis to become one system signal 13.
[0043]
The signal 13 representing the three values is modulated by the phase modulator 103 and becomes a phase modulated wave 14 having three signal points (see FIG. 4B).
[0044]
On the other hand, the correspondence between the input three-row (length 3) binary signal and the modulated signal subjected to the three-phase modulation is performed according to the correspondence relationship illustrated in FIG. 5, for example. The correspondence between a binary signal having a length of 3 and a ternary signal having a length of 2 is as follows: For (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0), ( (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1). Note that the correspondence between the binary signal and the ternary signal shown in FIG. 5 includes those other than the optimized correspondence shown in FIG. , Are assigned as natural binary signals. In the present invention, the correspondence between the binary signal and the ternary signal is such that the average error rate of each bit of the binary signal of length 3 is minimized for all errors of distance 1 of the ternary signal of length 2. The allocation is not limited to the allocation (the allocation of the first to 24th columns in FIG. 2), but also includes the allocation for reducing the average error rate.
[0045]
That is, in the example shown in FIG. 5, of the two modulation symbols, the first modulation symbol takes a value from “0” to “2”.
[0046]
While the first modulation symbol is between “0” and “1”, the second modulation symbol takes a value between “0” and “2”, and when the first modulation symbol is “2”, the second modulation symbol has a value of “2”. Take two values from "0" to "1".
[0047]
At this time, all signal types are
2x3 + 1x2 ... (5)
And is equal to “8”.
[0048]
“2” in the first half of “2 × 3” in the first term of Expression (5) indicates that the first modulation symbol takes a value from “0” to “1”, and the second half “3” indicates the first modulation symbol. Indicate that the second modulation symbol takes a value from “0” to “2” for each of the modulation symbols.
[0049]
Also, “1” in the first half of “1 × 2” in the second term of Equation (6) indicates that the first modulation symbol takes one value of “2”, and “2” in the second half is: This indicates that the second modulation symbol takes a value from “0” to “1”.
[0050]
Further, when the input signal, which is a binary signal in three columns, changes from (0, 0, 0) to (1, 1, 1), the operation of the modulated wave is shown in FIGS. Modulated waves defined by the signal diagram shown in (H) are sequentially output.
[0051]
As shown in FIG. 5A, the modulation signal (modulation wave) is (0, 0) with respect to the input signal (0, 0, 0) which is a three-column binary signal. ), The modulation signal is (0, 1) with respect to the input signal (0, 0, 1) which is a three-column binary signal. Hereinafter, as shown in FIG. The modulation signal is (2, 1) with respect to the input signal (1, 1, 1) which is a binary signal in three columns. That is, from (0,0,0) to (1,1,1) of the input signal, the first modulation symbol is the second modulation symbol between "0" and "1". The modulation symbol takes a value from "0" to "2", and when the first modulation symbol is "2", the second modulation symbol takes a value from "0" to "1".
[0052]
At this time, all signal types are
2x3 + 1x2 ... (6)
And is equal to “8”.
[0053]
As described above, in this embodiment, after associating three binary data strings with two modulation symbols (signals), the two modulation symbols are multiplexed on the time axis. Thus, one modulation symbol equivalently transmits 1.5 binary data strings.
[0054]
As described in the above embodiment, by optimizing the assignment of the binary signal to the ternary signal (minimizing the average error rate of each bit of the binary signal), 10^-6To get the error rate of
Eb / No = 10.22 (dB) (7)
(However, Eb represents energy per bit and No represents noise power density.)
It is.
[0055]
On the other hand, when the allocation of the binary signal to the ternary signal is not optimized, in the worst case, the ratio of the error rate of the binary signal to the error rate of the ternary signal increases to 1.375,
Eb / No = 10.36 (dB) (8)
To increase.
[0056]
FIG. 6 is a diagram illustrating bit error rate characteristics with respect to Eb / No in the present invention and a comparative example. FIG. 6 shows the bit error rate characteristics of 2-PSK (Phase Shift Keying) / 4-PSK (Comparative Example), the best value of 3-PSK according to the present invention, and the worst value of 3-PSK. I have.
[0057]
The specific embodiment has been described above in connection with the case where a three-digit binary signal is assigned to a two-digit ternary signal in three-phase modulation.
[0058]
Next, as another embodiment of the present invention, the present invention can be applied to the modulation system shown in FIG. FIG. 7 shows a list of the number of phases N of the phase modulation, the number of binary digits b, the number of N values, and the ratio b / n of the number of digits. For example, in three-phase modulation (N = 3), an 11-digit binary signal is assigned to a 7-digit ternary signal, a 19-digit binary signal is assigned to a 12-digit ternary signal, and the like. is there.
[0059]
Similarly, the present invention can be applied to the conversion shown in FIG. 7 in the case of five-phase modulation, six-phase modulation, seven-phase modulation, and the like. For example, for the number of phases N = 5 in the phase modulation, (the digit number b of the binary signal and the digit number n of the N value) are (9, 4), (16, 7), (23, 10), etc. It is said. For the number of phases N = 6 in the phase modulation, (the number b of digits of the binary signal, the number n of the N value) are (5, 2), (18, 7), (23, 9), and the like. You. For the number of phases N = 7 in the phase modulation, (the digit number b of the binary signal and the digit number n of the N value) are (8, 3), (11, 4), (25, 9) and the like. You. The digit ratio b / n is as described in the rightmost column of FIG.
[0060]
Another embodiment of the present invention will be described. The demodulation device that receives the signal modulated and transmitted as described above and demodulates the modulated signal has, for example, a configuration as shown in FIG. Referring to FIG. 8, the demodulation device includes a phase demodulator 201 that performs three-phase phase demodulation on a modulated wave (modulated signal) 21 and outputs a signal 22 representing a ternary value, and two ternary values from the phase demodulator 201. And a serial-to-parallel conversion circuit 202 that converts the signal 22 representing the signal into a serial-parallel format and outputs the signal, and signals 23A and 23B representing the first and second ternary values from the serial-to-parallel conversion circuit 202. In accordance with the conversion rules shown, a data inverse conversion circuit 203 that outputs three columns of binary signals 24 and a control circuit 204 that controls the data inverse conversion are provided. The ternary signal (t of length 2) (t shown in FIG.₁, T₀) And a binary signal of length 3 (b₂, B₁, B₀) May be provided with a storage device such as a look-up table for giving a correspondence (conversion rule) between the two. The control circuit 204 may be configured to appropriately change the conversion rule (contents of the lookup table) in the data inverse conversion circuit 203. Alternatively, the look-up table may be provided on the control circuit 204 side.
[0061]
In the present invention, a modulation / demodulation system including the modulation device shown in FIG. 3 and the demodulation device shown in FIG. 8 may be configured. In the data conversion circuit 101 in FIG. 3 and the data inversion circuit 203 in FIG. 8, the binary signal (b₂, B₁, B₀) And a ternary signal of length 2 (t₁, T₀For example, one of the first to twenty-fourth columns shown in FIG. 2 is commonly used as a correspondence (conversion rule). That is, by optimizing the assignment of the binary signal and the ternary signal, the value of the error rate with respect to Eb / No can be improved.
[0062]
As described above, the present invention has been described with reference to the above embodiment. However, the present invention is not limited to the configuration of the above embodiment, and a person skilled in the art should be within the scope of the claims of the present application. Needless to say, various changes and modifications that could be made are included.
[0063]
【The invention's effect】
As described above, according to the present invention, 2ⁿIn phase modulation, the bandwidth of A is 2^{(N + 1)}When half the bandwidth of A is required in the phase modulation, for example, it is possible to obtain the same code error rate by using a bandwidth between A and A / 2,^{(N + 1 )}There is an effect that transmission with less transmission power can be realized than in phase modulation.
[0064]
Further, the present invention has an effect that the value of the error rate with respect to Eb / No can be improved with respect to the assignment when the binary signal is assigned to the N-value signal.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an embodiment of the present invention.
FIG. 2 is a diagram showing a correspondence between a binary signal and a ternary signal in one embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of a modulation device according to an embodiment of the present invention.
FIG. 4A is a timing chart for explaining the operation of one embodiment of the present invention, and FIG. 4B is a diagram showing three signal points in three-phase modulation;
FIG. 5 is a signal diagram for explaining one embodiment of the present invention.
FIG. 6 is a diagram illustrating bit error rate characteristics of an example of the present invention and a comparative example.
FIG. 7 is a diagram for explaining another embodiment of the present invention.
FIG. 8 is a diagram showing a configuration of a demodulation device according to another embodiment of the present invention.
[Explanation of symbols]
11 3 row binary signal
12A Signal representing the first ternary value
12B Signal representing the second ternary value
13 Time multiplexed ternary signal
14 ° modulated wave (signal)
101 data conversion circuit
102 parallel-to-serial conversion circuit
103 ° phase modulator
104 control circuit
201 phase demodulator
202 serial-parallel conversion circuit
203 data inverse conversion circuit
204 control circuit

Claims (19)

N is a predetermined integer value exceeding 2 which is not a power of 2 and a binary signal having a predetermined length b with respect to the phase number N of the phase modulation is transmitted in correspondence with an N-value phase signal having a predetermined length n. A modulation method,
A data converter for converting the binary signal having the length b into an N-value signal having a length n is provided for each error of the distance 1 of the N-value signal having the length n. The binary signal having the length b and the N-value signal having the length n are associated with each other so as to reduce the average bit error rate, and the binary signal having the length b is converted into the N-value signal having the length n. A modulation method, comprising the step of performing a conversion. A modulation method for transmitting a binary signal having a length of 3 with respect to the number of phases 3 of phase modulation in correspondence with a ternary phase signal having a length of 2,
A data conversion unit for converting a binary signal having a length of 3 into a ternary signal having a length of 2 includes a ternary signal having a length of 2 (0, 0), (0, 1), (0, 2). ), (1,0), (1,1), (1,2), (2,0), (2,1) and the binary signal (0,0,0), (0 , 0, 1), (0, 1, 1), (1, 1, 0), (1, 1, 1), (0, 1, 0), (1, 0, 0), (1, 0) , 1), all errors of distance 1 in the ternary signal of length 2 are associated with each other so that the average error rate of each bit of the binary signal of length 3 is reduced. A modulation method comprising: converting a binary signal having a length of 3 into a ternary signal having a length of 2. A modulation method for transmitting a binary signal having a length of 3 with respect to the number of phases 3 of phase modulation in correspondence with a ternary phase signal having a length of 2,
A data converter for converting a binary signal having a length of 3 into a ternary signal having a length of 2 has a length of 2 as a correspondence between the ternary signal having a length of 2 and the binary signal having a length of 3. Ternary signals (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1) ), The length 3 binary signal (b2, b1, b0) is assigned to each of the length 3 binary signals (b2, b1, b0). v2, v1, v0) (where (v2, v1, v0) is (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1,0,1), (1,1,0), or (1,1,1)), and (b2 + v2, b1 + v1, b0 + v0) (where the operation symbol + is exclusive OR) By representing each bit) It is from 3 binary signal having a step of performing conversion into the ternary signal of length 2, the modulation method, characterized in that. Length 2 ternary signal (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), ( The binary signal of length 3 (b2 + v2, b1 + v1, b0 + v0) assigned to (2, 1) (where the operation symbol + indicates an exclusive OR) is all of the ternary signals of length 2 4. The modulation method according to claim 3, wherein the error is assigned so that the average error rate of each bit of the binary signal having a length of 3 is reduced with respect to the error of the distance 1. A modulation method for transmitting a binary signal having a length of 3 with respect to the number of phases 3 of phase modulation in correspondence with a ternary phase signal having a length of 2,
A data conversion unit that converts a binary signal having a length of 3 into a ternary signal having a length of 2 is used as a correspondence between the binary signal having a length of 3 and the ternary signal having a length of 2 Set of eight ternary signals ((0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0) , (2,1))
As a set of eight binary signals of length 3,

Modulating a binary signal having a length of 3 into a ternary signal having a length of 2 in accordance with a conversion rule for assigning any one of the 24 sets. The data conversion unit may determine, as the conversion rule between a ternary signal having a length of 2 and a binary signal having a length of 3, a ternary signal having a length of 2 (0, 0), (0, 1), ( 0,2), (1,0), (1,1), (1,2), (2,0), (2,1), the length of any of the 24 sets For each of the binary signals (b2, b1, b0) of length 3, the binary signals (v2, v1, v0) of length 3 (where (v2, v1, v0) are (0, 0, 1) , (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1) ), And by assigning each bit as (b2 + v2, b1 + v1, b0 + v0) (the operation symbol + represents an exclusive OR), the length of the binary signal of length 3 is reduced to The step of converting to a value signal. To modulation method of claim 5, wherein a. N is a predetermined integer value exceeding 2 which is not a power of 2 and a binary signal having a predetermined length b with respect to the phase number N of the phase modulation is transmitted in correspondence with an N-value phase signal having a predetermined length n. A modulator,
A data conversion circuit that converts the input binary signal of length b into an N-value signal of length n and outputs the converted signal to the phase modulation unit;
The data conversion circuit is adapted to reduce the binary error of the length b so that the average error rate of each bit of the binary signal of the length b is reduced for all errors of the distance 1 of the N-value signal of the length n. A modulator comprising: means for associating a signal with an N-value signal having a length of n. A modulation device for transmitting a binary signal having a length of 3 with respect to a phase number of 3 of phase modulation in correspondence with a ternary phase signal having a length of 2,
A data conversion circuit for converting the input binary signal of length 3 into a ternary signal of length 2 and outputting the converted signal to a phase modulator;
The data conversion circuit includes a ternary signal (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1) and binary signal of length 3 (0,0,0), (0,0,1), (0,1,1), (1,1,0) , (1,1,1), (0,1,0), (1,0,0), and (1,0,1), the correspondence of all distances 1 of the ternary signal of length 2 For the error, refer to the conversion rule that is assigned so as to reduce the average error rate of each bit of the binary signal having a length of 3 so as to reduce the error rate. A modulation device for performing conversion into a signal. A modulation device for transmitting a binary signal having a length of 3 with respect to a phase number of 3 of phase modulation in correspondence with a ternary phase signal having a length of 2,
A data conversion circuit for converting the input binary signal of length 3 into a ternary signal of length 2 and outputting the converted signal to a phase modulator;
The data conversion circuit has a ternary signal of length 2 (0, 0), (0, 1), (0, 2) as a correspondence between the ternary signal of length 2 and the binary signal of length 3. , (1, 0), (1, 1), (1, 2), (2, 0), and (2, 1) are assigned binary signals (b2, b1, b0) having a length of 3. In this case, the binary signal (v2, v1, v0) of length 3 (where (v2, v1, v0) is (0, (0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,0) 1) is added, and each bit is assigned as (b2 + v2, b1 + v1, b0 + v0) (where the operation symbol + represents exclusive OR), and the length of the binary signal of length 3 is reduced. Conversion into a ternary signal , Modulator, characterized in that. Length 2 ternary signal (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), ( The binary signal of length 3 (b2 + v2, b1 + v1, b0 + v0) assigned to (2, 1) (where the operation symbol + indicates an exclusive OR) is all of the ternary signals of length 2 10. The modulation apparatus according to claim 9, wherein an assignment at a distance 1 is made so as to reduce an average error rate of each bit of the binary signal having a length 3. A modulation device for transmitting a binary signal having a length of 3 with respect to a phase number of 3 of phase modulation in correspondence with a ternary phase signal having a length of 2,
A data conversion circuit for converting the input binary signal of length 3 into a ternary signal of length 2 and outputting the converted signal to a phase modulator;
The data conversion circuit sets eight sets ((0,0), (0,1)) of the ternary signal of length 2 as a correspondence between the binary signal of length 3 and the ternary signal of length 2 , (0,2), (1,0), (1,1), (1,2), (2,0), (2,1))
As a set of eight binary signals of length 3,

A conversion device for converting a binary signal having a length of 3 into a ternary signal having a length of 2 with reference to a conversion rule for assigning any one of the 24 sets. The data conversion unit may determine, as the conversion rule between a ternary signal having a length of 2 and a binary signal having a length of 3, a ternary signal having a length of 2 (0, 0), (0, 1), ( 0,2), (1,0), (1,1), (1,2), (2,0), (2,1), the length of any of the 24 sets For each of the binary signals (b2, b1, b0) of length 3, the binary signals (v2, v1, v0) of length 3 (where (v2, v1, v0) are (0, 0, 1) , (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1) ), And by assigning each bit as (b2 + v2, b1 + v1, b0 + v0) (the operation symbol + represents an exclusive OR), the length of the binary signal of length 3 is reduced to Conversion to a value signal. Modulator according to claim 11,. A binary signal having a length b is input with respect to the number of phases N of phase modulation (where N is a predetermined integer value exceeding 2 which is not a power of 2), and a length n is referred to by referring to a predetermined conversion rule. A data conversion circuit for converting the N-value signal into
A parallel-to-serial conversion circuit that multiplexes and outputs the n parallel outputs of the N-valued signals from the data conversion circuit;
A phase modulator for sequentially inputting the output of the parallel-to-serial conversion circuit, performing N-phase phase modulation, and outputting the resultant;
With
In the above conversion rule between a binary signal of length b and an N-value signal of length n, for all distance 1 errors of the N-value signal of length n, the binary signal of length b A modulation device, wherein a binary signal having a length b and an N-value signal having a length n are associated with each other so as to reduce an average error rate of each bit. A step of receiving a signal transmitted through the three-phase modulation by demodulating the modulated signal with a phase demodulator and outputting a ternary signal having a length of 2;
A data converter that receives a ternary signal of length 2 from the phase demodulator converts the ternary signal of length 2 into a binary signal of length 3 corresponding to the ternary signal of length 2 In doing so, a ternary signal of length 2 (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0) ), (2,1) and a binary signal (0,0,0), (0,0,1), (0,1,1), (1,1,0), (1 , 1, 1), (0, 1, 0), (1, 0, 0), and (1, 0, 1), for all distance 1 errors of a ternary signal of length 2, Converting a ternary signal having a length of 2 into a binary signal having a length of 3 with reference to a conversion rule that associates the average error rate of each bit of the binary signal having a length of 3 with a smaller value. A demodulation method characterized by the above-mentioned. A phase demodulator that receives an N (where N is a predetermined integer value exceeding 2 other than a power of 2) phase-modulated wave and outputs an N-value signal;
A serial-to-parallel conversion circuit for parallelizing and outputting the outputs of the n N-value signals from the phase demodulator;
An N-valued signal of length n output in parallel from the serial-parallel conversion circuit is input, and the correspondence between the N-valued signal of length n and the binary signal of length b with respect to the number N of phases of phase modulation is defined. A data inversion circuit that converts the data into a binary signal having a length b with reference to the conversion rule
With
In the above conversion rule between an N-valued signal of length n and a binary signal of length b, for all distance 1 errors of the N-valued signal of length n, the binary signal of length b A demodulation device, wherein a binary signal having a length b and an N-value signal having a length n are associated with each other so as to reduce an average error rate of each bit. A phase demodulator that inputs a three-phase-modulated wave transmitted from the modulator according to claim 11 and outputs a ternary signal;
The two ternary signals from the phase demodulator are input, and a set of eight ternary signals of length 2 ((0,0), (0,1), (0,2), (1, 0), (1,1), (1,2), (2,0), (2,1)) and eight binary signals of length 3 are used in the modulation device. A data inverse conversion circuit for performing an inverse conversion to a binary signal having a length of 3 with reference to the same conversion rule as the set obtained;
A demodulation device comprising: A modulation / demodulation system comprising the modulation device according to claim 13 and the demodulation device according to claim 15. The n is 2, the N is 3, the b is 3,
The modulation rule is that a set of eight ternary signals of length 2 ((0,0), (0,1), (0,2), (1,0), (1,1), (1 , 2), (2, 0), (2, 1)),
As a set of eight binary signals of length 3,

The modulation / demodulation system according to claim 17, wherein the modulation / demodulation system comprises any one of the 24 sets. The conversion rules between the ternary signal of length 2 and the binary signal of length 3 include a ternary signal of length 2 (0,0), (0,1), (0,2), ( (1,0), (1,1), (1,2), (2,0), (2,1), a binary signal having a length 3 of any of the 24 sets Each of (b2, b1, b0) has a binary signal (v2, v1, v0) of length 3 (where (v2, v1, v0) is (0, 0, 1), (0, 1, 1). 0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1) , (B2 + v2, b1 + v1, b0 + v0) (where the operation symbol + represents an exclusive OR), and by allocating each bit, the binary signal of length 3 and the ternary signal of length 2 Conversion is performed. 18 modem system described.

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