JP3864827B2 - Multilevel modulation apparatus, multilevel demodulation apparatus, multilevel modulation / demodulation communication system, program, and modulation / demodulation method - Google Patents

Description

【００２０】
上式（１）の右辺第１項は、第１信号の１５×２^{（ｐ−３）}ＱＡＭのうちの８×２^{（ｐ−３）}回は、第２、第３、第４の信号で各々１５×２^{（ｐ−３）}ＱＡＭ、１５×２^{（ｐ−３）}ＱＡＭ、１２×２^{（ｐ−３）}ＱＡＭを意味している。
【００２１】
上式（１）の右辺第２項は、４×２^{（ｐ−３）}回は第２、第３、第４の信号で各々１５×２^{（ｐ−３）}ＱＡＭ、１２×２^{（ｐ−３）}ＱＡＭ、１２×２^{（ｐ−３）}ＱＡＭを意味している。
【００２２】
上式（１）の右辺第３項は、２×２^{（ｐ−３）}回は第２、第３、第４の信号で各々１２×２^{（ｐ−３）}ＱＡＭ、１２×２^{（ｐ−３）}ＱＡＭ、８×２^{（ｐ−３）}ＱＡＭを意味している。
【００２３】
上式（１）の右辺第４項は、１×２^{（ｐ−３）}回は第２、第３、第４の信号で各々８×２^{（ｐ−３）}ＱＡＭ、７×２^{（ｐ−３）}ＱＡＭ、４×２^{（ｐ−３）}ＱＡＭを実行する事を意味している。
【００２４】
上式（１）において、第１信号の総数は、１５×２^{（ｐ−３）}となっている。
【００２５】
すなわち、１つの変調シンボルに対して、ｐ＋３／４（＝ｐ＋０．７５）ビットが割り当てられる動作を実行する。
【００２６】
このことから本発明によれば、ＱＡＭ方式において、多値数を、約、２^{（ｎ＋０．７５）}（ただし、ｎは３以上の正整数）とすることが可能となる。
【００２７】
図１は、本発明の一実施の形態の多値変調装置の構成をブロック図にて示した図である。図１を参照すると、本実施の形態の多値変調装置は、入力端子１と、データ列数変換回路２と、第１のデータ変換回路３と、第２のデータ変換回路４と、並列直列変換回路５と、多値変調器６と、出力端子７とを備えている。
【００２８】
第１のデータ変換回路３、及び第２のデータ変換回路４は、データ列数変換回路２が出力する４ｐ＋３列の入力データ信号２１を入力して変換して出力する。
【００２９】
第１のデータ変換回路３は、４ｐ＋３列の入力データ信号２１の値に応じて、１５×２^{（ｐ−３）}種の値を示すｐ＋１列の信号を出力する。
【００３０】
第２のデータ変換回路４は、第１のデータ変換回路３の出力信号を受け、入力データ信号２１の値を参照して、４つのｐ＋１列の信号４１、４２、４３、４４を出力する。
【００３１】
第２のデータ変換回路４は、第１のデータ変換回路３が、その出力信号として、１から８×２^{（ｐ−３）}の値を出力する場合には、これを第１の出力信号とするとともに、第２、第３、第４の出力信号として、それぞれ予め定めた１５×２^{（ｐ−３）}種、１５×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種の値を示す信号を出力する。
【００３２】
第２のデータ変換回路４は、第１のデータ変換回路３が、８×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}の値をとる場合には、これを第１の出力信号４１とするとともに、第２、第３、第４の出力信号４２〜４４として、それぞれ予め定めた１５×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種の値を示す信号を出力する。
【００３３】
第２のデータ変換回路４は、第１のデータ変換回路が、８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}の値をとる場合には、これを第１の出力信号４１とするとともに、第２、第３、第４の出力信号４２〜４４として、それぞれ予め定めた１２×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種、８×２^{（ｐ−３）}種の値を示す信号を出力する。
【００３４】
第２のデータ変換回路４は、第１のデータ変換回路３が、８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}＋１×２^{（ｐ−３）}の値をとる場合には、これを第１の出力信号４１とするとともに、第２、第３、第４の出力信号４２〜４４として、それぞれ予め定めた８×２^{（ｐ−３）}種、７×２^{（ｐ−３）}種、４×２^{（ｐ−３）}２^ｐ種の値を示す信号を出力する。
【００３５】
第２のデータ変換回路４は、第１のデータ変換回路３の出力信号が、８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}＋１×２^{（ｐ−３）}の値をとる場合、これを第１の出力信号４１とするとともに、第２、第３、第４の出力信号４２〜４４として、それぞれ予め定めた４×２^{（ｐ−３）}種、１４×２^{（ｐ−３）}種、４×２^{（ｐ−３）}種の値、又は、それぞれ予め定めた１４×２^{（ｐ−３）}種、８×２^{（ｐ−３）}種、２×２^{（ｐ−３）}種の値を示す信号を出力する構成としてもよい。
【００３６】
並列直列変換回路５は、第２のデータ変換回路４からの第１乃至第４の出力信号４１、４２、４３、４４を入力して時分割多重化し、ｐ＋１列の多重化信号５１を出力する。
【００３７】
多値変調器６は、多重化信号５１を多値変調し、出力端子７へ出力する。
【００３８】
この実施の形態において、第１のデータ変換回路３は、入力データ信号２１の値に応じて、第１のデータ変換回路３の出力信号として、１から１５×２^{（ｐ−３）}の値を分類するとき、第１のデータ変換回路３の出力信号である、８×２^{（ｐ−３）}、４×２^{（ｐ−３）}、２×２^{（ｐ−３）}、１×２^{（ｐ−３）}個の順番を、相互に、任意に入れ替えて出力する構成としてもよい。また第２のデータ変換回路４が、第２、第３、第４の出力信号として、それぞれ予め定めた複数種の値の順番について、該順番を相互に入れ替えて出力する構成としてもよい。
【００３９】
図２は、図１の多値変調装置から出力される信号（通信信号）を入力して復調する処理を行う多値復調装置の構成が示されている。図２を参照すると、本実施の形態の多値復調装置は、入力端子１１と、多値復調器１２と、直列並列変換回路１３と、データ逆変換回路１４と、出力端子１５とを備えている。
【００４０】
多値復調器１２は、入力端子１１に入力された通信信号を復調し、ｐ＋１列の受信復調データ列信号１２１を出力する。
【００４１】
直列並列変換回路１３は、受信復調データ列信号１２１を時分割多重分離して、それぞれｐ＋１列の、第１、第２、第３及び第４の復調データ列信号１３１、１３２、１３３、１３４を出力する。
【００４２】
データ逆変換回路１４は、第１乃至第４の復調データ列信号１３１、１３２、１３３、１３４を入力し、４ｐ＋３列の復調データ信号１４１を出力する。
【００４３】
データ逆変換回路１４は、第１の復調データ列信号が１から８×２^{（ｐ−３）}の値をとる場合には、第２、第３、第４の復調データ列信号として、それぞれ予め定めた１５×２^{（ｐ−３）}種、１５×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種の値を示す信号を受ける。
【００４４】
データ逆変換回路１４は、第１の復調データ列信号が８×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}の値をとる場合には、第２、第３、第４の復調データ列信号としてそれぞれ予め定めた１５×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種の値を示す信号を受ける。
【００４５】
データ逆変換回路１４は、第１の復調データ列信号が８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}の値をとる場合には、第２、第３、第４の復調データ列信号としてそれぞれ予め定めた１２×２^{（ｐ−３）}種、１２×２^{（ｐ−３）}種、８×２^{（ｐ−３）}種の値を示す信号を受ける。
【００４６】
データ逆変換回路１４は、第１の復調データ列信号が８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}＋１から８×２^{（ｐ−３）}＋４×２^{（ｐ−３）}＋２×２^{（ｐ−３）}＋１×２^{（ｐ−３）}の値をとる場合には、第２、第３、第４の復調データ列信号としてそれぞれ予め定めた８×２^{（ｐ−３）}種、７×２^{（ｐ−３）}種、４×２^{（ｐ−３）}２ｐ種の値を示す信号を受ける。
【００４７】
データ逆変換回路１４は、第１、第２、第３、第４の復調データ列信号の示す値に基づき予め定めた復調データ値を生成し、この復調データ値を４ｐ＋３列の復調データ信号１４１として出力する。
【００４８】
本発明に係る多値変復調通信システムは、図１に示した多値変調装置と、図２に示した多値復調装置とを備えて構成される。
【００４９】
次に、図１、図２に示したこの実施の形態の多値変調装置及び多値復調装置の動作について、図面を参照して説明する。
【００５０】
図３は、本実施の形態の多値変調装置内部の各部における、信号の変換を示すタイミングチャートである。図３の（１）は図１の入力データ信号２１を示す。図３の横軸は時間軸であり、入力データ信号２１は一定の時間毎に変化することを示している。図３の（２）Ａ、（２）Ｂ、（２）Ｃ、及び（２）Ｄは、それぞれ図１の第２のデータ変換回路４の出力する信号４１、４２、４３、及び４４を示している。図３の（３）は、図１の並列直列変換回路５の出力する多重化信号５１を示す。図３（３）には、図３の（２）Ａ、（２）Ｂ、（２）Ｃ、及び（２）Ｄの信号を時分割多重し、（２）Ａの信号を（３）のＡ期間に、（２）Ｂの信号を（３）のＢ期間に、（２）Ｃの信号を（３）のＣ期間に、（２）Ｄの信号を（３）のＤ期間に、それぞれ出力している様子が示されている。
【００５１】
図４は、４ｐ＋３列の入力データ信号（２値信号）２１の値（図４の「入力信号の番号」欄）と、出力端子７に出力される信号の値（図４の「変調シンボルの取り得る値」欄）の対応を、一例としてｐ＝４（入力信号は１９列：１９ビット構成）の場合について示している。なお、図４は、この実施の形態における第１、第２のデータ変換回路３、４におけるデータ変換テーブル（不図示）によるデータ変換の一例を示す図である。
【００５２】
図４を参照すると、４つの変調シンボルのうち、第１の変調シンボルは、１から３０までの値をとる。そして、第１の変調シンボルの値が１から１６までの間は、第２、第３、第４の変調シンボルはそれぞれ１から３０まで、１から３０まで、１から２４までの値をとる。
【００５３】
第１の変調シンボルが１７から２４までの間は、第２、第３、第４の変調シンボルはそれぞれ１から３０、１から２４、１から２４までの値をとる。
【００５４】
第１の変調シンボルが２５から２８までの間は、第２、第３、第４の変調シンボルはそれぞれ１から２４、１から２４、１から１６までの値をとる。
【００５５】
第１の変調シンボルが２９から３０までの間は、第２、第３、第４の変調シンボルはそれぞれ１から１６まで、１から１４まで、１から８までの値をとることとしている。
【００５６】
このとき、４つの変調シンボルによって表現できる信号の種類は、次の式（２）に示すとおりとなる。
【００５７】
１６×３０×３０×２４＋８×３０×２４×２４＋４×２４×２４×１６＋２×１６×１４×８＝５２４２８８（＝２^１９） …（２）
【００５８】
上式（２）において、左辺第１項の１６×３０×３０×２４の１６は、第１の変調シンボルが１から１６までの値をとることを示しており、３０×３０×２４は、第１のシンボルの値の１から１６までのそれぞれに対して、第２、第３、第４の変調シンボルがそれぞれ１から３０、１から３０、１から２４までの値をとることを示している。
【００５９】
また、上式（２）において、左辺第２項の８×３０×２４×２４の８は、第１の変調シンボルが１７から２４までの値をとることを示しており、３０×２４×２４は、第１の変調シンボルの１７から２４までのそれぞれに対して、第２、第３、第４の変調シンボルがそれぞれ１から３０、１から２４、１から２４の値をとることを示している。
【００６０】
上式（２）において、左辺第３項の４×２４×２４×１６の４は、第１の変調シンボルが２５から２８までの値をとることを示しており、２４×２４×１６は、第１の変調シンボルの２５から２８までのそれぞれに対して、第２、第３、第４の変調シンボルがそれぞれ１から２４、１から２４、１から１６の値をとることを示している。
【００６１】
上式（２）において、左辺第４項の２×１６×１４×８の２は、第１の変調シンボルが２９から３０までの値をとることを示しており、１６×１４×８は、第１の変調シンボルの２９から３０までのそれぞれに対して、第２、第３、第４の変調シンボルがそれぞれ１から１６、１から１４、１から８の値をとることを示している。
【００６２】
このように、入力データ信号と第１、第２、第３、第４の変調シンボルの値の対応は一義的に定めることができる。このため、第１、第２のデータ変換回路は、ＲＯＭ（Ｒｅａｄ Ｏｎｌｙ Ｍｅｍｏｒｙ）デバイスなどに所定のデータテーブルを格納するなどの構成を採用することにより、実現することができる。なお、図４には、ｐ＝４の場合が例示されているが、本発明は３以上の整数ｐに対して有効であり、本発明は、ｐ＝４の場合に限定されるものでないことは勿論である。
【００６３】
図５は、この実施の形態において、多値変調器６が出力する変調信号の第１、第２、第３、第４の変調シンボルを、位相平面上のいわゆるコンスタレーション（デジタル変調波の信号点配置）として表現した信号図である。図５では、式（２）の左辺第１項から４項において、第１シンボル、第２シンボル、第３シンボル、第４シンボルのとり得る座標点を黒点（丸内にドットが施されている点）にて示している。すなわち、図５の「第一シンボルの１６点」は、左から順に、式（２）の左辺第１項における第１シンボル、第２シンボル、第３シンボル、第４シンボルのとり得る座標点を黒点にて示している。同様に、「第一シンボルの８点」は、左から順に、式（２）の左辺第２項における第１シンボル、第２シンボル、第３シンボル、第４シンボルのとり得る座標点を黒点にて示し、「第一シンボルの４点」は、左から順に、式（２）の左辺第３項における第１シンボル、第２シンボル、第３シンボル、第４シンボルのとり得る座標点を黒点にて示し、「第一シンボルの２点」は、左から順に、式（２）の左辺第４項における第１シンボル、第２シンボル、第３シンボル、第４シンボルのとり得る座標点を黒点にて示す。
【００６４】
次に、本発明の別の実施の形態について説明する。本発明は、３以上の整数ｐにおいて実施可能な、一般的な形で構成法を示している。この応用例としてｐ＝３〜７の場合、すなわち、１５ＱＡＭ、３０ＱＡＭ、６０ＱＡＭ、１２０ＱＡＭ、２４０ＱＡＭについて、該ＱＡＭ変調方式を構成するパラメータの具体例を図６に示す。
【００６５】
図６は、第１、第２、第３及び第４の変調シンボルの、多値数及びそれらの繰り返し数を示している。例えば、１５６［Ｍｂｐｓ］（メガビット／秒）の伝送レートで通信したいが、周波数帯域が３３［Ｍｓｙｍｂｏｌ／ｓｅｃ］（メガ（１００万）シンボル／秒）相当しかない場合には、３２ＱＡＭでは３１．２［Ｍｓｙｍｂｏｌ／ｓｅｃ］となるために帯域の余りが大きくなるが、１６ＱＡＭでは３９［Ｍｓｙｍｂｏｌ／ｓｅｃ］しかとれないために、帯域が不足する。
【００６６】
このような場合には、図６に示す３０ＱＡＭを適用すると、３２．８［Ｍｓｙｍｂｏｌ／ｓｅｃ］の変調速度を確保することができるため、帯域の利用効率よく伝送することが可能となる。
【００６７】
また、このとき、符号誤り率で１０のマイナス６乗を実現するために、従来の３２ＱＡＭでは、所要Ｃ／Ｎ（Carrier to Noise ratio）として、２４．０［ｄＢ］が必要とされている。これに対して、本発明による３０ＱＡＭを用いた場合の所要Ｃ／Ｎは、２３．２［ｄＢ］となる。すなわち、本発明によれば、０．８［ｄＢ］だけ送信電力を小さくしても、従来の３２ＱＡＭと同一の品質で伝送でき、有利である。したがって、電力をより有効に利用することができる。
【００６８】
本発明のさらに別の実施の形態について説明する。図７は、本発明のさらに別の実施の形態の多値変調装置の構成を示す図である。図７において、図１に示した要素と同一の要素には、同一の参照符号が付されている。この実施の形態では、多値変調装置と多値復調装置に制御手段を具備し、多値変調装置、及び多値復調装置におけるデータ変換テーブルを、ＲＡＭ（Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）デバイスなどにより構成し、ＲＡＭに格納するデータ変換テーブルを制御手段により変更可能に構成することができる。多値変調装置と多値復調装置のデータ変換テーブル（データ変換回路、及びデータ逆変換回路内に設けられる）を相互に対応させて変更することで、送受信するデータの値と、通信信号（コンスタレーション上の座標点）の関係を任意に変更することができる。かかる構成により、この実施の形態によれば、送受信データの秘匿性を高め、通信システムの信頼性を向上することができる。
【００６９】
図７を参照すると、この実施の形態の多値変調装置は、図１の多値変調装置に多値変調制御手段８を追加したものである。図７の多値変調制御手段８は、第１のデータ変換回路３と、第２のデータ変換回路４とを制御し、これらの有するデータ変換テーブル（不図示）を変更する。
【００７０】
図８は、本発明のさらに別の実施の形態の多値復調装置の構成を示す図である。図８において、図２に示した要素と同一の要素には、同一の参照符号が付されている。図８を参照すると、この実施の形態の多値復調装置は、図２の多値復調装置に多値復調制御手段１６を追加したものである。多値復調制御手段１６は、データ逆変換回路１４を制御し、これの有するデータ逆変換テーブル（不図示）を変更する。
【００７１】
本発明に係る多値変復調通信システムは、図７に示した多値変調装置と、図８に示した多値復調装置とを備えた構成としてもよい。
【００７２】
また、図７の第１のデータ変換回路３及び第２のデータ変換回路４を多値変調制御手段８の入出力デバイスとして構成し、第１及び第２のデータ変換回路３、４のデータ変換機能を、多値変調制御手段８を構成するコンピュータによって行うようにしてもよい。この場合には、多値変調制御手段８の制御プログラムにてデータ変換回路３、４を代替する処理を行うように構成する。
【００７３】
図９は、このように構成した場合に、多値変調制御手段８のコンピュータで実行すべきプログラムのフローチャートである。多値変調制御手段８は、ステップＳ１にて入力データ信号２１を入力する。続いてステップＳ２で、入力データ信号２１の値に対応する第１の変換データを生成する。
【００７４】
ステップＳ３で第２、第３、第４の変換データを生成する。これらの変換データは、一例として示した図４を参照して構成することができる。
【００７５】
ステップＳ４では、第１、第２、第３、第４の変換データを順次並列直列変換回路６に出力させる。
【００７６】
なお、図９には、１つの入力データを変換する処理が示されているが、図３のタイミングチャートに示したように、入力データ信号は順次供給される。順次供給される入力データ信号にしたがって、図９のフローチャートに示す処理を繰り返し実行させることで、順次、変調信号を送出するよう制御できる。
【００７７】
同様にして、図８のデータ逆変換回路１４を、多値復調制御手段１６の入出力デバイスとして構成し、データ逆変換回路１４のデータ逆変換機能を、多値復調制御手段１６を構成するコンピュータにて行うようにしてもよい。この場合には、多値復調制御手段１６の制御プログラムにて、データ逆変換回路１４の機能を代替する処理を行うよう構成する。
【００７８】
図１０は、このように構成した場合に、多値復調制御手段１６のコンピュータで実行すべきプログラムのフローチャートである。多値復調制御手段１６は、ステップＳ１１にて第１の復調データを入力し、ステップＳ１２にて第２、第３、第４の復調データを入力する。続いてステップＳ１３にて第１、第２、第３及び第４の復調データに対応する復調データ値を生成する。この復調データ値は、一例として示した図４を参照し、逆変換テーブルを作成することによって構成することができる。
【００７９】
ステップＳ１４では、復調データ値を４ｐ＋１列の復調データ信号として出力させる。なお、図１０には、一組の復調データを入力し逆変換する処理が示されているが、復調データが順次供給されるにしたがって、図１０のフローチャートに示す処理を繰り返し実行させることで、順次、復調データ信号を出力するよう制御するようにしてもよいことは勿論である。
【００８０】
また上記実施例の説明で用いた図１、図７では、第１のデータ変換回路３、第２のデータ変換回路４を２つの回路ブロックで構成した例が示されているが、これらのデータ変換回路を１つの回路で構成してもよいことは勿論である。以上、本発明を上記実施の形態に即して説明したが、本発明は、上記実施の形態の構成にのみ限定されるものでなく、特許請求の範囲の各請求項の発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
【００８１】
【発明の効果】
以上説明したように、本発明によれば、４ｐ＋３列の入力データを、４つの変調シンボルに割り当てた後、その４つの変調シンボルを時間軸上で多重化した１つの変調シンボル列によって、ｐ＋０．７５列の２値データ列を伝送しているため、ＱＡＭ方式の多値数を、約２^{（ｐ＋０．７５）}とすることを可能としている。かかる本発明によれば、２^ｎＱＡＭでは周波数帯域に余裕があり過ぎであるが、２^{（ｎ−１）}ＱＡＭでは要求される周波数帯域を超えてしまう場合に、これらの中間の変調方式を提供することができる。
【００８２】
この結果、本発明よれば、周波数をより有効に利用できるだけでなく、２^ｎＱＡＭに比べて少ない所要の信号対雑音比で２^{（ｎ−０．２５）}ＱＡＭが実現でき、電力を有効に利用することができるという効果を奏する。
【００８３】
さらに、本発明によれば、３以上の任意の整数ｐについて構成することのできる、一般的な形で構成法を提供しており、１５ＱＡＭ、３０ＱＡＭ、６０ＱＡＭ、１２０ＱＡＭ、２４０ＱＡＭの他、多くのＱＡＭ変調方式に適用することが可能である。
【図面の簡単な説明】
【図１】本発明の一実施の形態の多値変調装置の構成を示す図である。
【図２】本発明の一実施の形態の多値復調装置の構成を示す図である。
【図３】本発明の一実施の形態の多値変調装置の各部の信号の変換を示すタイミングチャートである。
【図４】本発明の一実施の形態の多値変調装置における第１及び第２のデータ変換回路のデータ変換テーブルの構成を説明するための図である。
【図５】本発明の第１の実施の形態における多値変調信号の位相平面において各変調シンボルのとり得る座標点を示した説明図である。
【図６】本発明の他の実施の形態における他のＱＡＭ変調方式を構成するパラメータの具体例を示す図である。
【図７】本発明のさらに別の実施の形態の多値変調装置の構成を示す図である。
【図８】本発明のさらに別の実施の形態の多値復調装置の構成を示す図である。
【図９】本発明のさらに別の実施の形態の多値変調装置の多値変調制御手段を構成するコンピュータに実行させるプログラムの処理手順の一例を説明するための流れ図である。
【図１０】本発明のさらに別の実施の形態の多値復調装置の多値復調制御手段を構成するコンピュータに実行させるプログラムの処理手順の一例を説明するための流れ図である。
【符号の説明】
１ 入力端子
２ データ列数変換回路
３ 第１のデータ変換回路
４ 第２のデータ変換回路
５ 並列直列変換回路
６ 多値変調器
７ 出力端子
８ 多値変調制御手段
１１ 入力端子
１２ 多値復調器
１３ 直列並列変換回路
１４ データ逆変換回路
１５ 出力端子
１６ 多値復調制御手段
２１ 入力データ信号
４１ 第１の出力信号
４２ 第２の出力信号
４３ 第３の出力信号
４４ 第４の出力信号
５１ 多重化信号
１２１ 受信復調データ列信号
１３１ 第１の復調データ列信号
１３２ 第２の復調データ列信号
１３３ 第３の復調データ列信号
１３４ 第４の復調データ列信号
１４１ 復調データ信号[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilevel modulation / demodulation technique, and more particularly to a multilevel modulation apparatus and multilevel demodulation apparatus that allocate transmission data to a plurality of modulation symbols, a multilevel modulation / demodulation communication system, a multilevel modulation / demodulation program, and a multilevel modulation method.
[0002]
[Prior art]
The multi-level modulation technique has been conventionally used particularly in digital microwave communication and the like. 2 such as 4QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAMⁿA QAM (Quadrature Amplitude Modulation) method (where n is a natural number) is often used. Conventionally, these modulation methods are generally employed because of the simplicity of the circuit. However, in recent years, demands for effective use of frequency and effective use of transmission power are increasing. That is, it is required to ensure a necessary data transmission capacity without waste while suppressing a frequency band to be secured as a digital microwave communication line as narrow as possible. This is because, for example, the 16QAM system cannot realize the required data transmission capacity, so the 32QAM system is adopted. However, the 32QAM system has a large data transmission capacity and wastes the frequency band. It is a request to improve the situation of occupying.
[0003]
As a response to such a demand, for example, Japanese Patent Laid-Open No. 04-196945 proposes a general configuration in which one input data is allocated to two or more modulation symbols. In Japanese Patent Laid-Open No. 04-196945, M and N are set to integers equal to or greater than 2, P is set to be equal to 1 or greater than 1 and less than N, and Q is equal to 1. Or an integer greater than 1, and the input single or plural binary data strings are converted into M × N + P strings, and N values A₁, A₂... A_N2 each^{M + P / N}Is approximately equal to A₁To A_NProduct up to 2^{M × N + P}, The M × N + P binary data string is represented by the value A₁~ A_NAre converted so as to be expressed by a combination of N sets of binary data strings of M + Q columns corresponding to, and each of these N sets of binary data strings of M + Q columns is converted to a binary data string of one set of M + Q columns. Input a binary data string of one set of M + Q columns, and value A at each time₁~ A_NIs a method of performing multilevel modulation by arranging a number of signal points corresponding to the phase plane (N = 2, M = 4, P = 1, Q = 1, A₁= 24, A₂= 24) is disclosed.
[0004]
[Problems to be solved by the invention]
However, the above Japanese Laid-Open Patent Publication No. 04-196945 only shows a general configuration, and does not describe a specific configuration when an input signal sequence is assigned to a plurality of modulation symbols. For this reason, in the above Japanese Patent Laid-Open No. 04-196945, for example, the multi-value number is 2^{(P + 0.75)}When taking a degree (however, p is an integer greater than or equal to 3), it is not shown how it can be specifically configured, and a QAM modulation system that arbitrarily sets a multilevel number is implemented. There is no description suggesting the means and configuration for doing so.
[0005]
Therefore, the problem to be solved by the present invention is to perform a multi-level modulation apparatus and multi-level demodulation apparatus, a multi-level modulation / demodulation communication system, and multi-level modulation and multi-level demodulation that can set modulation frequencies more flexibly. It is to provide a program and a modulation / demodulation method.
[0006]
Another problem to be solved by the present invention is to make effective use of frequency and 2ⁿ2 with a low required signal-to-noise ratio compared to the QAM system^(N-0.25)An object of the present invention is to provide a multilevel modulation apparatus and multilevel demodulation apparatus, a multilevel modulation / demodulation communication system, a program for performing multilevel modulation and multilevel demodulation, and a modulation / demodulation method capable of realizing QAM.
[0007]
[Means for Solving the Problems]
An apparatus according to one aspect of the present invention that solves at least one of the above problems is a multi-level modulation device that multi-level modulates an input data string and outputs a communication signal. , P is an integer of 3 or more) a data string number conversion circuit that converts the input data signal to a binary signal, and the input data signal output from the data string number conversion circuit is input to convert the input data signal The first data conversion circuit to be output, the input data signal output from the data string number conversion circuit and the output signal of the first data conversion circuit are input, and the input signals are respectively a second data conversion circuit for converting and outputting four sets of output signals in the p + 3 column (four sets of output signals are referred to as “first, second, third, and fourth output signals”); Data conversion A parallel-serial conversion circuit that inputs the four sets of p + 1 column output signals output from the path and performs time-division multiplexing, multi-value modulation of the output signal of the parallel-serial conversion circuit, and output of the communication signal And the first data conversion circuit is 1 to 15 × 2 depending on the value of the input data signal.^(P-3)The second data conversion circuit outputs an output signal indicating a value up to 1 × 8 × 2 based on the input data signal.^(P-3)When taking the value of the above, the value of the output signal of the first data conversion circuit is set as the first output signal, and the second, third, and fourth output signals are respectively determined in advance. 15x2^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)A signal indicating a seed value is output, and the output signal of the first data conversion circuit is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)When taking the value of the above, the value of the output signal of the first data conversion circuit is set as the first output signal, and the second, third, and fourth output signals are respectively determined in advance. 15x2^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)A signal indicating a seed value is output, and the output signal of the first data conversion circuit is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)In this case, the value of the output signal of the first data conversion circuit is set as the first output signal, and the second, third, and fourth output signals are respectively determined in advance. , 12x2^(P-3)Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)A signal indicating a seed value is output, and the output signal of the first data conversion circuit is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)When taking the value of the above, the value of the output signal of the first data conversion circuit is set as the first output signal, and the second, third, and fourth output signals are respectively determined in advance. 8x2^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)It is configured to output a signal indicating a seed value.
[0008]
An apparatus according to another aspect of the present invention is a multilevel demodulator that demodulates a communication signal and outputs a demodulated data signal of 4p + 3 columns (p is an integer of 3 or more). A multilevel demodulator that outputs a column signal; a serial-to-parallel converter circuit that time-division demultiplexes the received demodulated data sequence signal and outputs first, second, third, and fourth demodulated data sequence signals; A data reverse conversion circuit that inputs first, second, third, and fourth demodulated data string signals and outputs the demodulated data signal of 4p + 3 columns, and the data reverse conversion circuit includes the first Demodulated data string signal is 1 to 8 × 2^(P-3)In the case of taking the value of 15 × 2 as the second, third, and fourth demodulated data sequence signals,^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)A signal indicating a seed value is received, and the first demodulated data string signal is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)In the case of taking the value of 15 × 2 as the second, third, and fourth demodulated data sequence signals,^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)A signal indicating a seed value is received, and the first demodulated data string signal is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)In the case of taking a value of 12 × 2 as the second, third, and fourth demodulated data string signals,^{(P -3)}Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)A signal indicating a seed value is received, and the first demodulated data string signal is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)In the case of taking the value of 8 × 2 which is predetermined as the second, third and fourth demodulated data string signals, respectively.^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)Based on the values indicated by the first, second, third, and fourth demodulated data sequence signals, a predetermined demodulated data value is taken, and the demodulated data values are obtained as 4p + 3 columns. The demodulated data signal is output.
[0009]
According to still another aspect of the present invention, there is provided a multilevel modulation / demodulation method in which an input signal of 4p + 3 columns (p is an integer of 3 or more) is assigned to four modulation symbols, and the first modulation symbol is 15 × 2^(P-3)1 to 8 × 2 in which the first modulation symbol is determined in advance using a number of signal points.^(P-3)In this case, the second, third, and fourth modulation symbols are each 15 × 2 predetermined corresponding to the input signal.^(P-3)15 × 2^(P-3)12 × 2^(P-3)The number of signal points is used, and the first modulation symbol is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)In this case, 15 × 2 which is determined in advance as the second, third and fourth modulation symbols corresponding to the input signal respectively.^(P-3)12 × 2^(P-3)12 × 2^(P-3)The number of signal points is used, and the first modulation symbol is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)In this case, 12 × 2 predetermined as corresponding to the input signal as the second, third, and fourth modulation symbols respectively.^(P-3)12 × 2^(P-3)8 × 2^(P-3)The number of signal points is used, and the first modulation symbol is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)In this case, the second, third, and fourth modulation symbols are 8 × 2 predetermined corresponding to the input signal, respectively.^(P-3)7 × 2^(P-3)4 × 2^(P-3)The number of signal points is used.
[0010]
A program according to still another aspect of the present invention is a program for causing a computer constituting a multi-level modulation device to execute a multi-level modulation process on an input data signal of 4p + 3 columns (p is an integer of 3 or more), A process of converting an input data signal into first, second, third, and fourth conversion data, wherein the first conversion data is 1 to 15 × 2 depending on the value of the input data signal^(P-3)The first conversion data is 1 to 8 × 2^(P-3)15 × 2 which is predetermined in accordance with the value of the input data signal as the second, third and fourth conversion data.^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)Taking a seed value, the first conversion data is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)15 × 2 which is predetermined in accordance with the value of the input data signal as the second, third and fourth conversion data.^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)Taking a seed value, the first conversion data is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)In this case, the second, third, and fourth conversion data are respectively determined in advance according to the value of the input data signal as 12 × 2^(P-3)Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)Take a seed value and the first conversion data is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)In this case, the second, third, and fourth conversion data are respectively determined in advance according to the value of the input data signal, 8 × 2^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)The program includes a program for causing the computer to execute a process of obtaining a seed value and a process of sequentially outputting the first, second, third, and fourth conversion data to the multilevel modulator.
[0011]
A program according to another aspect of the present invention configures a multilevel demodulation apparatus for multilevel demodulation processing that multilevel-demodulates a communication signal and outputs a demodulated data signal of 4p + 3 columns (where p is an integer of 3 or more). In a program to be executed by a computer, a process for inputting a communication signal as first, second, third, and fourth demodulated data sequence signals and converting the demodulated data signal into 4p + 3 sequences, As a demodulated data string signal, 15 × 2^(P-3)The first demodulated data sequence signal is received from 1 to 8 × 2^(P-3)In this case, 15 × 2 predetermined as the second, third, and fourth demodulated data string signals, respectively.^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)Receiving a seed value, the first demodulated data sequence signal is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)In this case, 15 × 2 predetermined as the second, third, and fourth demodulated data string signals, respectively.^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)Receiving a seed value, the first demodulated data sequence signal is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)In the case of taking the value of 12 × 2 which is predetermined as the second, third and fourth demodulated data string signals, respectively^(P-3)Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)Receiving a seed value, the first demodulated data sequence signal is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)When taking the value of 8 × 2 predetermined as the second, third, and fourth demodulated data string signals, respectively.^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)Receiving a seed value and outputting a predetermined demodulated data value based on the values indicated by the first, second, third, and fourth demodulated data sequence signals; and demodulating the demodulated data value into 4p + 3 sequences And a program for causing the computer to execute a process of outputting as a data signal.
[0012]
[Summary of Invention]
The multilevel modulation apparatus of the present invention converts an input data signal of 4p + 3 columns (where p is an integer of 3 or more) into four p + 1 column signals, and assigns them to independent phase planes. Time-division multiplexing with a set of phase planes, multi-level modulation, and transmission. At this time, a configuration in which p + 0.75 bits are allocated to one modulation symbol is realized by giving a predetermined relationship to the allocation of coordinate points on a set of four phase planes.
[0013]
When p + 3/4 bits are assigned to one modulation symbol, the signal score is 2^{(P + 3/4)}It becomes. However, if it is to be realized with one modulation symbol, 2^{(P + 3/4)}Becomes an irrational number, and modulation cannot be realized as the actual number of signal points.
[0014]
Therefore, the present invention adopts a configuration in which four phase planes are taken as a set and multi-level modulation is performed to control the number of signal points on each of the four phase planes. With this configuration, there are as many as two modulation symbols.^{(P + 3/4)}The effect is as if bits are allocated. As a result, in the QAM system, the multi-value number is reduced to about 2^{(N + 0.75)}It becomes possible.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
In the present invention, in the multilevel modulation method in which p is an integer of 3 or more and an input signal of 4p + 3 columns is assigned to four modulation symbols, 15 × 2 in the first modulation symbol^(P-3)The number of signal points is used, and the first modulation symbol is predetermined from 1 to 8 × 2^(P-3)In this case, 15 × 2 predetermined as the second, third, and fourth modulation symbols corresponding to the input signal respectively.^(P-3)15 × 2^(P-3)12 × 2^(P-3)Number of signal points, and the first modulation symbol is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)In this case, 15 × 2 predetermined as the second, third, and fourth modulation symbols corresponding to the input signal respectively.^(P-3)12 × 2^(P-3)12 × 2^(P-3)Number of signal points, and the first modulation symbol is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)When the signal points are taken, 12 × 2 predetermined as the second, third, and fourth modulation symbols corresponding to the input signal, respectively.^(P-3)12 × 2^(P-3)8 × 2^(P-3)Number of signal points, and the first modulation symbol is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)In this case, 8 × 2 predetermined as the second, third, and fourth modulation symbols corresponding to the input signal, respectively.^(P-3)7 × 2^{(P- 3)}4 × 2^(P-3)It is characterized by using one signal point.
[0017]
The multilevel modulation apparatus according to the present invention inputs an input signal having a value from 1 to 2 to the power of (4p + 3) (where p is an integer equal to or greater than 3), and the first to the second based on the input signal. Conversion means for generating and outputting fourth conversion data; and means for inputting the first to fourth conversion data, performing multi-level modulation and outputting the data, and the conversion means outputs the input signal as its input signal. Depending on the value, it is divided into one of four predetermined groups that do not have common elements.
(A) When the input signal belongs to the first group, the first conversion data is 1 to 8 × 2 depending on the value of the input signal.^(P-3)The second to fourth conversion data are 15 × 2 assigned in advance according to the value of the input signal.^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)Take the value of the seed,
(B) When the input signal belongs to the second group, the first conversion data is 8 × 2 according to the value of the input signal.^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)The second to fourth conversion data are 15 × 2 assigned in advance according to the value of the input signal.^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)Take the value of the seed,
(C) When the input signal belongs to a third group, the first conversion data is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)The second to fourth conversion data are 12 × 2 assigned in advance according to the value of the input signal, respectively.^(P-3)Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)Take the value of the seed,
(D) When the input signal belongs to a fourth group, the first conversion data is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)The second to fourth conversion data are 8 × 2 assigned in advance according to the value of the input signal.^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)It is configured to take a seed value.
[0018]
The modulation system of the present invention is based on the following equation being established when p is an integer of 3 or more.
[0019]

[0020]
The first term on the right side of the above equation (1) is 15 × 2 of the first signal.^(P-3)8 × 2 of QAM^(P-3)The times are 15 × 2 for the second, third and fourth signals.^(P-3)QAM, 15x2^(P-3)QAM, 12x2^(P-3)QAM is meant.
[0021]
The second term on the right side of the above formula (1) is 4 × 2.^(P-3)The times are 15 × 2 for the second, third and fourth signals.^(P-3)QAM, 12x2^(P-3)QAM, 12x2^(P-3)QAM is meant.
[0022]
The third term on the right side of equation (1) is 2 × 2^(P-3)2nd, 3rd and 4th signal each 12x2^(P-3)QAM, 12x2^(P-3)QAM, 8x2^(P-3)QAM is meant.
[0023]
The fourth term on the right side of the above formula (1) is 1 × 2^(P-3)Each time is 8 × 2 for the second, third and fourth signals^(P-3)QAM, 7x2^(P-3)QAM, 4x2^(P-3)This means that QAM is executed.
[0024]
In the above equation (1), the total number of first signals is 15 × 2^(P-3)It has become.
[0025]
That is, an operation is performed in which p + 3/4 (= p + 0.75) bits are assigned to one modulation symbol.
[0026]
Therefore, according to the present invention, in the QAM method, the multi-value number is reduced to about 2^{(N + 0.75)}(Where n is a positive integer of 3 or more).
[0027]
FIG. 1 is a block diagram showing a configuration of a multilevel modulation apparatus according to an embodiment of the present invention. Referring to FIG. 1, the multilevel modulation device of the present embodiment includes an input terminal 1, a data string number conversion circuit 2, a first data conversion circuit 3, a second data conversion circuit 4, and a parallel series. A conversion circuit 5, a multilevel modulator 6, and an output terminal 7 are provided.
[0028]
The first data conversion circuit 3 and the second data conversion circuit 4 input the 4p + 3 columns of input data signals 21 output from the data column number conversion circuit 2, convert them, and output them.
[0029]
The first data conversion circuit 3 generates 15 × 2 according to the value of the input data signal 21 in 4p + 3 columns.^(P-3)A p + 1 column signal indicating a seed value is output.
[0030]
The second data conversion circuit 4 receives the output signal of the first data conversion circuit 3, refers to the value of the input data signal 21, and outputs four p + 1 column signals 41, 42, 43, 44.
[0031]
In the second data conversion circuit 4, the first data conversion circuit 3 outputs 1 to 8 × 2 as its output signal.^(P-3)Is output as the first output signal, and as the second, third, and fourth output signals, 15 × 2 respectively determined in advance.^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)Output a signal indicating the seed value.
[0032]
The second data conversion circuit 4 is configured so that the first data conversion circuit 3 is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)When this value is taken, this is used as the first output signal 41, and as the second, third, and fourth output signals 42 to 44, the predetermined 15 × 2 respectively.^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)Output a signal indicating the seed value.
[0033]
The second data conversion circuit 4 is the same as the first data conversion circuit 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)When this value is taken, this is used as the first output signal 41, and as the second, third, and fourth output signals 42 to 44, 12 × 2 respectively determined in advance.^(P-3)Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)Output a signal indicating the seed value.
[0034]
The second data conversion circuit 4 is configured so that the first data conversion circuit 3 is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)When this value is taken, this is used as the first output signal 41, and as the second, third, and fourth output signals 42 to 44, 8 × 2 respectively determined in advance.^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)2^pOutput a signal indicating the seed value.
[0035]
In the second data conversion circuit 4, the output signal of the first data conversion circuit 3 is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)When this value is taken, this is used as the first output signal 41, and as the second, third, and fourth output signals 42 to 44, 4 × 2 respectively determined in advance.^(P-3)Seed, 14x2^(P-3)Seed, 4 × 2^(P-3)Species value or 14x2 respectively determined in advance^(P-3)Seed, 8 × 2^(P-3)Seed, 2 × 2^(P-3)It is good also as a structure which outputs the signal which shows a seed value.
[0036]
The parallel-serial conversion circuit 5 receives the first to fourth output signals 41, 42, 43, 44 from the second data conversion circuit 4 and performs time division multiplexing to output a multiplexed signal 51 of p + 1 columns. .
[0037]
The multi-level modulator 6 multi-level modulates the multiplexed signal 51 and outputs it to the output terminal 7.
[0038]
In this embodiment, the first data conversion circuit 3 outputs 1 to 15 × 2 as an output signal of the first data conversion circuit 3 according to the value of the input data signal 21.^(P-3)8 × 2 which is the output signal of the first data conversion circuit 3 when classifying the values of^(P-3)4x2^(P-3)2x2^(P-3)1 × 2^(P-3)It is good also as a structure which replaces each order arbitrarily and outputs. In addition, the second data conversion circuit 4 may be configured to output the second, third, and fourth output signals by mutually switching the order of a plurality of types of values that are determined in advance.
[0039]
FIG. 2 shows the configuration of a multi-level demodulator that performs a process of receiving and demodulating a signal (communication signal) output from the multi-level modulator of FIG. Referring to FIG. 2, the multilevel demodulator of the present embodiment includes an input terminal 11, a multilevel demodulator 12, a serial / parallel converter circuit 13, a data inverse converter circuit 14, and an output terminal 15. Yes.
[0040]
The multilevel demodulator 12 demodulates the communication signal input to the input terminal 11 and outputs a received demodulated data sequence signal 121 of p + 1 sequence.
[0041]
The serial-to-parallel conversion circuit 13 time-division demultiplexes the received demodulated data sequence signal 121 and converts the first, second, third, and fourth demodulated data sequence signals 131, 132, 133, and 134 in p + 1 columns, respectively. Output.
[0042]
The data inverse conversion circuit 14 inputs the first to fourth demodulated data string signals 131, 132, 133, and 134, and outputs a 4p + 3 demodulated data signal 141.
[0043]
In the data inverse conversion circuit 14, the first demodulated data string signal is 1 to 8 × 2^(P-3)In this case, as the second, third, and fourth demodulated data string signals, the predetermined 15 × 2 respectively.^(P-3)Seed, 15x2^(P-3)Seed, 12x2^(P-3)A signal indicating the value of the seed is received.
[0044]
In the data inverse conversion circuit 14, the first demodulated data string signal is 8 × 2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)In this case, 15 × 2 predetermined as the second, third, and fourth demodulated data string signals, respectively.^(P-3)Seed, 12x2^(P-3)Seed, 12x2^(P-3)A signal indicating the value of the seed is received.
[0045]
In the data inverse conversion circuit 14, the first demodulated data string signal is 8 × 2^(P-3)+ 4x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)In the case of taking the value of 12 × 2 which is predetermined as the second, third and fourth demodulated data string signals, respectively^(P-3)Seed, 12x2^(P-3)Seed, 8 × 2^(P-3)A signal indicating the value of the seed is received.
[0046]
In the data inverse conversion circuit 14, the first demodulated data string signal is 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+1 to 8 × 2^(P-3)+ 4x2^(P-3)+ 2x2^(P-3)+ 1x2^(P-3)When taking the value of 8 × 2 predetermined as the second, third, and fourth demodulated data string signals, respectively.^(P-3)Seed, 7 × 2^(P-3)Seed, 4 × 2^(P-3)A signal indicating a value of 2p type is received.
[0047]
The data inverse conversion circuit 14 generates a predetermined demodulated data value based on the values indicated by the first, second, third, and fourth demodulated data string signals, and uses the demodulated data value as a 4p + 3 demodulated data signal 141. Output as.
[0048]
The multilevel modulation / demodulation communication system according to the present invention includes the multilevel modulation apparatus shown in FIG. 1 and the multilevel demodulation apparatus shown in FIG.
[0049]
Next, operations of the multilevel modulation apparatus and multilevel demodulation apparatus of this embodiment shown in FIGS. 1 and 2 will be described with reference to the drawings.
[0050]
FIG. 3 is a timing chart showing signal conversion in each part in the multilevel modulation apparatus according to the present embodiment. (1) in FIG. 3 shows the input data signal 21 in FIG. The horizontal axis in FIG. 3 is a time axis, and shows that the input data signal 21 changes every certain time. (2) A, (2) B, (2) C, and (2) D in FIG. 3 respectively show signals 41, 42, 43, and 44 output from the second data conversion circuit 4 in FIG. ing. (3) of FIG. 3 shows the multiplexed signal 51 output from the parallel-serial conversion circuit 5 of FIG. 3 (3), the signals of (2) A, (2) B, (2) C, and (2) D of FIG. 3 are time-division multiplexed, and (2) the signal of A is In period A, (2) B signal is in period B of (3), (2) C signal is in period C of (3), and (2) D signal is in period D of (3), respectively. The output is shown.
[0051]
4 shows the value of the input data signal (binary signal) 21 in the 4p + 3 column (“input signal number” field in FIG. 4) and the value of the signal output to the output terminal 7 (“modulation symbol of FIG. 4”). As an example, the correspondence between “possible values” column) is shown in the case of p = 4 (input signal is 19 columns: 19-bit configuration). FIG. 4 is a diagram showing an example of data conversion by a data conversion table (not shown) in the first and second data conversion circuits 3 and 4 in this embodiment.
[0052]
Referring to FIG. 4, among the four modulation symbols, the first modulation symbol takes a value from 1 to 30. When the value of the first modulation symbol is 1 to 16, the second, third, and fourth modulation symbols take values 1 to 30, 1 to 30, and 1 to 24, respectively.
[0053]
While the first modulation symbol is between 17 and 24, the second, third, and fourth modulation symbols take values from 1 to 30, 1 to 24, and 1 to 24, respectively.
[0054]
While the first modulation symbol is between 25 and 28, the second, third, and fourth modulation symbols take values from 1 to 24, 1 to 24, and 1 to 16, respectively.
[0055]
While the first modulation symbol is between 29 and 30, the second, third, and fourth modulation symbols take values from 1 to 16, from 1 to 14, and from 1 to 8, respectively.
[0056]
At this time, the types of signals that can be expressed by the four modulation symbols are as shown in the following equation (2).
[0057]
16 × 30 × 30 × 24 + 8 × 30 × 24 × 24 + 4 × 24 × 24 × 16 + 2 × 16 × 14 × 8 = 524288 (= 2¹⁹(2)
[0058]
In the above equation (2), 16 in the first term on the left side, 16 × 30 × 30 × 24, indicates that the first modulation symbol takes a value from 1 to 16, and 30 × 30 × 24 is Show that for each of the first symbol values 1 to 16, the second, third, and fourth modulation symbols take values 1 to 30, 1 to 30, and 1 to 24, respectively. Yes.
[0059]
In the above equation (2), 8 in the second term of the left side, 8 × 30 × 24 × 24, indicates that the first modulation symbol takes a value from 17 to 24, and 30 × 24 × 24. Indicates that for each of the first modulation symbols 17 through 24, the second, third, and fourth modulation symbols take values 1 through 30, 1 through 24, and 1 through 24, respectively. Yes.
[0060]
In the above equation (2), 4 of 4 × 24 × 24 × 16 in the third term on the left side indicates that the first modulation symbol takes a value from 25 to 28, and 24 × 24 × 16 is For each of the first modulation symbols 25 to 28, the second, third, and fourth modulation symbols have values 1 to 24, 1 to 24, and 1 to 16, respectively.
[0061]
In the above equation (2), 2 in the fourth term of the left side, 2 × 16 × 14 × 8, 2 indicates that the first modulation symbol takes a value from 29 to 30, and 16 × 14 × 8 is For each of the first modulation symbols 29 to 30, the second, third, and fourth modulation symbols have values 1 to 16, 1 to 14, and 1 to 8, respectively.
[0062]
Thus, the correspondence between the input data signal and the values of the first, second, third, and fourth modulation symbols can be uniquely determined. Therefore, the first and second data conversion circuits can be realized by adopting a configuration such as storing a predetermined data table in a ROM (Read Only Memory) device or the like. FIG. 4 illustrates the case of p = 4, but the present invention is effective for an integer p of 3 or more, and the present invention is not limited to the case of p = 4. Of course.
[0063]
FIG. 5 shows, in this embodiment, the first, second, third, and fourth modulation symbols of the modulation signal output from the multi-level modulator 6 as so-called constellations (digital modulation wave signals) on the phase plane. It is a signal diagram expressed as (point arrangement). In FIG. 5, in the first term to the fourth term on the left side of the formula (2), the coordinate points that the first symbol, the second symbol, the third symbol, and the fourth symbol can take are black dots (dots are given in circles). (Dot). That is, “16 points of the first symbol” in FIG. 5 are the coordinate points that can be taken by the first symbol, the second symbol, the third symbol, and the fourth symbol in the first term on the left side of Equation (2) in order from the left. Shown with black dots. Similarly, “eight points of the first symbol” are, from left to right, the coordinate points that can be taken by the first symbol, the second symbol, the third symbol, and the fourth symbol in the second term on the left side of Equation (2) as black points. The “four points of the first symbol” are, in order from the left, the coordinate points that can be taken by the first symbol, the second symbol, the third symbol, and the fourth symbol in the third term on the left side of Equation (2) as black points. The “two points of the first symbol” are, in order from the left, the coordinate points that can be taken by the first symbol, the second symbol, the third symbol, and the fourth symbol in the fourth term on the left side of Equation (2) as black points. Show.
[0064]
Next, another embodiment of the present invention will be described. The present invention shows a construction method in general form that can be implemented with an integer p greater than or equal to three. As an application example, in the case of p = 3 to 7, that is, for 15QAM, 30QAM, 60QAM, 120QAM, and 240QAM, specific examples of parameters constituting the QAM modulation scheme are shown in FIG.
[0065]
FIG. 6 shows the multi-value number and the number of repetitions of the first, second, third and fourth modulation symbols. For example, when it is desired to communicate at a transmission rate of 156 [Mbps] (megabits / second), but the frequency band is only equivalent to 33 [Msymbol / sec] (mega (million) symbols / second), 3Q in 32QAM is 31.2. [Msymbol / sec] increases the remainder of the band, but 16QAM can only take 39 [Msymbol / sec], so the band is insufficient.
[0066]
In such a case, when 30QAM shown in FIG. 6 is applied, a modulation rate of 32.8 [Msymbol / sec] can be ensured, so that it is possible to transmit the band efficiently.
[0067]
At this time, in order to realize a minus sixth power of 10 in the code error rate, the conventional 32QAM requires 24.0 [dB] as a required C / N (Carrier to Noise ratio). On the other hand, the required C / N when using 30QAM according to the present invention is 23.2 [dB]. That is, according to the present invention, even if the transmission power is reduced by 0.8 [dB], the transmission can be advantageously performed with the same quality as the conventional 32QAM. Therefore, electric power can be used more effectively.
[0068]
Still another embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration of a multi-level modulation device according to still another embodiment of the present invention. 7, the same elements as those shown in FIG. 1 are denoted by the same reference numerals. In this embodiment, the multi-level modulation device and the multi-level demodulation device are provided with control means, and the data conversion table in the multi-level modulation device and the multi-level demodulation device is constituted by a RAM (Random Access Memory) device, etc. The data conversion table stored in the RAM can be changed by the control means. By changing the data conversion tables (provided in the data conversion circuit and the data inverse conversion circuit) of the multi-level modulation device and the multi-level demodulation device so as to correspond to each other, the value of data to be transmitted and received and the communication signal (constant) The relationship of the coordinate points on the link can be arbitrarily changed. With this configuration, according to this embodiment, it is possible to improve the confidentiality of transmitted / received data and improve the reliability of the communication system.
[0069]
Referring to FIG. 7, the multilevel modulation apparatus of this embodiment is obtained by adding multilevel modulation control means 8 to the multilevel modulation apparatus of FIG. 7 controls the first data conversion circuit 3 and the second data conversion circuit 4, and changes the data conversion table (not shown) of these.
[0070]
FIG. 8 is a diagram showing a configuration of a multi-level demodulator according to still another embodiment of the present invention. In FIG. 8, the same elements as those shown in FIG. 2 are denoted by the same reference numerals. Referring to FIG. 8, the multilevel demodulator of this embodiment is obtained by adding multilevel demodulation control means 16 to the multilevel demodulator of FIG. The multi-level demodulation control means 16 controls the data reverse conversion circuit 14 and changes the data reverse conversion table (not shown) included therein.
[0071]
The multilevel modulation / demodulation communication system according to the present invention may be configured to include the multilevel modulation apparatus shown in FIG. 7 and the multilevel demodulation apparatus shown in FIG.
[0072]
Also, the first data conversion circuit 3 and the second data conversion circuit 4 of FIG. The function may be performed by a computer constituting the multi-level modulation control means 8. In this case, a process for substituting the data conversion circuits 3 and 4 is performed by the control program of the multilevel modulation control means 8.
[0073]
FIG. 9 is a flowchart of a program to be executed by the computer of the multi-level modulation control means 8 in such a configuration. The multi-level modulation control means 8 inputs the input data signal 21 in step S1. Subsequently, in step S2, first conversion data corresponding to the value of the input data signal 21 is generated.
[0074]
In step S3, second, third, and fourth conversion data are generated. These conversion data can be configured with reference to FIG. 4 shown as an example.
[0075]
In step S4, the first, second, third, and fourth conversion data are sequentially output to the parallel-serial conversion circuit 6.
[0076]
Although FIG. 9 shows a process of converting one input data, input data signals are sequentially supplied as shown in the timing chart of FIG. By repeatedly executing the processing shown in the flowchart of FIG. 9 in accordance with the sequentially supplied input data signals, it is possible to control to send the modulation signals sequentially.
[0077]
Similarly, the data reverse conversion circuit 14 of FIG. 8 is configured as an input / output device of the multilevel demodulation control means 16, and the data reverse conversion function of the data reverse conversion circuit 14 is configured as a computer that configures the multilevel demodulation control means 16. You may make it perform in. In this case, a process for substituting the function of the data inverse conversion circuit 14 is performed by the control program of the multilevel demodulation control means 16.
[0078]
FIG. 10 is a flowchart of a program to be executed by the computer of the multi-level demodulation control means 16 in such a configuration. The multilevel demodulation control means 16 inputs the first demodulated data at step S11, and inputs the second, third and fourth demodulated data at step S12. In step S13, demodulated data values corresponding to the first, second, third and fourth demodulated data are generated. This demodulated data value can be configured by creating an inverse conversion table with reference to FIG. 4 shown as an example.
[0079]
In step S14, the demodulated data value is output as a demodulated data signal of 4p + 1 columns. Note that FIG. 10 shows a process of inputting and inversely transforming a set of demodulated data, but by repeatedly executing the process shown in the flowchart of FIG. 10 as demodulated data is sequentially supplied, It goes without saying that control may be made so that the demodulated data signal is sequentially output.
[0080]
In FIGS. 1 and 7 used in the description of the above embodiment, an example in which the first data conversion circuit 3 and the second data conversion circuit 4 are constituted by two circuit blocks is shown. Of course, the conversion circuit may be constituted by one circuit. As mentioned above, although this invention was demonstrated according to the said embodiment, this invention is not limited only to the structure of the said embodiment, In the scope of invention of each claim of a claim It goes without saying that various modifications and corrections that can be made by those skilled in the art are included.
[0081]
【The invention's effect】
As described above, according to the present invention, after 4p + 3 columns of input data are assigned to four modulation symbols, p + 0... Are obtained by one modulation symbol sequence obtained by multiplexing the four modulation symbols on the time axis. Since 75 binary data strings are transmitted, the QAM multi-value number is reduced to approximately 2^{(P + 0.75)}It is possible to. According to the present invention, 2ⁿIn QAM, there is too much room in the frequency band, but 2^(N-1)When QAM exceeds a required frequency band, an intermediate modulation scheme can be provided.
[0082]
As a result, according to the present invention, not only the frequency can be used more effectively, but also 2ⁿLess required signal-to-noise ratio than QAM is 2^(N-0.25)QAM can be realized, and there is an effect that power can be used effectively.
[0083]
Furthermore, according to the present invention, a configuration method is provided in a general form that can be configured for any integer p greater than or equal to 3, including many QAMs in addition to 15QAM, 30QAM, 60QAM, 120QAM, and 240QAM. It is possible to apply to a modulation system.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a multilevel modulation device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a multilevel demodulator according to an embodiment of the present invention.
FIG. 3 is a timing chart showing signal conversion of each part of the multi-level modulation device according to one embodiment of the present invention.
FIG. 4 is a diagram for explaining a configuration of a data conversion table of the first and second data conversion circuits in the multilevel modulation device according to the embodiment of the present invention.
FIG. 5 is an explanatory diagram showing possible coordinate points of each modulation symbol on the phase plane of the multi-level modulation signal in the first embodiment of the present invention.
FIG. 6 is a diagram showing a specific example of parameters constituting another QAM modulation method in another embodiment of the present invention.
FIG. 7 is a diagram showing a configuration of a multi-level modulation device according to still another embodiment of the present invention.
FIG. 8 is a diagram illustrating a configuration of a multi-level demodulation device according to still another embodiment of the present invention.
FIG. 9 is a flowchart for explaining an example of a processing procedure of a program executed by a computer constituting the multi-level modulation control unit of the multi-level modulation device according to still another embodiment of the present invention.
FIG. 10 is a flowchart for explaining an example of a processing procedure of a program executed by a computer constituting the multi-level demodulation control unit of the multi-level demodulating apparatus according to still another embodiment of the present invention.
[Explanation of symbols]
1 Input terminal
2 Data string number conversion circuit
3 First data conversion circuit
4 Second data conversion circuit
5 Parallel to serial converter
6 Multi-level modulator
7 Output terminal
8 Multi-level modulation control means
11 Input terminal
12 Multilevel demodulator
13 Series-parallel converter
14 Data reverse conversion circuit
15 Output terminal
16 Multilevel demodulation control means
21 Input data signal
41 First output signal
42 Second output signal
43 Third output signal
44 Fourth output signal
51 Multiplexed signal
121 Received demodulated data string signal
131 First demodulated data string signal
132 Second demodulated data string signal
133 Third demodulated data string signal
134 Fourth demodulated data string signal
141 Demodulated data signal

Claims (26)

In a multi-level modulation device that multi-level modulates an input data string and outputs a communication signal,
A data string number conversion circuit for converting the input data string into an input data signal composed of binary signals of 4p + 3 columns (where p is an integer of 3 or more);
A first data conversion circuit that receives the input data signal output from the data string number conversion circuit, converts the input data signal, and outputs the converted data;
The input data signal output from the data string number conversion circuit and the output signal of the first data conversion circuit are input, and the input signals are divided into four output signals (four sets of p + 3 columns). A second data conversion circuit that converts the output signal into "first, second, third, and fourth output signals") and outputs the second data conversion circuit;
A parallel-serial conversion circuit that inputs the four sets of p + 1 column output signals output from the second data conversion circuit, outputs the signals by time division multiplexing, and
A multi-level modulator that inputs the output signal of the parallel-serial converter circuit and multi-level modulates and outputs the communication signal;
Have
The first data conversion circuit outputs an output signal indicating a value from 1 to 15 × 2 ^(p−3) according to the value of the input data signal,
When the output signal of the first data conversion circuit takes a value from 1 to 8 × 2 ^(p−3) based on the input data signal, the second data conversion circuit The value of the output signal of the conversion circuit is used as the first output signal, and as the second, third, and fourth output signals, 15 × 2 ^(p-3) types, 15 × 2 ^(P-3) seed, 12 × 2 ^(p-3) A signal indicating the value of the seed is output,
When the output signal of the first data conversion circuit takes a value from 8 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) , the first data The value of the output signal of the conversion circuit is used as the first output signal, and as the second, third, and fourth output signals, predetermined 15 × 2 ^(p-3) types, 12 × 2 respectively. ^(P-3) seed, 12 × 2 ^(p-3) A signal indicating the value of the seed is output,
The output signal of the first data conversion circuit is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^{(p -3),} the value of the output signal of the first data conversion circuit is the first output signal, and the second, third, and fourth output signals are respectively Output signals indicating predetermined values of 12 × 2 ^(p-3) type, 12 × 2 ^(p-3) type, and 8 × 2 ^(p-3) type,
The output signal of the first data conversion circuit is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^{(p -3) When} taking a value of + 2 × 2 ^(p-3) + 1 × 2 ^(p-3) , the value of the output signal of the first data conversion circuit is set as the first output signal, and As the second, third, and fourth output signals, predetermined values of 8 × 2 ^(p-3) type, 7 × 2 ^(p-3) type, and 4 × 2 ^(p-3) type, respectively. A multi-level modulation device configured to output a signal indicating When the first data conversion circuit classifies a value of 1 to 15 × 2 ^(p−3) as an output signal of the first data conversion circuit according to the value of the input data signal, the first data conversion circuit The order of 8 × 2 ^(p-3) , 4 × 2 ^(p-3) , 2 × 2 ^(p-3) , and 1 × 2 ^(p-3) output signals of one data conversion circuit 2. The multi-level modulation device according to claim 1, wherein the multi-level modulation device outputs the signals after being interchanged with each other. In the second data conversion circuit, the output signal of the first data conversion circuit is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) +1 to 8 × 2 ^(P-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) + 1 × 2 When taking the value of ^(p-3) , the value of the output signal of the first data conversion circuit is The first output signal and the second, third, and fourth output signals are respectively predetermined 4 × 2 ^(p-3) type, 14 × 2 ^(p-3) type, 4 × 2 ^{( p-3)} A value indicating a seed value or a signal indicating a predetermined value of 14 × 2 ^(p-3) type, 8 × 2 ^(p-3) type, or 2 × 2 ^(p-3) type, respectively. The multi-level modulation device according to claim 1, wherein The second data conversion circuit outputs, as the second, third, and fourth output signals, the predetermined order of a plurality of values, respectively, by switching the order of each other. The multi-level modulation device according to any one of claims 1 to 3. In a multilevel demodulator that demodulates a communication signal and outputs a demodulated data signal of 4p + 3 columns (where p is an integer of 3 or more),
A multilevel demodulator that demodulates the communication signal and outputs a received demodulated data string signal;
A serial-to-parallel conversion circuit for time-division demultiplexing the received demodulated data string signal and outputting first, second, third, and fourth demodulated data string signals;
A data inverse conversion circuit for inputting the first, second, third, and fourth demodulated data string signals and outputting the demodulated data signal of 4p + 3 columns;
Have
The data reverse conversion circuit includes:
When the first demodulated data string signal takes a value from 1 to 8 × 2 ^(p−3) , the second, third, and fourth demodulated data string signals are respectively determined in advance as 15 × 2 ^(P-3) seed, 15 × 2 ^(p-3) seed, 12 × 2 ^(p-3)
When the first demodulated data string signal takes a value from 8 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) , the second, third, As the fourth demodulated data string signal, signals indicating values of predetermined 15 × 2 ^(p-3) type, 12 × 2 ^(p-3) type, and 12 × 2 ^(p-3) type are received, respectively.
The first demodulated data string signal is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^{(p-3 )} , The second, third, and fourth demodulated data string signals are 12 × 2 ^(p-3) type, 12 × 2 ^(p-3) type, 8 X2 ^(p-3) receiving a signal indicating the value of the seed,
The first demodulated data string signal is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^{(p−3) ) When the value of} + 2 × 2 ^(p−3) + 1 × 2 ^(p−3) is taken, 8 × 2 ^{(p -3)} receiving a signal indicating the value of the species, 7 × 2 ^(p-3) species, 4 × 2 ^(p-3) species,
Based on the values indicated by the first, second, third, and fourth demodulated data sequence signals, a predetermined demodulated data value is taken and the demodulated data value is output as the demodulated data signal of 4p + 3 sequence. A multi-level demodulator characterized by comprising: When 1 to 15 × 2 ^(p−3) are classified according to the value of the first demodulated data sequence signal, 8 × 2 ^(p−3) 4 × 2 ⁽ 6. The multilevel demodulator according to claim 5, wherein the order of ^p-3) , 2 × 2 ^(p-3) , and 1 × 2 ^(p-3) is interchanged. In the data inverse conversion circuit, the first demodulated data string signal is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) +1 to 8 × 2 ^(p−3). + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) + 1 × 2 ^{(p−3) When} the value is taken as the second, third and fourth demodulated data string signals, respectively 14 × 2 ^(p-3) species determined, 4 × 2 ^(p-3) species, 4 × 2 ^(p-3) species values, or predetermined 14 × 2 ^(p-3) species, 7. The multi-level demodulating device according to claim 5, wherein the multi-level demodulating device receives a signal indicating a value of 8 × 2 ^(p-3) type and 2 × 2 ^(p-3) type. 7. The second, third, and fourth demodulated data string signals are output by switching the order of a plurality of types of values that are predetermined in advance, respectively. Multilevel demodulator. A multi-level modulation / demodulation communication system comprising the multi-level modulation device according to any one of claims 1 to 4 and the multi-level demodulation device according to any one of claims 5 to 8. The input data signal that controls the first and second data conversion circuits and is input to the first and second data conversion circuits, and the output signal that is output from the first and second data conversion circuits 5. The multi-level modulation device according to claim 1, further comprising multi-level modulation control means for changing the correspondence with the output value. The first, second, third, and fourth demodulated data sequence signals that control the data reverse conversion circuit and are input to the data reverse conversion circuit, and the output value of the output signal of the data reverse conversion circuit The multilevel demodulation apparatus according to any one of claims 6 to 8, further comprising multilevel demodulation control means for changing the correspondence. A multilevel modulation / demodulation communication system comprising the multilevel modulation apparatus according to claim 10 and the multilevel demodulation apparatus according to claim 11. A program that causes a computer that constitutes a multi-level modulation device to execute multi-level modulation of an input data signal in 4p + 3 columns (where p is an integer of 3 or more),
A process of converting the input data signal into first, second, third and fourth conversion data,
The first conversion data takes a value from 1 to 15 × 2 ^(p−3) according to the value of the input data signal,
When the first conversion data takes a value of 1 to 8 × 2 ^(p−3) , the second, third, and fourth conversion data are previously set according to the value of the input data signal, respectively. The defined 15 × 2 ^(p-3) species, 15 × 2 ^(p-3) species, and 12 × 2 ^(p-3) species values are taken,
When the first conversion data takes a value from 8 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) , the second, third and fourth As the conversion data, values of 15 × 2 ^(p-3) type, 12 × 2 ^(p-3) type, and 12 × 2 ^(p-3) type respectively determined according to the value of the input data signal are taken. ,
The first conversion data is from 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) . When taking a value, as the second, third, and fourth conversion data, 12 × 2 ^(p−3) types, 12 × 2 ^{(p− )} that are respectively predetermined in accordance with the value of the input data signal. ³⁾ Species, 8 × 2 ^(p-3) Species value,
The first conversion data is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +2 When taking the value of x2 ^(p-3) +1 x2 ^(p-3) , the second, third and fourth conversion data are respectively determined in advance according to the value of the input data signal. , 8 × 2 ^(p-3) type, 7 × 2 ^(p-3) type, 4 × 2 ^(p-3) type value conversion processing,
A process of sequentially outputting the first, second, third, and fourth conversion data to a multilevel modulator;
A program for causing the computer to execute. The program according to claim 13, wherein
When the first conversion data classifies values of 1 to 15 × 2 ^(p−3) according to the value of the input data signal, 8 × 2 ^{(p−3) of} the first conversion data, ^{4 × 2 (p-3)} , 2 × 2 (p-3), the 1 × ^{2 (p-3)} type of order, a process of outputting interchangeably, the program causing the computer to perform. The program according to claim 13 or 14,
The first conversion data is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +2 In the case of taking a value of × 2 ^(p-3) + 1 × 2 ^(p-3) , 4 × 2 ^(p-3) types and 14 respectively determined in advance as the second, third, and fourth signals, respectively. × 2 ^(p-3) species, 4 × 2 ^(p-3) species values, or predetermined 14 × 2 ^(p-3) species, 8 × 2 ^(p-3) species, 2 × 2 ^{( p-3)} A program for causing the computer to execute a process of outputting a signal indicating a seed value. The program according to any one of claims 13 to 15,
A program that causes the computer to execute a process of outputting a plurality of predetermined values in a predetermined order as the second, third, and fourth conversion data of the data conversion, with each other being switched in order. In a program for causing a computer constituting a multilevel demodulator to execute multilevel demodulation processing for multilevel demodulation of a communication signal and outputting a demodulated data signal of 4p + 3 columns (where p is an integer of 3 or more),
The communication signal is input as first, second, third, and fourth demodulated data string signals, and is converted into 4p + 3 demodulated data signals,
When the first demodulated data string signal receives 15 × 2 ^(p−3) types of values, and the first demodulated data string signal takes a value of 1 to 8 × 2 ^(p−3) , 15 × 2 ^(p-3) type, 15 × 2 ^(p-3) type, and 12 × 2 ^(p-3) type as the second, third, and fourth demodulated data string signals, respectively. The value of
When the first demodulated data string signal takes a value from 8 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) , the second, third, As the fourth demodulated data sequence signal, values of 15 × 2 ^(p-3) type, 12 × 2 ^(p-3) type, and 12 × 2 ^(p-3) type respectively determined in advance are received,
The first demodulated data string signal is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^{(p-3 )} , The second, third, and fourth demodulated data string signals are 12 × 2 ^(p-3) type, 12 × 2 ^(p-3) type, 8 × 2 ^(p-3)
The first demodulated data string signal is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^{(p−3) )} + 2 × 2 ^{(p−3) When} taking the value of + 1 × 2 ^(p−3) , the second, third, and fourth demodulated data string signals are respectively set to predetermined 8 × 2 ^{(p -3)} values indicated by the first, second, third, and fourth demodulated data string signals in response to the values of seed, 7 × 2 ^(p-3) , 4 × 2 ^(p-3) A program for causing the computer to execute a process of outputting a predetermined demodulated data value and outputting the demodulated data value as a demodulated data signal of 4p + 3 columns. The program according to claim 17,
When 1 to 15 × 2 ^(p−3) are classified according to the value of the first demodulated data sequence signal, 8 × 2 ^(p−3) 4 × of the first demodulated data sequence signal 2 ^(p-3) , 2 × 2 ^(p-3) , 1 × 2 ^(p-3) A program for causing the computer to execute a process of exchanging the order of each other. The program according to claim 17,
The first demodulated data string signal is the first 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^{( p-3) When} + 2 × 2 ^(p-3) + 1 × 2 ^(p-3) is taken, 14 × 2 predetermined as the second, third, and fourth demodulated data string signals, respectively. ^(P-3) species, 4 × 2 ^(p-3) species, 4 × 2 ^(p-3) species values, or predetermined 14 × 2 ^(p-3) species, 8 × 2 ^{(p− 3)} A program that causes the computer to execute a process of receiving a signal indicating a value of seed 2 × 2 ^(p-3) . The program according to any one of claims 17 to 19,
A program that causes the computer to execute a process of outputting the second, third, and fourth demodulated data string signals by changing the order of a plurality of types of predetermined values. A multilevel modulation / demodulation method that assigns 4p + 3 columns (where p is an integer of 3 or more) to four modulation symbols,
The first modulation symbol uses 15 × 2 ^(p−3) signal points,
When the first modulation symbol takes a predetermined 1 to 8 × 2 ^(p-3) signal point, the second, third and fourth modulation symbols correspond to the input signal, respectively. Using predetermined 15 × 2 ^(p-3) , 15 × 2 ^(p-3) , and 12 × 2 ^(p-3) signal points,
When the first modulation symbol takes a signal point of 8 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) , the second, third, and fourth Using 15 × 2 ^(p−3) , 12 × 2 ^(p−3) , and 12 × 2 ^(p−3) signal points that correspond to the input signal as modulation symbols,
The first modulation symbol is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) . When taking a signal point, 12 × 2 ^(p−3) , 12 × 2 ^(p−3) predetermined as corresponding to the input signal as the second, third and fourth modulation symbols, respectively. , 8 × 2 ^(p-3) signal points,
The first modulation symbol is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +2 When taking 2 × ^(p−3) + 1 × 2 ^(p−3) signal points, the second, third, and fourth modulation symbols are 8 × predetermined corresponding to the input signal, respectively. 2. A multilevel modulation / demodulation method using 2 ^(p-3) , 7 × 2 ^(p-3) , and 4 × 2 ^(p-3) signal points. When classifying 1 to 15 × 2 ^(p−3) according to the value of the first modulation symbol, 8 × 2 ^(p−3) , 4 × 2 ^{(p− ) of} the first modulation symbol The multilevel modulation / demodulation method according to claim 21, wherein the order of ³⁾ , 2 × 2 ^(p-3) , and 1 × 2 ^(p-3) is interchanged. The first modulation symbol is 8 × 2 ^(p-3) + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) +1 to 8 × 2 ^(p-3) + 4 × 2 ^(p-3) +2 When taking a value of × 2 ^(p-3) + 1 × 2 ^(p-3) , 14 × 2 ^(p-3) types respectively predetermined as the second, third, and fourth modulation symbols, 4 × 2 ^(p-3) species, 4 × 2 ^(p-3) species values, or predetermined 14 × 2 ^(p-3) species, 8 × 2 ^(p-3) species, 2 × 2 respectively. 23. The multilevel modulation / demodulation method according to claim 21 or 22, wherein a signal indicating a value of ^(p-3) is output. 24. The order of a plurality of types of values determined in advance as the second, third, and fourth modulation symbols, respectively, with the order being interchanged and output. The multilevel modulation / demodulation method described. Input an input signal that takes a value from 1 to 2 to a power of (4p + 3) (where p is an integer of 3 or more), and generate and output first to fourth conversion data based on the input signal Conversion means to
Means for inputting the first to fourth conversion data, performing multi-level modulation, and outputting;
With
The converting means divides the input signal into one of four predetermined groups that do not have elements common to each other according to the value thereof,
When the input signal belongs to the first group, the first conversion data takes a value of 1 to 8 × 2 ^(p−3) according to the value of the input signal, and the second to fourth conversions. The data takes values of 15 × 2 ^(p-3) type, 15 × 2 ^(p-3) type, and 12 × 2 ^(p-3) type assigned in advance according to the value of the input signal. ,
When the input signal belongs to the second group, the first conversion data is 8 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^(p depending on the value of the input signal. ^-3) , and the second to fourth conversion data are respectively assigned in advance according to the value of the input signal, 15 × 2 ^(p-3) types, 12 × 2 ^{(p-3). )} Seed, 12 × 2 ^(p-3)
When the input signal belongs to the third group, the first conversion data is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) +1 to 8 × 2 ^(p−3) + 4 × 2 ^{(p -3)} takes a value of + 2 × 2 ^(p-3) , and the second to fourth conversion data are 12 × 2 ^(p-3) types respectively assigned in advance according to the value of the input signal , 12 × 2 ^(p-3) species, 8 × 2 ^(p-3) species values,
When the input signal belongs to the fourth group, the first conversion data is 8 × 2 ^(p−3) + 4 × 2 ^(p−3) + 2 × 2 ^(p−3) +1 to 8 × 2 ^{(p -3)} + 4 × 2 ^(p-3) + 2 × 2 ^(p-3) + 1 × 2 ^(p-3) , and the second to fourth conversion data depend on the value of the input signal And a means for converting so as to take values of 8 × 2 ^(p-3) type, 7 × 2 ^(p-3) type, and 4 × 2 ^(p-3) type respectively assigned in advance. A modulation device characterized by that. A data signal of 4p + 3 columns (where p is an integer of 3 or more) is converted into four p + 1 column signals having a predetermined relationship, and each of the four p + 1 column signals is converted into four phase planes. Assignment, multi-level modulation with four phase planes as a set, and in the step of controlling the number of signal points on each of the four phase planes , k is an integer of 2 or more, and signal points M on the first phase plane ₁ from _{M 11} to _{M 1k,}
M ₁ = M ₁₁ + M ₁₂ +... M _1k
And the signal points of the second, third, and fourth phase planes are respectively M ₂₁ to M _2k , M ₃₁ to M _3k , and M ₁₁ to M _1k. , M ₄₁ to M _4k (where M ₁ and M _ij (i = 2, 3, 4, j = 1, 2,..., K) are values of 2 ^{(p + 3/4)} or less),
2 ^{4p + 3} = Σ _{j = 1} ^k Π _{i = 1} ⁴ M _ij
The step of controlling to be
A multi-level modulation method characterized by performing quadrature amplitude modulation (QAM) in which p + 3/4 bits are equivalently assigned to one modulation symbol and the multi-level number is approximated by 2 ^{(p + 3/4)} .

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