JP2004128138A - Junction type fet and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve following problems that a difference in impurity concentration in the PN junction between an insulating separation region 3 and a well region 4 is large, a leakage current cannot be reduced, internal resistance is high, and noise characteristics cannot be improved in the conventional junction type FET (field effect transistor). <P>SOLUTION: A gate region is set to be at low concentration and a one-conductivity impurity diffusion region is formed on the interface between the well region and the insulating separation region by the same process as gate region formation. Concentration is low in the one-conductivity impurity diffusion region as compared with the insulating separation region, thus reducing the difference in impurity concentration in the pn junction in the portion. More specifically, the area of the pn junction having a large difference in impurity concentration can be reduced, thus reducing the leakage current. Additionally, source and drain regions are deeply formed, thus reducing the internal resistance and hence increasing the noise characteristics. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a junction FET and a method for manufacturing the same, and more particularly, to a junction FET that can improve noise characteristics and a method for manufacturing the same.
[0002]
[Prior art]
In a conventional junction type FET, for example, an N-type well region is provided in a P-type semiconductor substrate, an N + type source region and a drain region are provided in the N-type well region, and a gate electrode is formed between the source region and the drain region ( For example, see Patent Document 1.)
[0003]
FIG. 8A is a plan view showing a conventional junction FET, and FIG. 8B is a cross-sectional view taken along line BB of FIG. 8A.
[0004]
After growing a P-type epitaxial layer 22 having a thickness of about 3 μm on a P-type substrate 21, an N-type epitaxial layer is formed, and a P + -type insulating isolation region 23 reaching the P-type substrate 21 is formed. Are defined and surrounded.
[0005]
An N + type source region 25 and an N + type drain region 26 are formed inside from the surface of the well region 24, and the source electrode 29 and the drain electrode 30 are respectively connected to the source region 25 and the drain region 26 through the contact holes provided in the insulating film 40. The connection is formed. Further, a gate region 27 connected to the gate electrode 31 is formed between the source region 25 and the drain region 26 from the surface to the inside.
[0006]
The source and drain regions 25 and 26 have respective distances from the P + -type insulating / isolating region 23, the P + -type gate region 27, and the P-type substrate 21 so as to satisfy the withstand voltage (for example, 10 V) required for the junction FET. It is decided.
[0007]
The depth of the gate region 27 formed between the source region 25 and the drain region 26 so as to separate them is an important factor influencing the performance of the junction type FET. , The width of the channel region formed at the gate electrode becomes smaller, the IDSS (current flowing to the drain when a constant voltage is applied between the drain electrode and the source electrode) becomes smaller, and V _{GS (off)} (The gate voltage required to turn off the junction FET) is reduced.
[0008]
With reference to FIG. 9, a method for manufacturing a conventional junction FET will be described.
[0009]
First step: First, a P-type epitaxial layer 22 and an N-type epitaxial layer are stacked on a P-type substrate 21, and an N-type well region 4 is separated and formed by a P + -type insulating separation region 23 (FIG. 9A).
[0010]
Second step: A predetermined position of the oxide film 40 is opened for forming the gate region 27, and P + type impurities are implanted and diffused. This impurity concentration is 10 ¹⁶ This is an order, and Vp is controlled by the depth of the gate region 27 (FIG. 9B).
[0011]
Third step: An opening is formed in the oxide film 40 at predetermined positions to be the source region 25 and the drain region 26, and an N + type impurity (for example, P) is implanted and diffused to form the source region 25 and the drain region 26 (FIG. 9 (C)).
[0012]
Fourth step: A source electrode 29 and a drain electrode 30 that are in contact with the source region 25 and the drain region 26 are formed, and a gate electrode 31 that is connected to the gate region 27 is formed on the back surface (FIG. 9D).
[0013]
[Patent Document 1]
JP 08-227900 A (Page 2 FIG. 6)
[0014]
[Problems to be solved by the invention]
For example, in a junction FET used for a sensor, noise characteristics are important. In order to improve the noise characteristics, it is necessary to reduce the leak current and the internal resistance of the operating section. In the case of the junction FET, the N-well region 24 serving as the operating region and the PN formed by the surrounding P-type region are used. Leakage current at the junction is inevitable. In particular, in the structure of FIG. 8, the gate region 27 provided in each well region 24 is connected to the gate electrode 31 on the back surface of the substrate via the insulating separation region 23. That is, in order to reduce the input resistance of the device, the P-type substrate 21, the P-type epitaxial layer 22, and the insulating isolation region 23 have a high impurity concentration. That is, since the concentration difference from the N-type well region 24 is large, the leak current also increases. For example, if the impurity concentration of the N-type well region 24 is increased, the reduction of the leak current can be suppressed, but the characteristics of the well region serving as a current path will be changed.
[0015]
As described above, in the related art, there has been a problem that the noise characteristics are deteriorated due to the leak current and the internal resistance of the operation unit, particularly when a junction FET is set in the sensor.
[0016]
[Means for Solving the Problems]
The present invention has been made in view of such a problem, and first, a semiconductor layer of one conductivity type, a well region of the opposite conductivity type provided in the semiconductor layer and separated by an insulating isolation region of one conductivity type, and In a junction type FET comprising: a provided reverse conductivity type source region and a drain region; and a one conductivity type gate region provided in the well region between the source region and the drain region. This problem is solved by providing an impurity diffusion region of one conductivity type at the interface of the well region.
[0017]
Second, a semiconductor substrate of one conductivity type, an epitaxial layer of one conductivity type provided on the substrate, and a well region of the opposite conductivity type provided on the epitaxial layer and separated by an insulating isolation region of one conductivity type A source region and a drain region of opposite conductivity type provided in the well region, a gate region of one conductivity type provided in the well region between the source region and the drain region, and the source region and the drain region. In a junction FET including a source electrode and a drain electrode to be contacted, and a gate electrode provided on the semiconductor substrate and connected to the gate region, a one conductivity type impurity diffusion region is provided at an interface between the insulating isolation region and the well region. This will solve the problem.
[0018]
Further, the gate region and the one conductivity type impurity diffusion region have the same impurity concentration and are provided at substantially the same depth.
[0019]
Further, the impurity concentration of the one conductivity type impurity diffusion region is lower than the impurity concentration of the insulating isolation region.
[0020]
Further, the impurity concentration of the gate region and the impurity concentration of the well region are set to be substantially the same.
[0021]
Further, the invention is characterized in that the source and drain regions are provided deeply to a limit at which a predetermined withstand voltage can be secured.
[0022]
Further, the source and drain regions are formed by diffusing a second reverse conductivity type impurity into a surface of a region in which a first reverse conductivity type impurity is deeply diffused.
[0023]
Third, a step of forming a well region of a reverse conductivity type separated by a one-conductivity-type insulating isolation region in a semiconductor layer of one conductivity type, and a step of forming a source region and a drain region of a reverse conductivity type in the well region Forming a one conductivity type gate region between the source region and the drain region of the well region, and simultaneously forming a one conductivity type impurity diffusion region at the interface between the insulating isolation region and the well region. Is to be solved.
[0024]
Fourthly, a one conductivity type epitaxial layer and a reverse conductivity type epitaxial layer are stacked on a one conductivity type semiconductor substrate, and a one conductivity type insulating isolation region reaching the one conductivity type epitaxial layer is formed to form a reverse conductivity type well region. Forming a source region and a drain region by diffusing a high-concentration impurity of the opposite conductivity type into the well region; and forming one conductivity type impurity between the source region and the drain region of the well region. Diffusion to form a gate region, simultaneously forming a one conductivity type impurity diffusion region at the interface between the insulating isolation region and the well region, and forming a source electrode and a drain electrode contacting the source region and the drain region, Forming a gate electrode connected to the gate region on the back surface of the substrate.
[0025]
Further, the gate region and the one-conductivity-type impurity diffusion region are formed by injecting impurities of the same concentration and under the same diffusion conditions.
[0026]
Further, the impurity concentration of the one conductivity type impurity diffusion region is formed to be lower than the impurity concentration of the insulating isolation region.
[0027]
Further, the source region and the drain region are formed before the step of forming the gate region.
[0028]
Further, the source region and the drain region are formed by diffusing a first reverse conductivity type impurity to a limit depth at which a predetermined withstand voltage can be secured, and further diffusing a second reverse conductivity type impurity to the surface. It is assumed that.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
A junction type FET according to the present invention will be described in detail with reference to FIGS.
[0030]
FIG. 1A is a plan view of a junction type FET, and FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A.
[0031]
As described above, the junction type FET of the present invention includes the semiconductor substrate 1, the epitaxial layer 2, the isolation region 3, the well region 4, the source region 5, the drain region 6, the gate region 7, It comprises a type impurity diffusion region 8, a source electrode 9, a drain electrode 10, and a gate electrode 11.
[0032]
The semiconductor substrate 1 is a P-type substrate, on which a P-type epitaxial layer 2 is laminated. The well region 4 is a region in which the N-type epitaxial layer laminated on the P-type epitaxial layer is separated by the insulating separation region 3, and a plurality of well regions are provided on the substrate.
[0033]
The insulating isolation region 3 is a high-concentration P + type region, and penetrates through the N-type epitaxial layer to reach the P-type epitaxial layer 2 to separate and form the N-type well region 4.
[0034]
The source region 5 is a region formed by injecting and diffusing an N + type impurity into the well region 4. In the source region 5, the respective distances from the insulating isolation region 3 and the gate region 7 are determined so as to satisfy the withstand voltage (for example, 10 V) required of the junction FET, and the source region 5 is deeper than the conventional source region 25. Provide. This depth is a limit depth at which the withstand voltage can be ensured, and is, for example, about 2.0 μm.
[0035]
The drain region 6 is a region formed by injecting and diffusing an N + type impurity into the well region 4. The distance between the insulating region 3 and the gate region 7 is determined so that the drain region 6 satisfies the withstand voltage (for example, 10 V) required of the junction FET, and is deeper than the conventional drain region 26. Provide. This depth is a limit depth at which the withstand voltage can be ensured, and is, for example, about 2.0 μm.
[0036]
By providing the source region 5 and the drain region 6 deeply, the resistance of the well layer 4 (operation region) can be reduced. That is, since the internal resistance of the operation unit can be reduced, it is possible to contribute to improvement in noise characteristics.
[0037]
The impurities forming the source region 5 and the drain region 6 are, for example, P (phosphorus) which is a first N + type impurity and As (arsenic) which is a second N + type impurity. A first N + type impurity (P) is implanted and diffused to provide a predetermined depth (for example, about 2.0 μm) at which a predetermined breakdown voltage can be secured. It is implanted and diffused to a depth of about 0.1 μm to increase the impurity concentration on the surface. Thereby, the resistance of the ohmic junction formed by the metal layer serving as the source electrode 9 and the drain electrode 10 and the source region 5 and the drain region 6 can be reduced.
[0038]
Gate region 7 is a P + type impurity diffusion region provided between source region 5 and drain region 6 of well region 4. The impurity concentration of the gate region 7 is lower than that of the conventional one, and is provided to be substantially the same as that of the well region 4. Specifically, 4 × 10 ¹⁴ cm ^-3 From 1 × 10 ^Fifteen cm ^―3 The degree is preferred. As described later, the voltage dependency of the IGSS can be stabilized. That is, the leak current can be suppressed even in the region where the voltage is high, and the noise characteristics are improved.
[0039]
The depth of the gate region 7 is an important factor that affects the performance of the junction type FET. When the depth is increased, the width up to the bottom of the well region 4 serving as a channel region is reduced, and the IDSS (drain electrode-source electrode) is reduced. (A current flowing to the drain when a constant voltage is applied during _{GS (off)} (The gate voltage required to turn off the junction FET) is reduced.
[0040]
One conductivity type impurity diffusion region 8 is a P + type impurity diffusion region provided at the interface between insulating isolation region 3 and well region 4. This is a P + type impurity region having the same concentration as the gate region 7, and has an impurity concentration one digit lower than that of the insulating isolation region 3. By providing the one-conductivity-type impurity diffusion region 8 having a low impurity concentration at the interface between the well region 4 and the insulating isolation region 3 which form a PN junction having a large impurity concentration difference, the PN junction area having a large concentration difference can be reduced by the one-conductivity impurity diffusion Since the current can be reduced by the area 8, the leakage current can be suppressed. Part of the one conductivity type impurity diffusion region 8 is formed so as to overlap or abut the well region 4.
[0041]
The source electrode 9 and the drain electrode 10 are provided on the substrate surface in contact with the source region 5 and the drain region 6, respectively. The gate electrode 11 is provided on the back surface of the substrate, and is connected to the gate region 7 via the insulating isolation region 3. .
[0042]
The first feature of the present invention is to reduce the impurity concentration of the gate region 7. Thereby, the leak current can be reduced as shown in FIG.
[0043]
FIG. 2 is a characteristic diagram showing a relationship between the impurity dose of the gate region 7 and IGSS (leakage current).
[0044]
First, FIG. 2A is a diagram showing IGSS-VGS dependence depending on the impurity dose when the gate region 7 is formed. The broken line indicates the characteristics of the conventional structure, and the dose amount of the gate region 27 is 10 ¹⁶ It is an order. On the other hand, in the embodiment of the present invention, the dose amount is 1 × 10 ¹⁴ cm ^-3 (Circle) and 4 × 10 ¹⁴ cm ^-3 (Squares). As described above, according to the structure of the present embodiment in which the impurity concentration of the gate region 7 is lower than that of the conventional structure indicated by the broken line, the IGSS, that is, the leak current can be reduced. In particular, the initial leak current is reduced as compared with the related art, regardless of the impurity concentration.
[0045]
FIG. 2B is a correlation diagram of the IGSS and the impurity dose of the gate region 7. The upper limit (square) and the lower limit (circle) of the IGSS measured a plurality of times by changing the impurity concentration in forming the gate region 7 are shown. Is plotted.
[0046]
If the impurity concentration of the gate region 7 is too high, the leakage current increases. Also, if the concentration is too low, the concentration difference from the well region 4 increases, which also causes the leakage current to increase. This is apparent from the fact that the IGSS increases when the dose in FIG. 2B is low. In other words, the gate region 7 is lower than the conventional impurity concentration, and the concentration difference between the gate region 7 and the N well region 4 does not increase. ¹⁴ cm ^-3 From 1 × 10 ^Fifteen cm ^―3 Concentrations of the order are preferred.
[0047]
As described above, by setting the impurity concentration of the gate region 7 low and substantially equal to that of the N well region 4, the voltage dependency of the IGSS can be stabilized, and the leak current can be reduced as compared with the conventional case.
[0048]
When the impurity concentration of the gate region 7 is reduced as compared with the conventional case, the gate resistance becomes higher than before, but there is no problem because the gate resistance hardly affects the noise characteristic improvement.
[0049]
The second feature is the one-conductivity-type high-concentration impurity diffusion region 8 provided at the interface between the well region 4 and the insulating separation region 3. By providing a one-conductivity-type high-concentration impurity diffusion region 8 having the same concentration as that of the gate region 7 and a sufficiently lower impurity concentration than the insulation separation region 3 at the interface, a PN junction having a large concentration difference and a well region are formed. Since the PN junction area of No. 4 can be reduced by the one conductivity type impurity diffusion region 8, the leakage current can be suppressed.
[0050]
A third feature resides in that the source region 5 and the drain region 6 are each provided deeply to the limit that a breakdown voltage can be secured. As a result, the internal resistance of the operating unit is reduced, and the noise characteristics are improved from this point as well.
[0051]
Fourth, the source region 5 and the drain region 6 are provided with a diffusion region of the second N + type impurity (As) on the surface of the deep diffusion region formed by the first N + type impurity (P) to increase the surface concentration. Is to do. Thereby, the internal resistance of the operating section can be reduced, and the resistance of the ohmic junction with the source electrode 9 and the drain electrode 10 can be reduced.
[0052]
FIG. 3 shows a comparison of noise characteristics between the conventional structure and the embodiment of the present invention. This figure shows the characteristics when the junction type FET is set for a sensor. FIG. 3A shows the noise at f = 0 to 100 KHz, and FIG. 3B shows the noise at f = 0 to 10 KHz. FIG. The broken line shows the characteristics of the conventional product, and the solid line shows the dose of 1 × 10 ^Fifteen cm ^-3 This is the characteristic in the case of As described above, according to the embodiment of the present invention, a reduction in leakage current and a reduction in internal resistance can be realized, so that noise characteristics can be improved as shown in FIG.
[0053]
Next, a method for manufacturing a junction FET of the present invention will be described with reference to FIGS.
[0054]
The method for manufacturing a junction type FET of the present invention includes the steps of laminating a one-conductivity-type epitaxial layer and a reverse-conductivity-type epitaxial layer on a one-conductivity-type semiconductor substrate, and forming a one-conductivity-type insulating isolation region reaching the one-conductivity-type epitaxial layer. Forming a source region and a drain region by diffusing a high-concentration impurity of a reverse conductivity type into the well region, and forming a source region and a drain region in the well region. Forming a gate region by diffusing an impurity of one conductivity type therebetween, and simultaneously forming an impurity diffusion region of one conductivity type at an interface between the insulating isolation region and the well region; and a source electrode contacting the source region and the drain region. And forming a drain electrode, and forming a gate electrode connected to the gate region on the back surface of the substrate.
[0055]
In the first step of the present invention, as shown in FIG. 4, one conductivity type epitaxial layer 2 and the opposite conductivity type epitaxial layer are laminated on one conductivity type semiconductor substrate 1, and one conductivity type epitaxial layer 2 reaching the one conductivity type epitaxial layer 2 is formed. The purpose is to form the mold isolation region 3 and form the well region 4 of the opposite conductivity type.
[0056]
A P-type epitaxial layer 2 and an N-type epitaxial layer are stacked on a P-type semiconductor substrate 1. In order to form the insulating isolation region 3, a predetermined position of the oxide film 20 formed on the entire surface is opened, a high concentration (approximately) P + type impurity is implanted and diffused, and the high concentration reaches the P type epitaxial layer 2. An insulating isolation region 3 made of a P + type impurity region is formed. Thereby, the N-type epitaxial layer is separated, and an N-type well region 4 is formed.
[0057]
The second step of the present invention is to form a source region 5 and a drain region 6 by diffusing a high concentration impurity of the opposite conductivity type into the well region 4 as shown in FIG.
[0058]
This step is the first feature of the present invention. First, an oxide film 20 is formed again on the entire surface, a predetermined position for forming the source region 5 and the drain region 6 is opened, and P + -type impurities are ion-implanted. Next, diffusion is performed by heat treatment to form a source region 5 and a drain region 6 which are deeper than the conventional one and have a depth (for example, about 2.0 μm) at which a breakdown voltage can be ensured.
[0059]
By making the source region 5 and the drain region 6 deep, the resistance of the well region 4 (operation region) can be reduced, and the noise characteristics can be improved.
[0060]
Here, first, a first N + type impurity (for example, P) is implanted and diffused to form a predetermined depth, for example, about 2.0 μm, and further, a second N + impurity is formed to a depth of about 0.1 μm from its surface. A type impurity (eg, As) is implanted and diffused to increase the impurity concentration on the surface. Thereby, the resistance of the ohmic junction between the metal layer that will become the source electrode 9 and the drain electrode 10 in a later step and the source region 5 and the drain region 6 can be reduced.
[0061]
Alternatively, P may be used as the first N + type impurity and As may be used as the second N + type impurity, and then both impurities may be implanted and then simultaneously diffused. As has a large atomic size and diffusion in Si does not proceed, so that the surface concentration can be similarly increased.
[0062]
The depth of the gate region 7 determines the characteristics of the FET. However, by forming the source and drain regions 5 and 6 before the gate region 7 is formed, the deep source region 5 and the drain region can be formed without considering the gate depth. Region 6 can be formed. Accordingly, the deep source region 5 and the drain region 6 become a part of the current path, so that the internal resistance of the operation section can be reduced and the leak current can be suppressed.
[0063]
In the third step of the present invention, as shown in FIG. 6, one conductivity type impurity is diffused into the well region 4 between the source region 5 and the drain region 6 to form a gate region 7, and at the same time, the insulating isolation region is formed. One impurity diffusion region 8 is formed at the interface between the well 3 and the well region 4.
[0064]
This step is the second feature of the present invention. An oxide film 20 is again formed on the entire surface, and an opening is formed in a predetermined position of the oxide film 20 where the gate region 7 and the one conductivity type impurity diffusion region 8 are to be formed. The gate region 7 is formed between the source region 5 and the drain region 6 at an equal distance from both the regions 5 and 6. The one-conductivity-type impurity diffusion region 8 is formed at the interface between the insulating isolation region 3 and the well region 4 so that a part thereof overlaps or abuts the well region 4.
[0065]
Next, the dose amount is 4 × 10 ¹⁴ cm ^-3 From 1 × 10 ^Fifteen cm ^―3 The gate region 7 and the one-conductivity-type impurity diffusion region 8 are simultaneously formed by injecting and diffusing a P + type impurity of a degree. By forming the gate region 7 with a lower impurity concentration than in the related art, the voltage dependency of the IGSS can be stabilized. That is, the leak current can be suppressed even in the region where the voltage is high, and the noise characteristics are improved.
[0066]
In one part of the insulating isolation region 3, the one conductivity type impurity diffusion region 8 forms a PN junction with the well region 4. Conventionally, the insulating isolation region 3 and the well region 4, which are high-concentration P-type impurity regions, form a PN junction, and the difference in impurity concentration is large, so that the leakage current is increased. In the one-conductivity-type impurity diffusion region 8, the difference in impurity concentration at the PN junction can be reduced as compared with the conventional case. That is, a PN junction area having a large impurity concentration difference can be reduced, so that a leak current can be suppressed.
[0067]
Here, Vp is controlled by the depth of the gate region 7. If the gate region 7 is made deeper, the width to the bottom of the well region 4 which becomes a channel region becomes narrower, and the IDSS (current flowing to the drain when a constant voltage is applied between the drain electrode and the source electrode) becomes smaller. _{GS (off)} (The gate voltage required to turn off the junction FET) is reduced.
[0068]
Conventionally, the source region 5 and the drain region 7 are formed after the gate region 7 is formed. However, in the present embodiment, there is no diffusion step after the gate region 7 is formed. That is, even if the deep source region 5 and the drain region 6 are formed, it is only necessary to control so that a predetermined Vp is obtained in the subsequent formation of the gate region 7, and the characteristics do not change.
[0069]
The one conductivity type impurity diffusion region 8 can be formed simultaneously with the gate region 7 only by changing the pattern for forming the gate region 7. That is, in the same process, the low-concentration gate region 7 and the one-conductivity-type impurity diffusion region 8 in which the difference in the concentration of the PN junction is small can be formed, so that the leak current can be reduced without increasing the number of manufacturing steps.
[0070]
In the fourth step of the present invention, as shown in FIG. 7, a source electrode 9 and a drain electrode 10 are formed in contact with the source region 5 and the drain region 6, and a gate electrode connected to the gate region 7 is formed on the back surface of the substrate. 11 is formed.
[0071]
Opening the oxide film 20 on the substrate surface, exposing the surface of the source region 5 and the drain region 6, depositing a metal such as Al and patterning it into a predetermined electrode structure to form the source electrode 9 and the drain electrode 10. Further, a gate electrode 11 connected to the gate region 7 via the insulating isolation region 3 is formed on the back surface of the substrate.
[0072]
【The invention's effect】
According to the present invention, the following effects can be obtained.
[0073]
First, by reducing the impurity concentration of the gate region 7, the leakage current can be reduced and the noise characteristics can be improved.
[0074]
Second, by providing the one conductivity type impurity diffusion region 8 having the same impurity concentration as that of the gate region 7 having a reduced concentration at the interface between the well region 4 and the insulating isolation region 3, the PN junction of the portion is lower than in the conventional case. The difference in impurity concentration can be reduced. Since the PN junction area having a large impurity concentration difference between the well region 4 and the insulating isolation region 3 can be reduced, it is possible to contribute to the suppression of the leak current.
[0075]
Third, by deepening the source region 5 and the drain region 6 to the limit at which the withstand voltage can be ensured, the internal resistance of the operation section can be reduced, and thus the leak current can be reduced.
[0076]
Fourth, a diffusion region of As is further provided on the surface of the source region 5 and the drain region 6 to increase the impurity concentration on the surface, so that the metal layer serving as the source electrode 9 and the drain electrode 10 and the source region 5 Resistance of the ohmic junction with the semiconductor substrate can be reduced.
[0077]
Fifth, the impurity diffusion region 8 of one conductivity type can be formed simultaneously with the gate region 7 only by changing the pattern for forming the gate region 7, so that the leakage current can be reduced without increasing the number of manufacturing steps as compared with the related art. It is possible to provide a manufacturing method that can reduce the amount.
[0078]
Sixth, by forming the source region 5 and the drain region 6 before the gate region 7 is formed, the deep source region 5 and the drain region 6 can be formed without changing the depth of the gate region 7, and the Vp characteristics can be improved. The internal resistance can be reduced without changing.
[0079]
As described above, since the leakage current can be reduced and the internal resistance of the operation section can be reduced, the noise characteristics can be significantly improved.
[Brief description of the drawings]
FIG. 1A is a plan view and FIG. 1B is a cross-sectional view of a semiconductor device of the present invention.
FIG. 2 is a characteristic diagram of the semiconductor device of the present invention.
FIG. 3 is a characteristic diagram of the semiconductor device of the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;
FIG. 7 is a cross-sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;
8A is a plan view and FIG. 8B is a sectional view of a conventional semiconductor device.
FIG. 9 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
[Explanation of symbols]
1 P + type semiconductor substrate
2 P + type epitaxial layer
3 Isolation area
4 well area
5 Source area
6 Drain region
7 Gate area
8 One conductivity type impurity diffusion region
9 Source electrode
10 Drain electrode
11 Gate electrode
20 Oxide film
21 P + type semiconductor substrate
22 P + type epitaxial layer
23 Isolation area
24 well area
25 Source area
26 Drain region
27 Gate area
29 source electrode
30 drain electrode
31 Gate electrode
40 oxide film

Claims (13)

A semiconductor layer of one conductivity type, a well region of the opposite conductivity type provided in the semiconductor layer and separated by an insulating isolation region of one conductivity type, and a source region and a drain region of the opposite conductivity type provided in the well region; A junction FET provided with a gate region of one conductivity type provided in the well region between the source region and the drain region;
A junction type FET, wherein an impurity diffusion region of one conductivity type is provided at an interface between the insulating isolation region and the well region. A semiconductor substrate of one conductivity type; an e-epitaxial layer of one conductivity type provided on the substrate; a well region of the opposite conductivity type provided on the epitaxial layer and separated by an insulating isolation region of one conductivity type; A source region and a drain region of opposite conductivity type provided in a region, a gate region of one conductivity type provided in the well region between the source region and the drain region, and a source electrode in contact with the source region and the drain region And a drain electrode and a gate electrode provided on the semiconductor substrate and connected to the gate region,
A junction type FET, wherein an impurity diffusion region of one conductivity type is provided at an interface between the insulating isolation region and the well region. 3. The junction type FET according to claim 1, wherein the gate region and the one conductivity type impurity diffusion region have the same impurity concentration and are provided at substantially the same depth. 3. The junction type FET according to claim 1, wherein an impurity concentration of the one conductivity type impurity diffusion region is lower than an impurity concentration of the insulating isolation region. 3. The junction type FET according to claim 1, wherein the impurity concentration of the gate region and the impurity concentration of the well region are set to be substantially the same. 3. The junction type FET according to claim 1, wherein the source and drain regions are provided deep enough to ensure a predetermined breakdown voltage. 3. The junction according to claim 1, wherein the source and drain regions are formed by diffusing a second reverse conductivity type impurity into a surface of a region in which the first reverse conductivity type impurity is deeply diffused. 4. Type FET. Forming a well region of the opposite conductivity type separated by the one conductivity type insulating separation region in the one conductivity type semiconductor layer,
Forming a source region and a drain region of the opposite conductivity type in the well region;
Forming a one conductivity type gate region between the source region and the drain region of the well region, and simultaneously forming a one conductivity type impurity diffusion region at the interface between the insulating isolation region and the well region. A method for manufacturing a junction type FET, which is characterized by the following. Forming a one conductivity type epitaxial layer and a reverse conductivity type epitaxial layer on a one conductivity type semiconductor substrate, forming a one conductivity type insulating isolation region reaching the one conductivity type epitaxial layer, and forming a reverse conductivity type well region; When,
Forming a source region and a drain region by diffusing high-concentration reverse conductivity type impurities into the well region;
Forming a gate region by diffusing one conductivity type impurity between the source region and the drain region of the well region, and simultaneously forming a one conductivity type impurity diffusion region at the interface between the insulating isolation region and the well region;
Forming a source electrode and a drain electrode in contact with the source region and the drain region, and forming a gate electrode connected to the gate region on the back surface of the substrate. The method according to claim 8, wherein the gate region and the one-conductivity-type impurity diffusion region are formed under the same diffusion conditions by implanting the same concentration of impurities. 10. The method according to claim 8, wherein the impurity concentration of the one conductivity type impurity diffusion region is lower than the impurity concentration of the insulating isolation region. 10. The method according to claim 8, wherein the source region and the drain region are formed before the step of forming the gate region. The source region and the drain region are formed by diffusing a first reverse-conductivity-type impurity to a limit depth at which a predetermined withstand voltage can be secured, and further diffusing a second reverse-conductivity-type impurity on the surface. A method for manufacturing a junction type FET according to claim 8.

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