JP2004127663A - Abnormality detection device of battery pack - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make troubleshooting of the circuit for detecting the abnormality of cells. <P>SOLUTION: In the abnormality detection device, the threshold voltage of the overcharge detection circuits b1-bn for detecting overcharge state of the corresponding cells based on the terminal voltage of the cells s1-sn and the overcharge decision threshold voltage, and the threshold voltage of the overdischarge detection circuits c1-cn for detecting the overdischarge state of the corresponding cells based on the terminal voltage of the cells s1-sn and the overdischarge decision threshold voltage, are changed in the troubleshooting. In other word, by changing the threshold voltage so that a signal of H level or a signal of LL level may be outputted by all means in the overcharge detection circuits b1-bn where the defect is not brought about and in the overdischarge detection circuits c1-cn where the defect is not brought about, the troubleshooting of the overcharge detection circuits b1-bn and the overdischarge detection circuits c1-cn is carried out. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for detecting an abnormality in an assembled battery configured by connecting a plurality of cells in series, and particularly to an abnormality detection apparatus for an assembled battery having a failure diagnosis function of an abnormality detection circuit.
[0002]
[Prior art]
2. Description of the Related Art An apparatus that detects an abnormality such as an overcharged state or an overdischarged state of an assembled battery configured by connecting a plurality of cells in series is known that performs failure diagnosis of an assembled battery protection circuit. For example, in Japanese Patent Application Laid-Open No. 11-252809, the total voltage of the assembled battery is detected, the voltages of the individual cells are detected, and the sum of all the cell voltages is compared with the total voltage of the assembled battery. Diagnoses the failure of the battery protection circuit.
[0003]
[Patent Document 1]
JP-A-11-252809
[0004]
[Problems to be solved by the invention]
However, in the conventional failure diagnosis method, in a device for detecting the voltage of each cell, one voltage detection device erroneously detects a voltage on the plus side, and another one voltage detection device detects the voltage on the minus side. However, there is a problem that an error is canceled out in the added value of the cell voltage, and a failure of the protection circuit is not detected.
[0005]
An object of the present invention is to provide an assembled battery abnormality detection device that reliably detects a failure of a device that detects an overcharged state or an overdischarged state of the assembled battery.
[0006]
[Means for Solving the Problems]
An assembled battery abnormality detection device according to the present invention is an assembled battery abnormality detection device composed of a plurality of rechargeable cells, and is provided for each of the plurality of cells. An abnormality detection circuit for detecting an abnormality of the corresponding cell, a determination voltage changing circuit for changing the voltage value of the abnormality determination voltage, and an abnormality detection circuit based on the abnormality determination voltage changed by the determination voltage changing circuit The above-described object is achieved by providing a failure diagnosis circuit that performs failure diagnosis of the abnormality detection circuit based on the abnormality detection result performed in (1).
[0007]
【The invention's effect】
According to the battery pack abnormality detection device of the present invention, the abnormality determination voltage of the abnormality detection circuit that detects the abnormality of the corresponding cell is changed based on the terminal voltage of the cell and the abnormality determination voltage, and the abnormality determination voltage after the change is changed. Based on the abnormality detection result performed by the abnormality detection circuit based on the above, failure diagnosis of the abnormality detection circuit is performed, so that the failure of the abnormality detection circuit can be reliably detected.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a configuration of an embodiment of an assembled battery abnormality detection device according to the present invention. The assembled battery 1 is configured by connecting n cells s1 to sn that can be charged and discharged in series. Current bypass circuits a1 to an, overcharge detection circuits b1 to bn, overdischarge detection circuits c1 to cn, OR circuits d1 to dn, AND circuits e1 to en, and switch circuits f1 to fn are provided for each cell. .
[0009]
The current bypass circuits a1 to an detect that the terminal voltage of the corresponding cell has risen above the first predetermined voltage V1 and are close to full charge, and one of the currents flowing through the corresponding cells s1 to sn This circuit bypasses the unit. That is, since the DOD (depth of discharge) is different for each cell, the current bypass function of the current bypass circuit connected to the cell charged to near full charge is activated, and the charging current flowing through the cell is reduced. By continuing to charge other cells, it is possible to suppress the capacity variation between the cells.
[0010]
The overcharge detection circuits b1 to bn detect that the terminal voltages of the corresponding cells s1 to sn are higher than the second predetermined voltage V20 and are overcharged. Further, the overdischarge detection circuits c1 to cn detect that the terminal voltages of the corresponding cells s1 to sn are lowered from the third predetermined voltage V30 to cause overdischarge. The detection results of the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn are input to the OR circuits d1 to dn and the AND circuits e1 to en.
[0011]
The OR circuits d1 to dn calculate the logical sum of the detection results of the overcharge detection circuits b1 to bn and the detection results of the overdischarge detection circuits c1 to cn. The AND circuits e1 to en calculate the logical product of the detection results of the overcharge detection circuits b1 to bn and the detection results of the overdischarge detection circuits c1 to cn. The switch circuits f1 to fn are switching circuits that select one of the outputs of the OR circuits d1 to dn and the outputs of the AND circuits e1 to en. The switch is switched based on a signal from a charge / discharge control circuit 13 to be described later. When an L (low) level signal is input, the outputs of the OR circuits d1 to dn are selected, and the H (high) level is selected. When the signal is input, the outputs of the AND circuits e1 to en are selected. The logical operation result selected by the switch circuits f1 to fn is input to the OR circuit 10 and the AND circuit 11.
[0012]
The OR circuit 10 calculates the logical sum of the logical operation results selected by all the switch circuits f1 to fn. The AND circuit calculates the logical product of the logical operation results selected by all the switch circuits f1 to fn. The switch circuit 12 is a switching circuit that selects one of the output of the OR circuit 10 and the output of the AND circuit 11. The switch is switched based on a signal from a charge / discharge control circuit 13 to be described later. The output of the OR circuit 10 is selected when an L level signal is input, and an AND circuit when an H level signal is input. 11 outputs are selected. The logical operation result selected by the switch circuits f <b> 1 to fn is input to the charge / discharge control circuit 13.
[0013]
The charge / discharge control circuit 13 controls charge / discharge of the assembled battery 1 based on a signal from the OR circuit 10 or the AND circuit 11. The charge / discharge control circuit 13 outputs two diagnostic signals A and B in order to perform failure diagnosis of the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn.
[0014]
The AND circuit 14 calculates a logical product of a signal obtained by inverting the diagnostic signal B by the inverter 15 and the diagnostic signal A. Therefore, when the diagnostic signal A is at the H level and the diagnostic signal B is at the L level, an H level signal is output, and when the diagnostic signals A and B are in other combinations, an L level signal is output.
[0015]
FIG. 2 is a diagram showing a detailed configuration of the current bypass circuit a2, the overcharge detection circuit b2, and the overdischarge detection circuit c2 connected to the cell s2. The current bypass circuit a2 includes a comparator (voltage comparator) G1, resistors R11, R12, and R13, an N-type MOS transistor Q1, and an inverter INV1. A terminal voltage Vc of the corresponding cell s2 is applied to the negative terminal of the comparator G1, and a voltage V1 (= Vcc · R13 / (R12 + R13)) obtained by dividing the power supply voltage Vcc by the resistor R12 and the resistor R13 is applied to the positive terminal. Applied. The output terminal of the comparator G1 is connected to the gate terminal of the MOS transistor Q1 via the inverter INV1. The source terminal of the MOS transistor Q1 is connected to the negative electrode of the cell s2, and the drain terminal is connected to the positive electrode of the cell s2 via the resistor R11.
[0016]
Note that the comparator G1 outputs an L level signal when the terminal voltage Vc applied to the − terminal is higher than the first voltage V1 serving as a reference applied to the + terminal. At this time, since an H level signal is input to the gate terminal of the MOS transistor Q1 via the inverter INV1, the MOS transistor Q1 is turned on and the current bypass function of the current bypass circuit a2 is activated. That is, the first predetermined voltage V1 is a threshold voltage for bypassing the charging current flowing through the cell s1, and is obtained in advance through experiments or the like. Therefore, it is necessary to set the resistors R12 and R13 so that the voltage V1 can be realized.
[0017]
The overcharge detection circuit b2 includes a comparator G2, a P-type MOS transistor Q2, an N-type MOS transistor Q3, resistors R21, R22, R23, and R24, and inverters INV2 and INV3. When the overcharge of the cell s2 is detected, the L level diagnostic signals A and B are output from the charge / discharge control circuit 13 together. In this case, an H level signal is input to the gate terminal of the P-type MOS transistor Q2 via the inverter INV3, and an L level signal is input to the gate terminal of the N-type MOS transistor Q2. Therefore, the MOS transistor Q2 , Q3 are both off. Accordingly, the terminal voltage Vc of the corresponding cell s2 is applied to the − terminal of the comparator G2, and the voltage V20 (= Vcc · (R23 + R24) obtained by dividing the power supply voltage Vcc by the resistors R21, 22, 23, and 24 is applied to the + terminal. / (R21 + R22 + R23 + R24)) is applied.
[0018]
The comparator G2 outputs an L level signal when the terminal voltage Vc of the cell s2 is higher than the threshold voltage V20 for detecting overcharge. The output of the comparator G2 is input to the OR circuit d2 and the AND circuit e2 via the inverter INV2. Note that a signal output via the inverter INV2 is an output of the overcharge detection circuit b2.
[0019]
The overdischarge detection circuit c2 includes a comparator G3, a P-type MOS transistor Q4, an N-type MOS transistor Q5, resistors R31, R32, R33, and R34, and an inverter INV4. When the overdischarge state of the cell s2 is detected, the L level diagnostic signals A and B are output from the charge / discharge control circuit 13 together. In this case, an H level signal is input to the gate terminal of the P-type MOS transistor Q4 via the inverter INV4, and an L level signal is input to the gate terminal of the N-type MOS transistor Q5. , Q5 are both off. Accordingly, the terminal voltage Vc of the corresponding cell s2 is applied to the negative terminal of the comparator G3, and the voltage V30 (= Vcc · (R33 + R34) obtained by dividing the power supply voltage Vcc by the resistors R31, 32, 33, and 34 is applied to the positive terminal. / (R31 + R32 + R33 + R34)) is applied.
[0020]
The comparator G3 outputs an H level signal when the terminal voltage Vc of the cell s2 is lower than the threshold voltage V30 for detecting overdischarge. Since the signal output from the comparator G3 is directly output from the overdischarge detection circuit c2, an H level signal is output from the overdischarge detection circuit c2 when the overdischarge state of the cell s2 is detected. The output of the comparator G3 is input to the OR circuit d2 and the AND circuit e2.
[0021]
That is, when detecting overcharge and overdischarge of the cell s2, the L level diagnostic signals A and B are output from the charge / discharge control circuit 13 together. At this time, since the output of the AND circuit 14 (see FIG. 1) is at the L level, the switch circuit f2 selects the output from the OR circuit d2. Therefore, when an H level signal is output from the overcharge detection circuit b2 (overcharge state), or when an H level signal is output from the overdischarge detection circuit c2 (overdischarge state), An H level signal is output via the OR circuit d2. Since the switch circuit 12 selects the output of the OR circuit 10 based on the L level signal from the AND circuit 14, the H level signal is input to the charge / discharge control circuit 13. Thereby, the charge / discharge control circuit 13 can detect an abnormality such as overcharge or overdischarge of the cell s2.
[0022]
Note that the magnitude relationship between the threshold voltages V1, V20, and V30 described above is V20>V1> V30.
[0023]
-Failure diagnosis of overcharge detection circuit and overdischarge detection circuit-
In the assembled battery abnormality detection device according to the present embodiment, overcharge determination threshold voltage V20 of overcharge detection circuits b1 to bn and overdischarge determination threshold voltage V30 of overdischarge detection circuits c1 to cn are changed. Thus, failure diagnosis of the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn is performed. The failure diagnosis is performed when the battery pack abnormality detection device according to the present embodiment is started (when power is turned on), when a signal indicating abnormality (overcharge or overdischarge) of the cells s1 to sn is not output, or It is performed when charging / discharging of the battery 1 is stopped for a certain period or longer.
[0024]
When performing failure diagnosis of the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn, the charge / discharge control circuit 13 outputs diagnostic signals A and B with one being at the H level and the other being at the L level. . First, a failure diagnosis method when the diagnostic signal A is set to the H level and the diagnostic signal B is set to the L level will be described.
[0025]
<< When (A, B) = (H, L) >>
When the H level diagnostic signal A is output from the charge / discharge control circuit 13, the H level signal is input to the gate terminal of the N-type MOS transistor Q3 in the overcharge detection circuit b2, so that the MOS transistor Q3 is turned on. To do. However, since the diagnostic signal B is at the L level, the MOS transistor Q2 remains off. In this case, when the MOS transistor Q3 is turned on, a voltage V21 (= Vcc · R23 / (R21 + R22 + R23)) obtained by dividing the power supply voltage Vcc by the resistors R21, R22, and R23 is applied to the + terminal of the comparator G2.
[0026]
Resistance values of the resistors R21 to R24 and R31 to R34 are determined so that the voltage V21 becomes lower than the overdischarge determination threshold voltage V30 of the overdischarge detection circuit c2. Since the voltage Vc of the cell s2 in a normal state that is neither overcharge nor overdischarge is lower than the overcharge determination threshold voltage V20 and higher than the overdischarge determination threshold voltage V30, it is applied to the negative terminal of the comparator G2. The voltage Vc is higher than the voltage V21 applied to the + terminal. Accordingly, the output of the comparator G2 becomes L level, and the signal output from the overcharge detection circuit b2 via the inverter INV2 becomes H level.
[0027]
Next, the operation of the overdischarge detection circuit c2 will be described. Since the L level signal is input to the gate terminal of the P-type MOS transistor Q4 via the inverter INV4, the MOS transistor Q4 is turned on. On the other hand, since the diagnostic signal B is at the L level, the MOS transistor Q5 remains off. In this case, when the MOS transistor Q4 is turned on, the voltage V31 (= Vcc · (R33 + R34) / (R32 + R33 + R34)) obtained by dividing the power supply voltage Vcc by the resistors R32, R33, R34 is applied to the + terminal of the comparator G3. The
[0028]
Resistance values of the resistors R21 to R24 and R31 to R34 are determined so that the voltage V31 becomes higher than the overcharge determination threshold voltage V20 of the overcharge detection circuit b2. As described above, since the voltage Vc of the cell s2 in the normal state is lower than the overcharge determination threshold voltage V20 and higher than the overdischarge determination threshold voltage V30, the voltage Vc applied to the negative terminal of the comparator G3. Becomes lower than the voltage V31 applied to the + terminal. Therefore, the output of the comparator G3 becomes H level indicating that the cell s2 is in an overdischarged state.
[0029]
When the diagnostic signal A is at the H level and the diagnostic signal B is at the L level, an H level signal is input to the two input terminals of the AND circuit 14, so that an H level signal is output from the output terminal. Therefore, the switch circuit f2 selects the output of the AND circuit e2. As described above, since an H level signal is output from both the overcharge detection circuit b2 and the overdischarge detection circuit c2, an H level signal is output from the AND circuit e2.
[0030]
The switch circuit 12 selects the output of the AND circuit 11 based on the H level signal output from the AND circuit 14. As described above, since the H level signal is output from the AND circuit e2, the H level signal is input to one of the plurality of input terminals of the AND circuit 11. In FIG. 2, the overcharge detection circuit b2 and the overdischarge detection circuit c2 provided corresponding to the cell s2 have been described, but the other overcharge detection circuits b1, b3 to bn and overdischarge detection circuits c1, c3 to c3 are described. A similar operation is performed for cn. That is, since the H level signal is input to the AND circuit 11 from the AND circuits e1 to en, the H level signal is output from the output terminal and input to the charge / discharge control circuit 13.
[0031]
Thus, by setting the overcharge determination threshold voltage of the overcharge detection circuits b1 to bn to V21 which is lower than the overdischarge determination threshold voltage V30 at the time of normal cell abnormality detection, the overcharge detection circuits b1 to b1. A signal of H level (overcharge state) is forcibly output from bn. Further, by setting the overdischarge determination threshold voltage of the overdischarge detection circuits c1 to cn to V31 higher than the overcharge determination threshold voltage V20 at the time of normal cell abnormality detection, the overdischarge detection circuits c1 to cn Forcibly outputs an H level signal (overdischarge state). Thereby, as described above, an H level signal is input to the charge / discharge control circuit 13.
[0032]
On the other hand, for example, when the overcharge detection circuit b2 is out of order due to the failure of the comparator G2 and the L-level signal (normal state) is output from the overcharge detection circuit b2, the AND circuit e2 Therefore, the signal input from the AND circuit 11 to the charge / discharge control circuit 13 is also at the L level. Further, for example, when the overdischarge detection circuit c2 is out of order due to a failure of the comparator G3 and the L level signal (normal state) is output from the overdischarge detection circuit c2, the output of the AND circuit e2 is Since it becomes L level, the signal input from the AND circuit 11 to the charge / discharge control circuit 13 also becomes L level.
[0033]
That is, when the H-level signal is input when the charge / discharge control circuit 13 outputs the H-level diagnosis signal A and the L-level diagnosis signal B, the overcharge detection circuits b1 to bn and the overdischarge detection are detected. The circuits c1 to cn are normal, and when an L level signal is input, it is determined that any of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn has failed.
[0034]
<< When (A, B) = (L, H) >>
Next, a failure diagnosis method when the diagnostic signal A is at the L level and the diagnostic signal B is at the H level will be described. In the assembled battery abnormality detection device according to the present embodiment, first, a diagnostic signal (A, B) of a combination of (H, L) is output, and overcharge detection circuits b1 to bn and overdischarge detection circuit c1 are output. After the failure diagnosis of .about.cn is performed, a diagnosis signal (A, B) of a combination of (L, H) described later is output.
[0035]
First, the operation of the overcharge detection circuit b2 will be described. When an H level diagnostic signal B is output from the charge / discharge control circuit 13, an L level signal is input to the gate terminal of the P-type MOS transistor Q2, so that the MOS transistor Q2 is turned on. On the other hand, since the diagnostic signal A is at the L level, the N-type MOS transistor Q3 is turned off. In this case, when the MOS transistor Q2 is turned on and the MOS transistor Q3 is turned off, the voltage V22 obtained by dividing the power supply voltage Vcc by the resistors R22, R23, and R24 (= Vcc · (R23 + R24) / ( R22 + R23 + R24) is applied.
[0036]
The resistance values of the resistors R21 to R24 are determined so that the voltage V22 is higher than the overcharge determination threshold voltage V20. Since the voltage Vc of the cell s2 in a normal state that is neither overcharge nor overdischarge is lower than the overcharge determination threshold voltage V20 and higher than the overdischarge determination threshold voltage V30, it is applied to the negative terminal of the comparator G2. The voltage Vc is lower than the voltage V22 applied to the + terminal. Accordingly, since the output of the comparator G2 becomes H level, the signal output from the overcharge detection circuit b2 via the inverter INV2 becomes L level.
[0037]
Next, the operation of the overdischarge detection circuit c2 will be described. Since an H level signal is input to the gate terminal of the P-type MOS transistor Q4 via the inverter INV4, the MOS transistor Q4 is turned off. On the other hand, since the diagnostic signal B is at the H level, the N-type MOS transistor Q5 is turned on. In this case, when the MOS transistor Q4 is turned off and Q5 is turned on, the voltage V32 (= Vcc · R33 / (R31 + R32 + R33)) obtained by dividing the power supply voltage Vcc by the resistors R31, R32, and R33 is applied to the + terminal of the comparator G3. Applied.
[0038]
The resistance values of R31 to R34 are determined so that this voltage V32 is lower than the overdischarge determination threshold voltage V30 of the overdischarge detection circuit c2. As described above, since the voltage Vc of the cell s2 in the normal state is lower than the overcharge determination threshold voltage V20 and higher than the overdischarge determination threshold voltage V30, the voltage Vc applied to the negative terminal of the comparator G3. Becomes higher than the voltage V32 applied to the + terminal. Therefore, the output of the comparator G3, that is, the overdischarge detection circuit c2, becomes L level.
[0039]
When the diagnostic signal A is at the L level and the diagnostic signal B is at the H level, the L level signal is input to the two input terminals of the AND circuit 14, and thus the L level signal is output from the output terminal. Accordingly, the switch circuit f2 selects the output of the OR circuit d2. As described above, since an L level signal is output from both the overcharge detection circuit b2 and the overdischarge detection circuit c2, an L level signal is output from the OR circuit d2. The same applies to the operations of the other overcharge detection circuits b1, b3 to bn, overdischarge detection circuits c1, c3 to cn, and switch circuits f1, f3 to fn. At this time, since the switch circuit 12 selects the output from the OR circuit 10, the OR circuit 10 calculates the logical sum of the L level signals input to the plurality of input terminals. That is, an L level signal is input from the OR circuit 10 to the charge / discharge control circuit 13.
[0040]
Thus, by setting the overcharge determination threshold voltage of the overcharge detection circuits b1 to bn to V22 higher than the overcharge determination threshold voltage V20 at the time of normal cell abnormality detection, the overcharge detection circuits b1 to b1. A signal of L level (normal state) is forcibly output from bn. Further, by setting the overdischarge determination threshold voltage of the overdischarge detection circuits c1 to cn to V32 that is lower than the overdischarge determination threshold voltage V30 at the time of normal cell abnormality detection, the overdischarge detection circuits c1 to cn Forcibly outputs an L level signal (normal state). Thereby, as described above, an L level signal is input to the charge / discharge control circuit 13.
[0041]
On the other hand, for example, when the overcharge detection circuit b2 has failed due to a failure of the comparator G2 or the like and an H level signal (overcharge state) is output from the overcharge detection circuit b2, the OR circuit Since the output of d2 becomes H level, the signal input from the OR circuit 10 to the charge / discharge control circuit 13 also becomes H level. Further, for example, when the overdischarge detection circuit c2 fails due to a failure of the comparator G3 or the like and an H level signal (overdischarge state) is output from the overdischarge detection circuit c2, the output of the OR circuit d2 is also output. Becomes H level, the signal inputted from the OR circuit 10 to the charge / discharge control circuit 13 also becomes H level.
[0042]
That is, when the L level signal is input when the charge / discharge control circuit 13 outputs the L level diagnosis signal A and the H level diagnosis signal B, the overcharge detection circuits b1 to bn and the overdischarge detection are detected. The circuits c1 to cn are normal, and when an H level signal is input, it is determined that any of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn has failed.
[0043]
FIG. 3 shows a combination of signal levels of the diagnostic signals A and B output from the charge / discharge control circuit 13, a bypass voltage V1 used in the current bypass circuits a1 to an, and an overcharge used in the overcharge detection circuits b1 to bn. It is the figure which put together the relationship of determination threshold voltage V20-V23 and the overdischarge determination threshold voltage V30-V33 used with overdischarge detection circuit c1-cn. FIG. 3 also shows threshold voltages V23 and V33 when the diagnostic signals A and B are both at the H level, but they are not used in the assembled battery abnormality detection device in the present embodiment.
[0044]
FIGS. 4A to 4C illustrate the relationship between the overcharge determination threshold voltages V20 to V23 and the overdischarge determination threshold voltages V30 to V33. 4A shows the overcharge determination threshold voltage V20 and the overdischarge determination threshold voltage V30 in the normal state, and FIG. 4B shows that the diagnostic signals (A, B) are (H, L). FIG. 4C shows the determination threshold voltage when the diagnostic signal (A, B) is (L, H). In the figure, ● represents the voltage variation of each cell.
[0045]
As described above, according to the battery pack abnormality detection device in the embodiment, the overcharge determination threshold voltage used in the overcharge detection circuits b1 to bn provided for each of the plurality of cells s1 to sn, and the overdischarge By changing the overdischarge determination threshold voltage used in the detection circuits c1 to cn, failures in the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn can be reliably detected. That is, at the time of failure diagnosis, the overcharge determination threshold voltage is set to a voltage V21 lower than the normal overdischarge determination threshold voltage V30, and the overdischarge determination threshold voltage is set to the normal overcharge determination threshold voltage. By setting the voltage V31 higher than V20, the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn always output signals indicating cell abnormalities (overcharge state or overdischarge state). On the other hand, if a signal indicating a cell abnormality is not output, it can be determined that one of the plurality of overcharge detection circuits b1 to bn and overdischarge detection circuits c1 to cn has failed.
[0046]
At the time of failure diagnosis, the overcharge determination threshold voltage is set to a voltage V22 higher than the normal overcharge determination threshold voltage V20, and the overdischarge determination threshold voltage is set to the normal overdischarge determination threshold voltage. By setting the voltage V32 lower than V30, the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn always give a signal (H level) indicating a cell abnormality (overcharge state or overdischarge state). Not output. Conversely, if a signal indicating a cell abnormality is output, it can be determined that one of the plurality of overcharge detection circuits b1 to bn and overdischarge detection circuits c1 to cn has failed.
[0047]
In the battery pack abnormality detection device according to the present embodiment, AND circuits e1 to en, 11 for calculating the logical product of the output signals of the plurality of overcharge detection circuits b1 to bn and the output signals of the overdischarge detection circuits c1 to cn. And OR circuits d1 to dn, 10 for calculating a logical sum. When detecting the overcharge state and overdischarge state of the cell, the output signals from the OR circuits d1 to dn, 10 are selected, but the overcharge determination threshold voltage is set to V21, and the overdischarge determination is performed. When the threshold voltage is set to V31, the output signals from the AND circuits e1 to en and 11 are selected using the switch circuits f1 to fn and 12. Accordingly, when an L level signal is output from any one of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn, the signal input from the AND circuit 11 to the charge / discharge control circuit 13 is also L. Therefore, the failure of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn can be reliably detected.
[0048]
When the overcharge determination threshold voltage is set to V22 and the overdischarge determination threshold voltage is set to V32, the switch circuits f1 to fn and 12 are used to output from the OR circuits d1 to dn and 10. Select the output signal. Accordingly, when an H level signal is output from any one of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn, the signal input from the OR circuit 10 to the charge / discharge control circuit 13 is also H. Therefore, the failure of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn can be reliably detected.
[0049]
That is, according to the battery pack abnormality detection device of the present embodiment, there is no need to add a new circuit for performing failure diagnosis of the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn. By changing the abnormality determination threshold values of the detection circuits b1 to bn and c1 to cn, failure diagnosis can be performed reliably.
[0050]
In the assembled battery abnormality detection device according to the embodiment described above, a diagnostic signal (A, B) of a combination of (H, L) is output, and the overcharge detection circuits b1 to bn and overdischarge detection circuits c1 to cn are output. After performing the failure diagnosis, a diagnosis signal (A, B) of a combination of (L, H) is output to perform the failure diagnosis. Thereby, the accuracy of failure diagnosis of the overcharge detection circuits b1 to bn or the overdischarge detection circuits c1 to cn can be further increased.
[0051]
The overcharge determination threshold voltages V21 and V22 and the overdischarge determination threshold voltages V31 and V32 are changed, the output signals from the AND circuits e1 to en and 11 and the OR circuits d1 to dn and 10 are output. Since switching to the output signal is performed based on the common diagnostic signals A and B, the signal lines can be saved.
[0052]
The failure diagnosis of the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn is performed when the assembled battery abnormality detection device according to the present embodiment is started (when the power is turned on), and abnormalities of the cells s1 to sn (overcharge or This is performed when a signal indicating overdischarge) is not output, or when charging / discharging of the assembled battery 1 is stopped for a certain period or longer. Thereby, the failure diagnosis is performed when the terminal voltage of the cell is stable, so that the failure diagnosis can be performed with higher accuracy.
[0053]
The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, after the diagnosis signal (A, B) of the combination (H, L) is output and the failure diagnosis is performed, the diagnosis signal (A, B) of the combination (L, H) is performed. ) Is output, but failure diagnosis can be performed with only one of them. However, the accuracy of the failure diagnosis is lower than that when a diagnosis signal (A, B) of a combination of (H, L) and (L, H) is output to perform the failure diagnosis.
[0054]
Further, the overcharge determination threshold voltage V21 when the diagnostic signal (A, B) of the combination of (H, L) is output is set to a value lower than the normal overdischarge determination threshold voltage V30, and overdischarge determination is performed. Although the threshold voltage V31 is set to a value higher than the normal overcharge determination threshold voltage V20, it is not always necessary to maintain such a relationship. That is, by setting the overcharge determination threshold voltage V21 at the time of failure diagnosis, an H level signal (overcharge state) is always output from the overcharge detection circuits b1 to bn where no failure has occurred, and at the time of failure diagnosis. By setting the overdischarge determination threshold voltage V31, the determination threshold voltages V21, V21, V so that an H level signal (overdischarge state) is always output from the overdischarge detection circuits c1 to cn in which no failure has occurred. V31 may be set.
[0055]
Similarly, the overdischarge determination threshold voltage V22 when the diagnostic signal (A, B) of the combination of (L, H) is output is set to a value higher than the normal overcharge determination threshold voltage V20, and overdischarge determination is performed. Although the threshold voltage V32 is set to a value lower than the normal overdischarge determination threshold voltage V30, such a relationship is not necessarily maintained. That is, by setting the overcharge determination threshold voltage V22 at the time of failure diagnosis, an L level signal (normal state) is always output from the overcharge detection circuits b1 to bn where no failure has occurred, and at the time of failure diagnosis. By setting the overdischarge determination threshold voltage V32, the determination threshold voltages V22 and V32 are set so that an L level signal (normal state) is always output from the overdischarge detection circuits c1 to cn in which no failure has occurred. It only has to be set.
[0056]
The correspondence between the constituent elements of the claims and the constituent elements of the embodiment is as follows. That is, the overcharge detection circuits b1 to bn and the overdischarge detection circuits c1 to cn calculate the abnormality detection circuit, the charge / discharge control circuit 13 calculates the determination voltage change circuit and the failure diagnosis circuit, and the OR circuits d1 to dn and 10 calculate the logical sum. In the circuit, AND circuits e1 to en, 11 constitute a logical product calculation circuit. In addition, as long as the characteristic function of this invention is not impaired, each component is not limited to the said structure.
[Brief description of the drawings]
FIG. 1 is a diagram showing the configuration of an assembled battery abnormality detection device according to an embodiment of the present invention;
FIG. 2 is a diagram showing a detailed configuration of a current bypass circuit, an overcharge detection circuit, and an overdischarge detection circuit.
FIG. 3 shows diagnostic signals A and B, a threshold V voltage used in a current bypass circuit, an overcharge determination threshold voltage used in an overcharge detection circuit, and an overdischarge determination used in an overdischarge detection circuit. Diagram showing relationship with threshold voltage
FIG. 4A shows normal overcharge determination threshold voltage V20 and overdischarge determination threshold voltage V30, and FIG. 4B shows diagnosis signals (A, B) of (H , L), and FIG. 4C shows the determination threshold voltages when the diagnostic signals (A, B) are (L, H).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Battery pack, 10 ... OR circuit, 11 ... AND circuit, 12 ... Switch circuit, 13 ... Charge / discharge control circuit, 14 ... AND circuit, 15 ... Inverter, s1-sn ... Cell, a1-an ... Current bypass circuit, b1 to bn... overcharge detection circuit, c1 to cn... overdischarge detection circuit, d1 to dn... OR circuit, e1 to en. , R24, R31, R32, R33, R34 ... resistors, G1 to G3 ... comparators, Q1 to Q5 ... MOS transistors, INV1 to INV4 ... inverters

Claims (10)

In the battery pack abnormality detection device composed of a plurality of rechargeable cells,
An abnormality detection circuit that is provided for each of the plurality of cells and detects an abnormality of the corresponding cell based on a terminal voltage and an abnormality determination voltage of the corresponding cell;
A determination voltage changing circuit for changing a voltage value of the abnormality determination voltage;
A failure diagnosis circuit that performs failure diagnosis of the abnormality detection circuit based on an abnormality detection result performed by the abnormality detection circuit based on the abnormality determination voltage changed by the determination voltage change circuit; An abnormality detection device for an assembled battery. In the assembled battery abnormality detection device according to claim 1,
The abnormality detection circuit includes an overcharge detection circuit that detects an overcharge state of the corresponding cell when a terminal voltage of the corresponding cell becomes equal to or higher than a first overcharge determination voltage, and the terminal voltage of the corresponding cell An overdischarge detection circuit that detects an overdischarge state of the corresponding cell when the overdischarge determination voltage is 1 or less,
The determination voltage changing circuit changes voltage values of the first overcharge determination voltage and the first overdischarge determination voltage,
The failure diagnosis circuit is changed in the overcharge determination result performed in the overcharge detection circuit based on the second overcharge determination voltage changed in the determination voltage change circuit, and changed in the determination voltage change circuit. A failure diagnosis of the overcharge detection circuit and the overdischarge detection circuit is performed based on an overdischarge determination result performed by the overdischarge detection circuit based on the second overdischarge determination voltage. An assembled battery abnormality detection device. In the assembled battery abnormality detection device according to claim 2,
The determination voltage changing circuit sets the second overcharge determination voltage to be lower than the first overdischarge determination voltage. In the assembled battery abnormality detection device according to claim 2 or 3,
The determination voltage changing circuit sets the second overdischarge determination voltage to be higher than the first overcharge determination voltage. In the assembled battery abnormality detection device according to claim 3 or 4,
A logical sum calculation circuit for calculating a logical sum of output signals of the plurality of overcharge detection circuits and output signals of the plurality of overdischarge detection circuits;
A logical product calculation circuit for calculating a logical product of the output signals of the plurality of overcharge detection circuits and the output signals of the plurality of overdischarge detection circuits;
A switching circuit for switching between the output of the logical sum calculation circuit and the output of the logical product calculation circuit,
The switching circuit selects an output of the logical sum calculation circuit when detecting an overcharge state and an overdischarge state of the plurality of cells, and performs a fault diagnosis of the overcharge detection circuit and the overdischarge detection circuit. In this case, an abnormality detection apparatus for an assembled battery, wherein the output of the logical product calculation circuit is selected. In the assembled battery abnormality detection device according to claim 2,
The determination voltage change circuit sets the second overcharge determination voltage to be higher than the first overcharge determination voltage. In the assembled battery abnormality detection device according to claim 2 or 6,
The determination voltage changing circuit sets the second overdischarge determination voltage to be lower than the first overdischarge determination voltage. The assembled battery abnormality detection device according to claim 6 or 7,
A logical sum calculation circuit for calculating a logical sum of output signals of the plurality of overcharge detection circuits and output signals of the plurality of overdischarge detection circuits;
A logical product calculation circuit for calculating a logical product of the output signals of the plurality of overcharge detection circuits and the output signals of the plurality of overdischarge detection circuits;
A switching circuit for switching between the output of the logical sum calculation circuit and the output of the logical product calculation circuit,
The battery pack abnormality detection device, wherein the switching circuit selects an output of the logical sum calculation circuit when performing fault diagnosis of the overcharge detection circuit and the overdischarge detection circuit. In the assembled battery abnormality detection device according to claim 5 or 8,
A battery pack abnormality detection device, wherein the determination voltage change by the determination voltage change circuit and the switching by the switching circuit are performed based on a common signal. In the abnormality detection apparatus of the assembled battery in any one of Claims 1-9,
The failure diagnosis by the failure diagnosis circuit is performed when the assembled battery abnormality detection device is started, when a signal indicating abnormality of the plurality of cells is not output, and charging / discharging of the assembled battery is suspended for a predetermined period or more. An abnormality detection device for a battery pack, wherein

Images