JP2004119440A - Wiring board - Google Patents

Wiring board Download PDF

Info

Publication number
JP2004119440A
JP2004119440A JP2002277124A JP2002277124A JP2004119440A JP 2004119440 A JP2004119440 A JP 2004119440A JP 2002277124 A JP2002277124 A JP 2002277124A JP 2002277124 A JP2002277124 A JP 2002277124A JP 2004119440 A JP2004119440 A JP 2004119440A
Authority
JP
Japan
Prior art keywords
wiring layer
bonding wire
wiring
substrate
coating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002277124A
Other languages
Japanese (ja)
Inventor
Koichi Nakahara
中原　光一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002277124A priority Critical patent/JP2004119440A/en
Publication of JP2004119440A publication Critical patent/JP2004119440A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85469—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/85498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/85598—Fillers
    • H01L2224/85599—Base material
    • H01L2224/856—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/85498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/85598—Fillers
    • H01L2224/85599—Base material
    • H01L2224/856—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/85498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/85598—Fillers
    • H01L2224/85599—Base material
    • H01L2224/856—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/85498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/85598—Fillers
    • H01L2224/85599—Base material
    • H01L2224/856—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85663—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/85498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/85598—Fillers
    • H01L2224/85599—Base material
    • H01L2224/856—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85663—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85669—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which enables an aluminum bonding wire having a large diameter of 100 μm or above to be firmly connected to a wiring layer without causing cracks or delamination between the wiring layer and a board. <P>SOLUTION: The wiring board 4 is composed of a board 1 formed of electric insulating material, the wiring layer 2 which is formed of, at least, an element out of Au, Ag, Cu, Pd, and Pt, provided on the board 1 by spontaneous burning, equipped with a region where the aluminum bonding wire 5 whose diameter is 100 μm or above is joined, and an Ni coating layer 6 which is deposited, at least, on the region of the wiring layer 2 where the bonding wire 5 is joined, 4 to 13 μm in thickness, and has an arithmetic average surface roughness (Ra) of 0.1 to 0.3 μm. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子や容量素子、抵抗器等の電子部品が搭載される配線基板に関し、より詳細には大きな電流の流れを許容する直径の大きなボンディングワイヤが配線層に接続される配線基板に関するものである。
【０００２】
【従来の技術】
従来、半導体素子や容量素子、抵抗器等の電子部品が搭載される配線基板は酸化アルミニウム質焼結体等の電気絶縁材料から成り、表面に電子部品搭載部を有する基板と、該基板に形成されたタングステン、モリブデン等の高融点金属材料から成る配線層とで構成されており、基板の搭載部に半導体素子や容量素子、抵抗器等の電子部品を搭載するとともに各電子部品の電極を配線層にボンディングワイヤを介して電気的に接続するようになっている。
【０００３】
かかる配線基板は、配線層の一部を外部電気回路基板の配線導体に錫−鉛半田等の低融点ろう材を介し接続することによって外部電気回路基板上に実装され、同時に配線基板に搭載されている電子部品の各電極が所定の外部電気回路に電気的に接続されることとなる。
【０００４】
なお、前記電子部品の各電極を配線層に接続するボンディングワイヤの材料としては、一般にアルミニウム、金が使用されており、特に大電流を流すためにボンディングワイヤの径を大きくする必要があるような場合には経済性を重視してアルミニウム製のボンディングワイヤが多用される。
【０００５】
また前記配線層と電子部品の電極とのボンディングワイヤを介しての接続は、一般に超音波ボンダーを使用することによって行われており、具体的には配線層の表面にボンディングワイヤの一端を当接摺動させ、ボンディングワイヤと配線層表面との間に摩擦エネルギーを発生させるとともに該摩擦エネルギーでボンディングワイヤと配線層表面部分との間に金属拡散を行わせることによってボンディングワイヤは配線層に接合される。
【０００６】
この場合、従来のボンディングワイヤの直径は約３０μｍ程度であり、ボンディングワイヤは配線層の表面に対して約３０ｇｆ〜５０ｇｆ（０．２９４Ｎ〜０．４９Ｎ）の荷重で押し付けられ、摺動により摩擦エネルギーが効率よく発生するようにされている。
【０００７】
更に前記配線基板の配線層は、通常、その表面に平均の厚さが約３μｍのＮｉから成る被覆層がめっき法等により被着されており、超音波ボンダーを使用してのボンディングワイヤの接続性を良好としている。なお、前記Ｎｉから成る被覆層は、一般に、次亜リン酸ナトリウム等のリン系還元剤やジメチルアミンボラン等のホウ素系還元剤を用いる無電解Ｎｉめっき液を用いることによって形成され、被着されるＮｉから成る被覆層は、粗結晶体皮膜であり、その硬さはビッカース硬度で約１５０Ｈｖ程度である。
【０００８】
しかしながら、この従来の配線基板においては、タングステンやモリブデン等で形成されている配線層の電気抵抗値が高く、配線層を伝わる電気信号に電圧降下を招来させて配線層に接続されている半導体素子等の電子部品に電気信号を正確に入出力させることができないという欠点があった。特に配線層を伝わる電気信号の電流値が大きくなるほど、この欠点が顕著となる。
【０００９】
そこで上記欠点を解消するために、配線層をＣｕ（銅）やＡｇ（銀）、Ａｕ（金）等の電気抵抗値が低い金属材料で形成した配線基板が提案されている。
【００１０】
かかる配線基板によれば、配線層が電気抵抗値の低いＣｕやＡｇ、Ａｕ等で形成されていることから配線層に電気信号を伝搬させた場合、配線層で電気信号に大きな電圧降下を招来することはなく電子部品に電気信号を正確に伝えることが可能となる。
【００１１】
【発明が解決しようとする課題】
しかしながら、近時、配線基板はＥＣＵ（Ｅｌｅｃｔｒｏｎｉｃ　Ｃｏｎｔｒｏｌ　Ｕｎｉｔ）用の基板等、約５Ａ以上という大電流の電気信号を流す必要のある用途での使用が増加しつつあり、この場合、配線基板上に搭載されている電子部品に大電流を流すために配線層と電子部品とを接続させるボンディングワイヤの直径を１００μｍ以上と非常に大きくする必要があり、このような直径の大きなボンディングワイヤを超音波ボンダーにより配線層に接続させようとすると、配線層と基板との間で亀裂やハガレ等の不具合が発生するという欠点が新たに発生するようになってきた。
【００１２】
このように配線層と基板との間で亀裂やハガレ等の不具合が発生する原因としては、直径が１００μｍ以上と大きなボンディングワイヤを配線層に接続する場合、ボンディングワイヤと配線層との間に大きな摩擦エネルギーを発生させる必要があり、この大きな摩擦エネルギーを発生させるためにボンディングワイヤを配線層表面に対して約９０ｇｆ〜６００ｇｆ（０．８８２Ｎ〜５．８８Ｎ）という非常に大きな荷重をかけなければならず、この大きな荷重が配線層と基板との界面に作用すること、ボンディングワイヤと配線層との摺動にともなって発生する大きな機械的応力が配線層と基板との界面に作用すること、配線層の表面を被覆するＮｉから成る被覆層の厚さが平均で約３μｍ程度と比較的薄く、機械的な応力を吸収する作用が小さいため前記荷重やボンディングワイヤと配線層との摺動にともなって発生する機械的応力が被覆層で吸収・緩和されずそのまま配線層と基板との界面に作用すること等が原因であると考えられる。
【００１３】
またこの従来の配線基板は、配線層を形成するＣｕやＡｇ、Ａｕ等の金属材料の融点が１０００℃〜１２００℃程度と低いため、これらのＣｕやＡｇ、Ａｕ等の金属材料の粉末を基板と同時焼成することにより配線層を形成する際、金属粉末が溶融することを防止するため、平均粒径が約１μｍ以上と比較的粗い金属粉末が使用され、これに応じて、配線層およびその表面に被着された被覆層の表面粗さが、算術平均粗さ（Ｒａ）で約１μｍ以上と粗い表面となっている。そのため直径が１００μｍ以上と大きなボンディングワイヤを配線層に超音波ボンダーにより接続する場合、配線層の表面に被着されているＮｉから成る被覆層の表面粗さが大きいため、配線層（実質的には被覆層）とボンディングワイヤとの広い接合面の全面にわたって良好かつ均一に両者を密着させることができなくなり、部分的に摩擦エネルギーが不十分となって、ボンディングワイヤと配線層との間の全面で十分な金属拡散を行わせることができなくなって、配線層へのボンディングワイヤの接続信頼性が低下するという欠点も有していた。
【００１４】
本発明は、上記欠点に鑑み案出されたもので、その目的は、配線層に直径が１００μｍ以上と大きな径のアルミニウム製ボンディングワイヤを、配線層と基板との間に亀裂やハガレ等の不具合が発生することなく、強固に接続させることができる配線基板を提供することにある。
【００１５】
【課題を解決するための手段】
本発明の配線基板は、電気絶縁材料から成る基板と、Ａｕ、Ａｇ、Ｃｕ、Ｐｄ、Ｐｔの少なくとも１種より成り、前記基板に同時焼成により形成され、かつ直径が１００μｍ以上のアルミニウム製ボンディングワイヤが接合される領域を有する配線層と、前記配線層の少なくともボンディングワイヤが接合される領域に被着され、厚さが４μｍ乃至１３μｍ、表面の粗さが算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍであるＮｉから成る被覆層とで形成されていることを特徴とするものである。
【００１６】
また本発明の配線基板は、前記Ｎｉから成る被覆層の硬さがビッカース硬度で２００Ｈｖ以上であることを特徴とするものである。
【００１７】
本発明の配線基板によれば、配線層がＡｕ（金）、Ａｇ（銀）、Ｃｕ（銅）、Ｐｄ（パラジウム）、Ｐｔ（白金）の少なくとも１種より成り、低電気抵抗であることから配線層に電気信号を伝搬させた際、配線層で電気信号に大きな電圧降下を招来することはなく電気信号を正確に伝えることができる。
【００１８】
また本発明の配線基板によれば、前記配線層のボンディングワイヤが接続される領域に、厚さが４μｍ乃至１３μｍのＮｉから成る被覆層を被着させ、被覆層の厚さを４μｍ乃至１３μｍと厚くしたことから配線層に直径が１００μｍ以上と大きなボンディングワイヤを接続させる場合、ボンディングワイヤを配線層表面に押し付ける荷重、ボンディングワイヤと配線層との摺動にともなって発生する機械的応力は被覆層で吸収・緩和されて小さくなり、その結果、配線層と基板との界面に大きな力が作用することはなく、配線層と基板との間で亀裂やハガレ等の不具合が発生するのを有効に防止して配線層を基板に強固に接合させておくことができる。
【００１９】
更に本発明の配線基板によれば、配線層の表面に被着されているＮｉから成る被覆層の表面粗さを算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍとし、適度に平滑にしたことから配線層に直径が１００μｍ以上と大きなボンディングワイヤを超音波ボンダーで接続する場合、Ｎｉから成る被覆層とボンディングワイヤとを接合面の全面で良好に密着させ、両者間の全面にわたって均一に大きな摩擦エネルギーを発生させてボンディングワイヤと配線層との間に十分な金属拡散を行わせることができ、これによって配線層へのボンディングワイヤの接続信頼性を高いものとなすことができる。
【００２０】
【発明の実施の形態】
次に本発明を添付図面に基づき詳細に説明する。
【００２１】
図１及び図２は本発明の配線基板をＥＣＵ（Ｅｌｅｃｔｒｏｎｉｃ　Ｃｏｎｔｒｏｌ　Ｕｎｉｔ）基板等の半導体素子搭載用の基板に適用した場合の一実施例を示し、１は基板、２は配線層である。この基板１と配線層２とで半導体素子３を搭載するための配線基板４が形成される。
【００２２】
前記配線基板４の基板１は半導体素子３を支持する支持部材として作用し、上面の略中央部に半導体素子３がガラス、ろう材、樹脂等の接着材を介して取着固定される。
【００２３】
前記基板１は、ガラスセラミック焼結体や結晶性ガラス、マンガン化合物を添加すること等により１２００℃の低温焼成を可能とした酸化アルミニウム質焼結体等の電気絶縁材料から成り、例えば、ガラスセラミック焼結体から成る場合であれば、酸化珪素、酸化ホウ素、酸化カルシウム等のガラス粉末と、酸化アルミニウム、ムライト等のセラミック粉末とから成るガラスセラミック原料粉末に適当な有機バインダ、溶剤等を添加混合して泥漿物を作るとともに該泥漿物をドクターブレード法やカレンダーロール法を採用することによってガラスセラミックグリーンシート（ガラスセラミック生シート）と成し、しかる後、前記ガラスセラミックグリーンシートに適当な打ち抜き加工を施すとともに必要に応じてこれを複数枚積層し、約９００℃の温度で焼成することによって製作される。
【００２４】
また前記基板１はその上面で半導体素子３が搭載実装される領域周辺から下面にかけて複数の配線層２が形成してあり、該配線層２の基板１上面に露出する部位には半導体素子３の電極がボンディングワイヤ５を介して接続され、また基板１の下面に導出する部位は外部の電気回路基板に半田等の導電性接続材を介して接続される。
【００２５】
前記配線層２は半導体素子３の各電極を外部電気回路に接続するための導電路として作用し、半導体素子３の各電極をボンディングワイヤ５を介し配線層２に接続することによって半導体素子３の各電極は配線層２を介して外部電気回路に接続されることとなる。
【００２６】
前記配線層２は、Ａｕ、Ａｇ、Ｃｕ、Ｐｄ、Ｐｔの少なくとも１種より成り、このようなＡｕ、Ａｇ、Ｃｕ、Ｐｄ、Ｐｔ等から成る配線層２は電気抵抗値が小さいことから配線層２に電気信号を伝搬させた場合、配線層２で電気信号に大きな電圧降下を招来することはなく半導体素子３に電気信号を正確に伝えることが可能となる。
【００２７】
前記配線層２は、例えば、Ａｇから成る場合であれば、Ａｇ粉末に適当な有機バインダ及び溶剤を添加混合して金属ペーストを作成し、この金属ペーストを基板１となるガラスセラミックグリーンシートの表面に所定パターンに印刷塗布することによって基板１の上面から下面にかけて所定パターンに形成される。
【００２８】
また前記配線層２は、基板１の上面に露出する領域に半導体素子３の電極が、直径が１００μｍ以上のアルミニウム製ボンディングワイヤ５を介して接続され、これによって半導体素子３の各電極がボンディングワイヤ５を介して配線層２に電気的に接続されることとなる。
【００２９】
前記ボンディングワイヤ５はその直径が１００μｍ以上と大きいことからボンディングワイヤ５を介して配線層２から半導体素子３に約５Ａ以上という大電流の電気信号を流した場合、大電流の電気信号は何ら支障をきたすことなく半導体素子３に伝搬させることができる。
【００３０】
前記ボンディングワイヤ５はその直径が１００μｍ未満となると５Ａ以上の大電流の電気信号を伝搬させることが困難となる。従って、前記ボンディングワイヤ５はその直径が１００μｍ以上に特定される。
【００３１】
なお、前記配線層２へのボンディングワイヤ５の接続は、配線層２の表面にボンディングワイヤ５の一端を約９０ｇｆ〜６００ｇｆ（０．８８２Ｎ〜５．８８Ｎ）という大きな荷重で押し付けて摺動させ、ボンディングワイヤ５と配線層２表面との間に摩擦エネルギーを発生させるとともに該摩擦エネルギーでボンディングワイヤ５と配線層２表面部分との間に金属拡散を行わせることによって行われる。
【００３２】
また前記配線層２は更に少なくともボンディングワイヤ５が接続される領域に、図２に示す如く、厚さが４μｍ乃至１３μｍのＮｉから成る被覆層６が被着されており、該Ｎｉから成る被覆層６は無電解めっき法等により形成され、例えば、次亜リン酸ナトリウム等のリン系還元剤やジメチルアミンボラン等のホウ素系還元剤を用いる無電解Ｎｉめっき液中に配線層２を所定時間浸漬することにより形成される。
【００３３】
前記Ｎｉから成る被覆層６はアルミニウム製のボンディングワイヤ５との間で金属拡散が生じやすく、これによって配線層２にボンディングワイヤ５を強固に接続することができる。
【００３４】
また前記被覆層６は、その厚みが４μｍ乃至１３μｍと厚いことから配線層２を完全に被覆して配線層２の酸化等を有効に防止することができるとともに配線層２に直径が１００μｍ以上と大きなボンディングワイヤ５を接続させる場合、ボンディングワイヤ５を配線層２表面に押し付ける荷重、ボンディングワイヤ５と配線層２との摺動にともなって発生する機械的応力は被覆層６で吸収・緩和されて極めて小さな値となり、その結果、配線層２と基板１との界面に大きな力が作用することはなく、配線層２と基板１との間で亀裂やハガレ等の不具合が発生するのを有効に防止して配線層２を基板１に強固に接合させておくことが可能となる。
【００３５】
なお、前記被覆層６は、その厚さが４μｍ未満では、ボンディングワイヤ５を配線層２表面に押し付ける荷重、ボンディングワイヤ５と配線層２との摺動にともなって発生する機械的応力を十分に吸収緩和することができず、配線層２と基板１との界面に亀裂やハガレ等の不具合が生じてしまい、また、１３μｍを超えると、その皮膜内部応力が非常に大きくなり被覆層６と配線層２との間や、配線層２と基板１との間での接合強度が劣化し、被覆層６が配線層２より剥離したり、配線層２が基板１より剥離したりしてしまう。従って、前記被覆層６は、その厚さが４μｍ乃至１３μｍの範囲に特定される。
【００３６】
また、前記被覆層６は、その厚みを５μｍ乃至１０μｍの範囲としておくと、ボンディングワイヤ５を配線層２により一層確実、強固に接続させることができるできるとともに被覆層６が配線層２より剥離したり、配線層２が基板１より剥離したりしてしまうのを完全に防止して配線基板としての信頼性をより一層良好となすことができる。したがって、前記被覆層６は、その厚さを５μｍ乃至１０μｍの範囲としておくことがより一層好ましい。
【００３７】
更に前記被覆層６は、その硬さをビッカース硬度で２００Ｈｖ以上としておくと、ボンディングワイヤ５を配線層２表面に押し付ける荷重で大きく変形することはなく、これによって前記荷重は配線層２と基板１との界面に伝わることが効果的に遮断され、その結果、配線層２と基板との界面に大きな力が作用することはなく、配線層２と基板１との間で亀裂やハガレ等の不具合が発生するのをより一層効果的に防止し配線層２を基板１により強固に接合させておくことが可能となる。したがって、前記被覆層６は、その硬さをビッカース硬度で２００Ｈｖ以上としておくことが好ましい。
【００３８】
前記被覆層６の硬さをビッカース硬度で２００Ｈｖ以上と硬くするには、厚さが４μｍ乃至１３μｍとなるようにしてＮｉをめっき法等で配線層２の表面に被着させた後、熱処理を加え、Ｎｉ３ＰやＮｉ３Ｂなどの金属間化合物を析出させることによる析出硬化を行なったり、Ｎｉの結晶を緻密化させて、硬さが２００Ｈｖ以上となるようにする方法や、無電解めっき法でＮｉから成る被覆層を形成する過程で、めっき時間を長くすることによりＮｉの結晶の緻密化を図り硬さを２００Ｈｖ以上と硬くする等の方法を用いることができる。
【００３９】
なお、めっき法等でＮｉを配線層２の表面に被着させ、被覆層６を形成する場合、その硬さをビッカース硬度で５００Ｈｖを超えるようなものとしようとすると、必要以上にめっき時間を長くしたり、高温でＮｉを熱処理したりする必要が生じ、生産性や経済性を低下させるおそれがある。したがって、前記被覆層６は、その硬さを、ビッカース硬度で２００Ｈｖ乃至５００Ｈｖの範囲とすることがより一層好ましい。
【００４０】
また前記被覆層６は、その表面の粗さが算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍの範囲としておく必要がある。
【００４１】
前記被覆層６の表面粗さを算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍとし適度に平滑にしておくと、配線層２に直径が１００μｍ以上と大きなボンディングワイヤ５を超音波ボンダーで接続する場合、Ｎｉから成る被覆層６とボンディングワイヤ５とを接合面の全面にわたって良好に密着させることができ、両者間の全面で大きな摩擦エネルギーを発生させてボンディングワイヤ５と配線層２との間に十分な金属拡散を行わせることができ、これによって配線層２へのボンディングワイヤ５の接続信頼性を高いものとなすことができる。
【００４２】
前記被覆層６はその表面の粗さが算術平均粗さ（Ｒａ）で０．１μｍ未満となると、平滑になり過ぎるため、被覆層６とボンディングワイヤ２との間で大きな摩擦エネルギーを発生させることができず、ボンディングワイヤと配線層との間に十分な金属拡散を行わせることができなくなって、配線層２とボンディングワイヤ５との接続信頼性が低下することとなってしまう。また表面の粗さが算術平均粗さ（Ｒａ）で０．３μｍを超えると、配線層２に直径が１００μｍ以上と大きなボンディングワイヤ５を超音波ボンダーで接続する場合、被覆層６とボンディングワイヤ５との広い接合面の全面にわたって良好かつ均一に両者を密着させることができなくなり、部分的に摩擦エネルギーが不十分となって、ボンディングワイヤ５と被覆層６との間の全面で十分な金属拡散を行わせることができなくなって、配線層２にボンディングワイヤ５を強固に接続することができない。従って、前記被覆層６はその表面の粗さが算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍの範囲に特定される。
【００４３】
前記被覆層６の表面を算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍの範囲とするには、例えば、配線層２に無電解めっき法によりＮｉから成るめっき層を被着させることにより被覆層６を形成する場合、無電解Ｎｉめっき液中に結晶調整剤（光沢剤）として硫黄化合物等やＢｉ、Ｓｅ、Ｔｅ等を適量添加したり、ＮｉおよびＮｉと共析するリンやボロンとの安定度定数（錯化力）が異なる錯化剤を２〜３種類組み合わせたり、ｐＨ、液温、撹拌スピード等のめっき条件を、配線層２の表面状態等に応じて調整したりすることによって、配線層２表面の凹凸を埋めて平滑化させるようにしてＮｉを析出・被着させる、等の方法を用いることができる。
【００４４】
かくして半導体素子３が搭載された配線基板４は、半導体素子３を蓋体や封止樹脂等の封止材（不図示）を用いて封止するとともに、ＭＯＳ−ＦＥＴ、コンデンサー等の電子部品（不図示）を搭載し、その電極を配線層２に接続することにより製品としてのＥＣＵ（Ｅｌｅｃｔｒｏｎｉｃ　Ｃｏｎｔｒｏｌ　Ｕｎｉｔ）基板が完成する。
【００４５】
なお本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例において前記配線層２の外周上端の角（稜線）部分を円弧状に面取りしておくと、この角部分で、配線層２と被覆層６との被着界面に応力が集中し、被覆層６に亀裂等の機械的な破壊が生じることを効果的に防止することができる。したがって、前記配線層２は、その外周上端の角（稜線）部分を円弧状に面取りしておくことが好ましい。
【００４６】
【発明の効果】
本発明の配線基板によれば、配線層がＡｕ（金）、Ａｇ（銀）、Ｃｕ（銅）、Ｐｄ（パラジウム）、Ｐｔ（白金）の少なくとも１種より成り、低電気抵抗であることから配線層に電気信号を伝搬させた際、配線層で電気信号に大きな電圧降下を招来することはなく電気信号を正確に伝えることができる。
【００４７】
また本発明の配線基板によれば、前記配線層のボンディングワイヤが接続される領域に、厚さが４μｍ乃至１３μｍのＮｉから成る被覆層を被着させ、被覆層の厚さを４μｍ乃至１３μｍと厚くしたことから配線層に直径が１００μｍ以上と大きなボンディングワイヤを接続させる場合、ボンディングワイヤを配線層表面に押し付ける荷重、ボンディングワイヤと配線層との摺動にともなって発生する機械的応力は被覆層で吸収・緩和されて小さくなり、その結果、配線層と基板との界面に大きな力が作用することはなく、配線層と基板との間で亀裂やハガレ等の不具合が発生するのを有効に防止して配線層を基板に強固に接合させておくことができる。
【００４８】
更に本発明の配線基板によれば、配線層の表面に被着されているＮｉから成る被覆層の表面粗さを算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍとし、適度に平滑にしたことから配線層に直径が１００μｍ以上と大きなボンディングワイヤを超音波ボンダーで接続する場合、Ｎｉから成る被覆層とボンディングワイヤとを接合面の全面で良好に密着させ、両者間の全面にわたって均一に大きな摩擦エネルギーを発生させてボンディングワイヤと配線層との間に十分な金属拡散を行わせることができ、これによって配線層へのボンディングワイヤの接続信頼性を高いものとなすことができる。
【図面の簡単な説明】
【図１】本発明の配線基板の一実施例を示す断面図である。
【図２】本発明の配線基板の一実施例の要部拡大断面図である。
【符号の説明】
１・・・・基板
２・・・・配線層
３・・・・半導体素子
４・・・・配線基板
５・・・・ボンディングワイヤ
６・・・・被覆層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board on which electronic components such as a semiconductor element, a capacitance element, and a resistor are mounted, and more particularly, to a wiring board in which a large-diameter bonding wire allowing a large current flow is connected to a wiring layer. It is.
[0002]
[Prior art]
Conventionally, a wiring board on which electronic components such as a semiconductor element, a capacitance element, and a resistor are mounted is made of an electrically insulating material such as an aluminum oxide sintered body, and has a substrate having an electronic component mounting portion on a surface and a wiring board formed on the substrate. And a wiring layer made of a refractory metal material such as tungsten, molybdenum, etc., which mounts electronic components such as semiconductor elements, capacitors, resistors, etc. on the mounting portion of the substrate and wires the electrodes of each electronic component. The layers are electrically connected via bonding wires.
[0003]
Such a wiring board is mounted on an external electric circuit board by connecting a part of a wiring layer to a wiring conductor of the external electric circuit board via a low melting point brazing material such as tin-lead solder, and is simultaneously mounted on the wiring board. Each of the electrodes of the electronic component is electrically connected to a predetermined external electric circuit.
[0004]
In addition, aluminum and gold are generally used as a material of a bonding wire for connecting each electrode of the electronic component to a wiring layer. In particular, it is necessary to increase the diameter of the bonding wire in order to flow a large current. In this case, aluminum bonding wires are frequently used with emphasis on economy.
[0005]
The connection between the wiring layer and the electrode of the electronic component via a bonding wire is generally performed by using an ultrasonic bonder. Specifically, one end of the bonding wire is brought into contact with the surface of the wiring layer. The bonding wire is bonded to the wiring layer by sliding to generate frictional energy between the bonding wire and the wiring layer surface and to cause metal diffusion between the bonding wire and the wiring layer surface portion with the frictional energy. You.
[0006]
In this case, the diameter of the conventional bonding wire is about 30 μm, and the bonding wire is pressed against the surface of the wiring layer with a load of about 30 gf to 50 gf (0.294 N to 0.49 N), and the frictional energy is generated by sliding. Are generated efficiently.
[0007]
Further, the wiring layer of the wiring board is usually coated with a coating layer made of Ni having an average thickness of about 3 μm on its surface by plating or the like, and the bonding wires are connected using an ultrasonic bonder. The property is good. Incidentally, the coating layer made of Ni is generally formed by using an electroless Ni plating solution using a phosphorus-based reducing agent such as sodium hypophosphite or a boron-based reducing agent such as dimethylamine borane, and is applied. The coating layer made of Ni is a coarse crystalline film, and its hardness is about 150 Hv in Vickers hardness.
[0008]
However, in this conventional wiring board, a wiring layer formed of tungsten, molybdenum, or the like has a high electric resistance, and causes a voltage drop in an electric signal transmitted through the wiring layer, thereby causing a semiconductor element connected to the wiring layer to have a low voltage. There is a drawback that electric signals cannot be accurately input / output to / from such electronic components. In particular, the larger the current value of the electric signal transmitted through the wiring layer, the more remarkable this disadvantage.
[0009]
In order to solve the above-mentioned disadvantage, there has been proposed a wiring board in which the wiring layer is formed of a metal material having a low electric resistance such as Cu (copper), Ag (silver), or Au (gold).
[0010]
According to such a wiring board, since the wiring layer is formed of Cu, Ag, Au, or the like having a low electric resistance, when an electric signal is transmitted to the wiring layer, a large voltage drop occurs in the electric signal in the wiring layer. It is possible to accurately transmit the electric signal to the electronic component without performing the operation.
[0011]
[Problems to be solved by the invention]
However, recently, the use of a wiring board in an application requiring a large current of about 5 A or more to flow an electric signal such as a board for an ECU (Electronic Control Unit) is increasing. In order to allow a large current to flow through the mounted electronic component, the diameter of the bonding wire connecting the wiring layer and the electronic component needs to be very large, such as 100 μm or more. However, when a connection is made to the wiring layer, a defect such as a crack or peeling occurs between the wiring layer and the substrate.
[0012]
As described above, when a bonding wire having a diameter as large as 100 μm or more is connected to the wiring layer, a cause such as a crack or peeling between the wiring layer and the substrate is caused by a large gap between the bonding wire and the wiring layer. It is necessary to generate frictional energy, and in order to generate this large frictional energy, a very large load of about 90 gf to 600 gf (0.882 N to 5.88 N) must be applied to the bonding wire against the wiring layer surface. The large load acts on the interface between the wiring layer and the substrate, and the large mechanical stress generated due to the sliding between the bonding wire and the wiring layer acts on the interface between the wiring layer and the substrate. The thickness of the coating layer made of Ni which covers the surface of the layer is relatively thin, about 3 μm on average, and the effect of absorbing mechanical stress is small. Therefore, it is considered that the load and the mechanical stress generated due to the sliding between the bonding wire and the wiring layer are not absorbed or relieved by the coating layer and act on the interface between the wiring layer and the substrate as it is. Can be
[0013]
Further, in this conventional wiring board, since the melting point of a metal material such as Cu, Ag, or Au forming a wiring layer is as low as about 1000 ° C. to 1200 ° C., the powder of the metal material such as Cu, Ag, or Au is used as a substrate. When the wiring layer is formed by co-firing, a relatively coarse metal powder having an average particle size of about 1 μm or more is used in order to prevent the metal powder from being melted. The surface roughness of the coating layer deposited on the surface is as rough as about 1 μm or more in arithmetic average roughness (Ra). Therefore, when a bonding wire having a diameter as large as 100 μm or more is connected to the wiring layer by an ultrasonic bonder, the surface roughness of the Ni coating layer applied to the surface of the wiring layer is large. Can not be brought into good and uniform contact with the entire surface of the wide bonding surface between the bonding wire and the bonding wire, and the frictional energy becomes partially insufficient, and the entire surface between the bonding wire and the wiring layer becomes inadequate. In this case, the metal diffusion cannot be performed sufficiently, and the connection reliability of the bonding wire to the wiring layer is reduced.
[0014]
The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to provide an aluminum bonding wire having a diameter as large as 100 μm or more in a wiring layer and to provide a defect such as a crack or peeling between the wiring layer and the substrate. It is an object of the present invention to provide a wiring board that can be firmly connected without causing the occurrence of the problem.
[0015]
[Means for Solving the Problems]
The wiring board of the present invention comprises a board made of an electrically insulating material and at least one of Au, Ag, Cu, Pd, and Pt, and is formed on the board by simultaneous firing and has an aluminum bonding wire having a diameter of 100 μm or more. Is attached to a wiring layer having a region to be bonded and at least a region of the wiring layer to which a bonding wire is to be bonded, has a thickness of 4 μm to 13 μm, and has a surface roughness of 0. And a coating layer made of Ni having a thickness of 1 μm to 0.3 μm.
[0016]
Further, the wiring board of the present invention is characterized in that the hardness of the coating layer made of Ni is 200 Hv or more in Vickers hardness.
[0017]
According to the wiring board of the present invention, the wiring layer is made of at least one of Au (gold), Ag (silver), Cu (copper), Pd (palladium), and Pt (platinum) and has a low electric resistance. When the electric signal is propagated to the wiring layer, the electric signal can be accurately transmitted without causing a large voltage drop in the electric signal in the wiring layer.
[0018]
Further, according to the wiring substrate of the present invention, a coating layer made of Ni having a thickness of 4 μm to 13 μm is applied to a region of the wiring layer to which the bonding wire is connected, and the coating layer has a thickness of 4 μm to 13 μm. When a large bonding wire having a diameter of 100 μm or more is connected to the wiring layer due to the increase in thickness, the load that presses the bonding wire against the surface of the wiring layer and the mechanical stress generated due to the sliding between the bonding wire and the wiring layer are covered by the coating layer. Absorbed and relaxed by the above, it becomes smaller, and as a result, a large force does not act on the interface between the wiring layer and the substrate, and it is possible to effectively prevent defects such as cracks and peeling between the wiring layer and the substrate. This can prevent the wiring layer from being firmly bonded to the substrate.
[0019]
Further, according to the wiring board of the present invention, the surface roughness of the coating layer made of Ni applied to the surface of the wiring layer is set to 0.1 μm to 0.3 μm in arithmetic average roughness (Ra), and is moderately smooth. Therefore, when connecting a large bonding wire having a diameter of 100 μm or more to the wiring layer with an ultrasonic bonder, the coating layer made of Ni and the bonding wire are brought into close contact with the entire bonding surface, and uniform over the entire surface therebetween. In this case, a large amount of frictional energy can be generated to cause sufficient metal diffusion between the bonding wire and the wiring layer, whereby the connection reliability of the bonding wire to the wiring layer can be increased.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
[0021]
1 and 2 show an embodiment in which the wiring board of the present invention is applied to a board for mounting a semiconductor element such as an ECU (Electronic Control Unit) board, and 1 is a board and 2 is a wiring layer. The substrate 1 and the wiring layer 2 form a wiring substrate 4 on which the semiconductor element 3 is mounted.
[0022]
The substrate 1 of the wiring board 4 functions as a support member for supporting the semiconductor element 3, and the semiconductor element 3 is attached and fixed to a substantially central portion of the upper surface via an adhesive such as glass, brazing material, resin, or the like.
[0023]
The substrate 1 is made of an electrically insulating material such as a glass ceramic sintered body, crystalline glass, or an aluminum oxide sintered body that can be fired at a low temperature of 1200 ° C. by adding a manganese compound. In the case of a sintered body, an appropriate organic binder, a solvent, etc. are added to a glass-ceramic raw material powder composed of glass powder of silicon oxide, boron oxide, calcium oxide, etc. and ceramic powder of aluminum oxide, mullite, etc., and mixed. To form a glass ceramic green sheet (glass ceramic green sheet) by employing a doctor blade method or a calender roll method, and then appropriately punching the glass ceramic green sheet. And, if necessary, laminating a plurality of the It is manufactured by firing at a temperature of 0 ° C..
[0024]
On the upper surface of the substrate 1, a plurality of wiring layers 2 are formed from the periphery of the area where the semiconductor element 3 is mounted and mounted to the lower surface. The electrodes are connected via bonding wires 5, and a portion extending to the lower surface of the board 1 is connected to an external electric circuit board via a conductive connecting material such as solder.
[0025]
The wiring layer 2 functions as a conductive path for connecting each electrode of the semiconductor element 3 to an external electric circuit, and connects each electrode of the semiconductor element 3 to the wiring layer 2 via a bonding wire 5 to thereby form the semiconductor element 3. Each electrode is connected to an external electric circuit via the wiring layer 2.
[0026]
The wiring layer 2 is made of at least one of Au, Ag, Cu, Pd, and Pt. Since the wiring layer 2 made of such Au, Ag, Cu, Pd, and Pt has a small electric resistance value, When the electric signal is propagated to the semiconductor element 3, the electric signal can be accurately transmitted to the semiconductor element 3 without causing a large voltage drop in the electric signal in the wiring layer 2.
[0027]
When the wiring layer 2 is made of, for example, Ag, an appropriate organic binder and a solvent are added to and mixed with Ag powder to form a metal paste, and the metal paste is applied to the surface of the glass ceramic green sheet to be the substrate 1. Is formed in a predetermined pattern from the upper surface to the lower surface of the substrate 1 by printing and applying a predetermined pattern.
[0028]
In the wiring layer 2, the electrodes of the semiconductor element 3 are connected to the region exposed on the upper surface of the substrate 1 via aluminum bonding wires 5 having a diameter of 100 μm or more, whereby each electrode of the semiconductor element 3 is connected to the bonding wire. 5 to be electrically connected to the wiring layer 2.
[0029]
Since the bonding wire 5 has a diameter as large as 100 μm or more, when an electric signal of a large current of about 5 A or more flows from the wiring layer 2 to the semiconductor element 3 through the bonding wire 5, the electric signal of the large current does not cause any problem. Can be propagated to the semiconductor element 3 without causing the problem.
[0030]
When the diameter of the bonding wire 5 is less than 100 μm, it becomes difficult to transmit a large-current electric signal of 5 A or more. Therefore, the diameter of the bonding wire 5 is specified to be 100 μm or more.
[0031]
The connection of the bonding wire 5 to the wiring layer 2 is performed by pressing one end of the bonding wire 5 against the surface of the wiring layer 2 with a large load of about 90 gf to 600 gf (0.882 N to 5.88 N). This is performed by generating frictional energy between the bonding wire 5 and the surface of the wiring layer 2 and diffusing the metal between the bonding wire 5 and the surface of the wiring layer 2 by the frictional energy.
[0032]
Further, as shown in FIG. 2, a coating layer 6 made of Ni having a thickness of 4 μm to 13 μm is applied to the wiring layer 2 at least in a region to which the bonding wire 5 is connected. 6 is formed by an electroless plating method or the like. For example, the wiring layer 2 is immersed in an electroless Ni plating solution using a phosphorus-based reducing agent such as sodium hypophosphite or a boron-based reducing agent such as dimethylamine borane for a predetermined time. It is formed by doing.
[0033]
The coating layer 6 made of Ni is liable to cause metal diffusion between the bonding layer 5 and the aluminum bonding wire 5, whereby the bonding wire 5 can be firmly connected to the wiring layer 2.
[0034]
Further, since the coating layer 6 is as thick as 4 μm to 13 μm, it can completely cover the wiring layer 2 to effectively prevent oxidation and the like of the wiring layer 2 and has a diameter of 100 μm or more. When a large bonding wire 5 is connected, a load for pressing the bonding wire 5 against the surface of the wiring layer 2 and a mechanical stress generated by sliding between the bonding wire 5 and the wiring layer 2 are absorbed and relaxed by the coating layer 6. As a result, a large force does not act on the interface between the wiring layer 2 and the substrate 1, and it is possible to effectively prevent defects such as cracks and peeling between the wiring layer 2 and the substrate 1 from occurring. Thus, the wiring layer 2 can be firmly bonded to the substrate 1.
[0035]
When the thickness of the coating layer 6 is less than 4 μm, the load for pressing the bonding wire 5 against the surface of the wiring layer 2 and the mechanical stress generated due to the sliding between the bonding wire 5 and the wiring layer 2 are sufficiently reduced. Absorption cannot be alleviated, causing problems such as cracks and peeling at the interface between the wiring layer 2 and the substrate 1. When the thickness exceeds 13 μm, the internal stress of the coating becomes extremely large and the coating layer 6 and the wiring The bonding strength between the layer 2 and between the wiring layer 2 and the substrate 1 is deteriorated, and the coating layer 6 is separated from the wiring layer 2 or the wiring layer 2 is separated from the substrate 1. Therefore, the thickness of the coating layer 6 is specified in the range of 4 μm to 13 μm.
[0036]
When the thickness of the coating layer 6 is in the range of 5 μm to 10 μm, the bonding wire 5 can be more securely and firmly connected to the wiring layer 2, and the coating layer 6 is separated from the wiring layer 2. Also, it is possible to completely prevent the wiring layer 2 from being peeled off from the substrate 1 and to further improve the reliability as a wiring substrate. Therefore, it is more preferable that the thickness of the coating layer 6 be in the range of 5 μm to 10 μm.
[0037]
Further, when the hardness of the coating layer 6 is set to 200 Vv or more in Vickers hardness, the bonding wire 5 is not greatly deformed by a load pressing the surface of the wiring layer 2, whereby the load is reduced by the wiring layer 2 and the substrate 1. The transmission to the interface between the wiring layer 2 and the substrate 1 is effectively blocked, and as a result, a large force does not act on the interface between the wiring layer 2 and the substrate 1 and defects such as cracks and peeling between the wiring layer 2 and the substrate 1 Is more effectively prevented, and the wiring layer 2 can be more firmly joined to the substrate 1. Therefore, the coating layer 6 preferably has a hardness of 200 Hv or more in Vickers hardness.
[0038]
In order to increase the hardness of the coating layer 6 to 200 Hv or more in Vickers hardness, Ni is applied to the surface of the wiring layer 2 by plating or the like so as to have a thickness of 4 μm to 13 μm. In addition, a method of performing precipitation hardening by depositing an intermetallic compound such as Ni 3 P or Ni 3 B, or densifying the crystal of Ni so that the hardness becomes 200 Hv or more, or electroless plating In the process of forming the coating layer made of Ni by the method, it is possible to use a method of increasing the plating time to increase the density of the Ni crystal and increase the hardness to 200 Hv or more.
[0039]
When Ni is applied to the surface of the wiring layer 2 by plating or the like to form the coating layer 6, if the hardness is to exceed 500 Hv in Vickers hardness, the plating time will be longer than necessary. It is necessary to lengthen or heat-treat Ni at a high temperature, which may reduce productivity and economic efficiency. Therefore, it is even more preferable that the coating layer 6 has a hardness in the range of 200 to 500 Hv in Vickers hardness.
[0040]
The surface roughness of the coating layer 6 must be in the range of 0.1 μm to 0.3 μm in arithmetic average roughness (Ra).
[0041]
When the surface roughness of the coating layer 6 is set to be 0.1 μm to 0.3 μm in terms of arithmetic average roughness (Ra) and is appropriately smooth, the bonding wire 5 having a diameter of 100 μm or more is formed on the wiring layer 2 by an ultrasonic bonder. In this case, the coating layer 6 made of Ni and the bonding wire 5 can be satisfactorily brought into close contact with each other over the entire bonding surface, and a large frictional energy is generated on the entire surface between the two to form the bonding wire 5 with the wiring layer 2. In this case, sufficient metal diffusion can be performed, and thereby the connection reliability of the bonding wire 5 to the wiring layer 2 can be increased.
[0042]
When the surface roughness of the coating layer 6 is less than 0.1 μm in arithmetic average roughness (Ra), the coating layer 6 becomes too smooth, so that large frictional energy is generated between the coating layer 6 and the bonding wire 2. Therefore, sufficient metal diffusion cannot be performed between the bonding wire and the wiring layer, and the connection reliability between the wiring layer 2 and the bonding wire 5 is reduced. When the surface roughness exceeds 0.3 μm in arithmetic average roughness (Ra), when the bonding wire 5 having a large diameter of 100 μm or more is connected to the wiring layer 2 by an ultrasonic bonder, the coating layer 6 and the bonding wire 5 Cannot be adhered to each other in a good and uniform manner over the entire surface of the wide bonding surface, and the frictional energy becomes partially inadequate, and sufficient metal diffusion occurs over the entire surface between the bonding wire 5 and the coating layer 6. Cannot be performed, and the bonding wire 5 cannot be firmly connected to the wiring layer 2. Accordingly, the surface roughness of the coating layer 6 is specified in the range of 0.1 μm to 0.3 μm in arithmetic average roughness (Ra).
[0043]
To make the surface of the coating layer 6 have an arithmetic average roughness (Ra) in the range of 0.1 μm to 0.3 μm, for example, a plating layer made of Ni is applied to the wiring layer 2 by an electroless plating method. When the coating layer 6 is formed by the method, an appropriate amount of a sulfur compound or the like, Bi, Se, Te, or the like is added as a crystal modifier (brightening agent) to the electroless Ni plating solution, or Ni or phosphorus or boron eutectoid with Ni. Or two or three kinds of complexing agents having different stability constants (complexing power) from each other, and adjusting plating conditions such as pH, solution temperature, and stirring speed according to the surface condition of the wiring layer 2 and the like. This makes it possible to use a method of depositing and depositing Ni so as to fill and smooth the unevenness on the surface of the wiring layer 2.
[0044]
Thus, the wiring board 4 on which the semiconductor element 3 is mounted seals the semiconductor element 3 using a sealing material (not shown) such as a lid or a sealing resin, and also includes electronic components such as a MOS-FET and a capacitor. (Not shown) and connecting the electrodes to the wiring layer 2 to complete an ECU (Electronic Control Unit) substrate as a product.
[0045]
It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the spirit of the present invention. If the corners (ridges) are chamfered in an arc shape, stress concentrates on the adhered interface between the wiring layer 2 and the coating layer 6 at the corners, and mechanical destruction such as cracks occurs in the coating layer 6. This can be effectively prevented. Therefore, it is preferable that the corners (ridges) of the upper end of the outer periphery of the wiring layer 2 be chamfered in an arc shape.
[0046]
【The invention's effect】
According to the wiring board of the present invention, the wiring layer is made of at least one of Au (gold), Ag (silver), Cu (copper), Pd (palladium), and Pt (platinum) and has a low electric resistance. When the electric signal is propagated to the wiring layer, the electric signal can be accurately transmitted without causing a large voltage drop in the electric signal in the wiring layer.
[0047]
Further, according to the wiring substrate of the present invention, a coating layer made of Ni having a thickness of 4 μm to 13 μm is applied to a region of the wiring layer to which the bonding wire is connected, and the coating layer has a thickness of 4 μm to 13 μm. When a large bonding wire having a diameter of 100 μm or more is connected to the wiring layer due to the increase in thickness, the load that presses the bonding wire against the surface of the wiring layer and the mechanical stress generated due to the sliding between the bonding wire and the wiring layer are covered by the coating layer. Absorbed and relaxed by the above, it becomes smaller, and as a result, a large force does not act on the interface between the wiring layer and the substrate, and it is possible to effectively prevent defects such as cracks and peeling between the wiring layer and the substrate. This can prevent the wiring layer from being firmly bonded to the substrate.
[0048]
Further, according to the wiring board of the present invention, the surface roughness of the coating layer made of Ni applied to the surface of the wiring layer is set to 0.1 μm to 0.3 μm in arithmetic average roughness (Ra), and is moderately smooth. Therefore, when connecting a large bonding wire having a diameter of 100 μm or more to the wiring layer with an ultrasonic bonder, the coating layer made of Ni and the bonding wire are brought into close contact with the entire bonding surface, and uniform over the entire surface therebetween. In this case, a large amount of frictional energy can be generated to cause sufficient metal diffusion between the bonding wire and the wiring layer, whereby the connection reliability of the bonding wire to the wiring layer can be increased.
[Brief description of the drawings]
FIG. 1 is a sectional view showing one embodiment of a wiring board of the present invention.
FIG. 2 is an enlarged sectional view of a main part of an embodiment of the wiring board of the present invention.
[Explanation of symbols]
1 ... substrate 2 ... wiring layer 3 ... semiconductor element 4 ... wiring board 5 ... bonding wires 6 ... coating layer

Claims (2)

電気絶縁材料から成る基板と、Ａｕ、Ａｇ、Ｃｕ、Ｐｄ、Ｐｔの少なくとも１種より成り、前記基板に同時焼成により形成され、かつ直径が１００μｍ以上のアルミニウム製ボンディングワイヤが接合される領域を有する配線層と、前記配線層の少なくともボンディングワイヤが接合される領域に被着され、厚さが４μｍ乃至１３μｍ、表面の粗さが算術平均粗さ（Ｒａ）で０．１μｍ乃至０．３μｍであるＮｉから成る被覆層とで形成された配線基板。A substrate made of an electrically insulating material, and at least one of Au, Ag, Cu, Pd, and Pt, formed on the substrate by simultaneous firing, and having a region to which an aluminum bonding wire having a diameter of 100 μm or more is joined. The wiring layer is applied to at least a region of the wiring layer where the bonding wire is bonded, and has a thickness of 4 μm to 13 μm and a surface roughness of 0.1 μm to 0.3 μm in terms of arithmetic average roughness (Ra). A wiring board formed with a coating layer made of Ni. 前記Ｎｉから成る被覆層の硬さがビッカース硬度で２００Ｈｖ以上であることを特徴とする請求項１に記載の配線基板。2. The wiring board according to claim 1, wherein the hardness of the coating layer made of Ni is not less than 200 Hv in Vickers hardness.
JP2002277124A 2002-09-24 2002-09-24 Wiring board Withdrawn JP2004119440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002277124A JP2004119440A (en) 2002-09-24 2002-09-24 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002277124A JP2004119440A (en) 2002-09-24 2002-09-24 Wiring board

Publications (1)

Publication Number Publication Date
JP2004119440A true JP2004119440A (en) 2004-04-15

Family

ID=32272812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002277124A Withdrawn JP2004119440A (en) 2002-09-24 2002-09-24 Wiring board

Country Status (1)

Country Link
JP (1) JP2004119440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3588035A1 (en) * 2018-06-28 2020-01-01 Heraeus Nexensos GmbH A wire bonding arrangement and method of manufacturing a wire bonding arrangement

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3588035A1 (en) * 2018-06-28 2020-01-01 Heraeus Nexensos GmbH A wire bonding arrangement and method of manufacturing a wire bonding arrangement
WO2020001979A1 (en) * 2018-06-28 2020-01-02 Heraeus Nexensos Gmbh A wire bonding arrangement and method of manufacturing a wire bonding arrangement

Similar Documents

Publication Publication Date Title
JP2013214721A (en) Wiring board
JP2000340912A (en) Ceramic circuit board
JP2002057444A (en) Wiring board
JP2004200644A (en) Wiring board
JP2004119440A (en) Wiring board
JP2005072282A (en) Wiring board
JP3935026B2 (en) Wiring board
JP2004140108A (en) Wiring board
JP4174407B2 (en) Electronic component storage package
JP4683768B2 (en) Wiring board
JP2004119439A (en) Wiring board
JP4299421B2 (en) Manufacturing method of ceramic circuit board
JP2004119438A (en) Wiring board
JP2001102733A (en) Mounting method of electronic component
JP2014078627A (en) Wiring board, wiring board with solder bumps and semiconductor device
JP2004140105A (en) Wiring board
JP4721533B2 (en) Ceramic circuit board
JP4427467B2 (en) Wiring board and electric element module using the same
JP2004146444A (en) Wiring board
JP3898482B2 (en) Wiring board
JP2004172297A (en) Circuit board
JP3740407B2 (en) Wiring board
JPH10139559A (en) Glass-ceramic substrate and its manufacture
JPH07202356A (en) Circuit board
JPS61166144A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050309

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20060904

A072 Dismissal of procedure

Free format text: JAPANESE INTERMEDIATE CODE: A072

Effective date: 20070703