JP2004111987A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004111987A
JP2004111987A JP2003374084A JP2003374084A JP2004111987A JP 2004111987 A JP2004111987 A JP 2004111987A JP 2003374084 A JP2003374084 A JP 2003374084A JP 2003374084 A JP2003374084 A JP 2003374084A JP 2004111987 A JP2004111987 A JP 2004111987A
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Prior art keywords
resin
bump electrode
wafer
chip
semiconductor device
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Japanese (ja)
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Yoshikazu Takahashi
高橋　義和
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP2003374084A priority Critical patent/JP2004111987A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable chip-size package having resin on a side or a back of an LSI chip to prevent chipping. <P>SOLUTION: The chip-size package comprises a semiconductor chip having a surface on which an electrode pad is formed and a side formed by dicing; sealing resin that covers the surface and the side of the semiconductor chip with a thickness of the resin covering the side of at least 20 μm; and a bump electrode that is partially connected to the electrode pad and partially exposed from the sealing resin. <P>COPYRIGHT: (C)2004,JPO

Description

　本発明は樹脂封止された半導体素子、特にＬＳＩチップと略同じサイズのチップサイズパッケージに関するものである。 The present invention relates to a resin-encapsulated semiconductor element, in particular, a chip size package having substantially the same size as an LSI chip.

　従来このような分野の技術としては、半導体素子上にリードを形成し、このリードの一部にバンプを形成し、半導体素子の裏面を露出させた状態で樹脂封止するものがあった。このような技術は特開平８−３０６８５３号公報に開示されている。 Conventionally, as a technique in such a field, there has been a technique in which a lead is formed on a semiconductor element, a bump is formed on a part of the lead, and resin sealing is performed with the back surface of the semiconductor element exposed. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 8-306853.

　しかしながら、上記した半導体素子の製造方法では、個々のチップに分割してから個々のパッケージを作成しているので、その作成に工程数がおおくなり、製造が煩雑になる。
　本発明は、チップサイズパッケージを容易に作成できる製造方法に適した形状の半導体装置を提供することを目的とする。 However, in the semiconductor device manufacturing method described above, since individual packages are created after being divided into individual chips, the number of steps is increased in the production and the manufacturing becomes complicated.
An object of this invention is to provide the semiconductor device of the shape suitable for the manufacturing method which can produce a chip size package easily.

　上記目的を達成するために、本発明の半導体装置は、電極パッドが形成された表面とダイシングによって形成された側面とを有する半導体チップと、半導体チップの表面及び側面を覆い側面を覆う厚さは少なくとも２０μｍである封止樹脂と、一部は電極パッドと接続し他の一部は封止樹脂から露出するバンプ電極とを備える。 In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor chip having a surface on which electrode pads are formed and a side surface formed by dicing, and a thickness that covers the surface and side surface of the semiconductor chip and covers the side surface. A sealing resin that is at least 20 μm and a bump electrode that is partly connected to the electrode pad and the other part is exposed from the sealing resin.

　本発明に係る半導体装置によれば、ＬＳＩチップの側面あるいは裏面に樹脂が形成されているので、チップの欠けを防止することができ、信頼性の高いチップサイズパッケージを提供することができる。
　また、ウエハ表面に形成された樹脂に、ＬＳＩチップを個片に分割する際の切断部分を示す凹部を設けたので、個片に分割する際に目印となり、正確に分割することができる。 According to the semiconductor device of the present invention, since the resin is formed on the side surface or the back surface of the LSI chip, chip chipping can be prevented and a highly reliable chip size package can be provided.
Further, since the resin formed on the wafer surface is provided with a concave portion indicating a cut portion when the LSI chip is divided into individual pieces, it becomes a mark when the LSI chip is divided into individual pieces and can be accurately divided.

　以下、本発明の実施例について図面を参照しながら説明する。図1は本発明の第１実施形態を説明する断面図であり、１はＬＳＩチップ、２は１辺が約５０〜１００μｍ、高さ約１５μｍの金めっき等で形成されたバンプ電極、３はＬＳＩチップ表面保護のためのエポキシ樹脂であり、ＬＳＩチップ１の表面と側面を覆っている。また、エポキシ樹脂３の表面はバンプ電極２の表面と同じ高さになっている。４は外部基板と接続するためのハンダボールであり、直径約３００〜５００μｍ程度の球状である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention. 1 is an LSI chip, 2 is a bump electrode formed by gold plating or the like having a side of about 50 to 100 μm and a height of about 15 μm. This is an epoxy resin for protecting the LSI chip surface, and covers the surface and side surfaces of the LSI chip 1. The surface of the epoxy resin 3 is the same height as the surface of the bump electrode 2. Reference numeral 4 denotes a solder ball for connection to an external substrate, which has a spherical shape with a diameter of about 300 to 500 μm.

　次にこのような半導体素子の製造方法の第１の実施形態を図２（ａ）〜（ｈ）を参照しながら説明する。
　まず、図２（ａ）に示すように、回路素子の形成されたウエハ５上の図示しないアルミ電極上にバンプ電極２を金めっき等で形成する。バンプ電極２の大きさは１辺が約５０〜１００μｍ、高さ約１５μｍとする。
　次に、図２（ｂ）に示すように、ウエハ５の裏面をスクライブシート７を用いてスクライブリング８に張り付け、ダイヤモンドブレード９等で図２（ｃ）に示すように個片に分割する。ここで、ダイヤモンドブレード９の幅は、およそ６０μｍ程度のものを用いる。 Next, a first embodiment of such a semiconductor device manufacturing method will be described with reference to FIGS.
First, as shown in FIG. 2A, a bump electrode 2 is formed by gold plating or the like on an aluminum electrode (not shown) on a wafer 5 on which circuit elements are formed. The size of the bump electrode 2 is about 50 to 100 μm on one side and about 15 μm in height.
Next, as shown in FIG. 2B, the back surface of the wafer 5 is attached to a scribe ring 8 using a scribe sheet 7, and is divided into individual pieces as shown in FIG. Here, the diamond blade 9 has a width of about 60 μm.

　次に、図２（ｄ）に示すように、スクライブシート７に支持されている個片に分割済のウエハ５をスクライブリング８、スクライブシート７と共にモールド金型１０に入れる。上下の金型で挟んだ際に上金型を１バンプ当たり５０ｇｆ程度の圧力で押さえ、金型温度は約１８０℃でプレスすることにより、金バンプ２の表面高さを揃える。その後、ゲート１１より樹脂１２を注入する。図２（ｅ）は図２（ｄ）において樹脂を注入後、金型１０をはずした状態を示している。この図に示されるように、バンプ電極２の上面が露出した状態で樹脂１２が形成されている。 Next, as shown in FIG. 2 (d), the wafer 5 that has been divided into individual pieces supported by the scribe sheet 7 is placed in the mold 10 together with the scribe ring 8 and the scribe sheet 7. When the upper mold is sandwiched between upper and lower molds, the upper mold is pressed with a pressure of about 50 gf per bump, and the mold temperature is pressed at about 180 ° C., so that the surface height of the mold bumps 2 is made uniform. Thereafter, the resin 12 is injected from the gate 11. FIG. 2 (e) shows a state in which the mold 10 is removed after the resin is injected in FIG. 2 (d). As shown in this figure, the resin 12 is formed with the upper surface of the bump electrode 2 exposed.

　その後、図２（ｆ）に示すように、バンプ電極２の上面にハンダボール４を搭載する。ハンダボール４の搭載方法としては、バンプ電極２上にフラックスを塗布し、その上にハンダボール４を載せ、その後２００〜２５０℃の熱を加え、ハンダボール４とバンプ電極を接合させることにより搭載することができる。ハンダボール４を搭載後、図２（ｇ）に示されるように、分割された隙間に樹脂が注入されているウエハをダイヤモンドブレード１４等で個々のチップに再度分割することで、図２（ｈ）に示すように、ＬＳＩチップ１の側面も樹脂で覆われたチップサイズパッケージを得ることができる。ここで、ダイヤモンドブレード１４の幅はおよそ４０μｍ程度であり、ダイヤモンドブレード９の幅よりも細いものを用いているため、容易にＬＳＩチップ１の側面に樹脂を残した状態で個々のチップに分割することができる。 Thereafter, as shown in FIG. 2F, a solder ball 4 is mounted on the upper surface of the bump electrode 2. The solder ball 4 is mounted by applying flux on the bump electrode 2, placing the solder ball 4 thereon, and then applying heat at 200 to 250 ° C. to bond the solder ball 4 and the bump electrode. can do. After the solder balls 4 are mounted, as shown in FIG. 2G, the wafer in which the resin is injected into the divided gaps is divided again into individual chips with a diamond blade 14 or the like, thereby obtaining the structure shown in FIG. ), A chip size package in which the side surface of the LSI chip 1 is also covered with a resin can be obtained. Here, the diamond blade 14 has a width of about 40 μm and is smaller than the width of the diamond blade 9, so that it is easily divided into individual chips while leaving the resin on the side surfaces of the LSI chip 1. be able to.

　また、図２（ｂ）おいて、ダイヤモンドブレード９の幅を、図２（ｇ）に示すダイヤモンドブレード１４の幅の２倍程度とすれば、図２（ｈ）におけるＬＳＩチップ１側面の樹脂の厚さを十分確保することができ、側面の樹脂のはがれに対してより高い強度を得ることができる。
　次に本願発明の製造方法の第２の実施形態について図３（ａ）〜（ｈ）を用いて説明する。図２と対応する箇所には同一の符号を付し、その詳細な説明を省略する。
　第２の実施形態では、まず、回路素子の形成されたウエハ５上の図示しないアルミ電極上にバンプ電極２を金めっき等で形成する。 In FIG. 2B, if the width of the diamond blade 9 is about twice the width of the diamond blade 14 shown in FIG. 2G, the resin on the side surface of the LSI chip 1 in FIG. Thickness can be sufficiently secured, and higher strength can be obtained against the peeling of the resin on the side surface.
Next, a second embodiment of the manufacturing method of the present invention will be described with reference to FIGS. Parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
In the second embodiment, first, bump electrodes 2 are formed by gold plating or the like on aluminum electrodes (not shown) on the wafer 5 on which circuit elements are formed.

　次に、図３（ｂ）に示すようにダイヤモンドブレード１４を用いてウエハを個片に分割する。ここで用いるダイヤモンドブレード１４は、第１の実施形態の図２（ｇ）に示す幅の細いものを用いる。
　次に、図３（ｃ）に示すようにスクライブシート７を引き伸ばし、個片に分割されたウエハ間を広げる。ここで、個片に分割されたウエハ間の間隔は約１００μｍ程度とする。 Next, as shown in FIG. 3B, the wafer is divided into pieces using a diamond blade 14. The diamond blade 14 used here has a narrow width as shown in FIG. 2G of the first embodiment.
Next, as shown in FIG. 3C, the scribe sheet 7 is stretched to widen the space between the wafers divided into individual pieces. Here, the interval between the wafers divided into individual pieces is about 100 μm.

　次に、第１の実施例と同様に金型１０を用いてＬＳＩチップ個片間の隙間も含めたＬＳＩチップ表面全体を樹脂にて封止する。
　次に、図３（ｆ）に示すようにバンプ電極２上にハンダボール４を搭載する。
　ハンダボール４搭載後、図３（ｇ）に示すように、ダイヤモンドブレード１４を用いて樹脂の充填されたＬＳＩチップ間を再度分割する。それにより、図３（ｈ）に示すようにＬＳＩチップ１側面も樹脂で覆われたチップサイズパッケージを得ることができる。 Next, as in the first embodiment, the entire LSI chip surface including the gap between the LSI chip pieces is sealed with resin using the mold 10.
Next, solder balls 4 are mounted on the bump electrodes 2 as shown in FIG.
After mounting the solder balls 4, as shown in FIG. 3G, the LSI chips filled with the resin are divided again by using a diamond blade. Thereby, as shown in FIG. 3H, a chip size package in which the side surface of the LSI chip 1 is also covered with the resin can be obtained.

　この第２の実施形態で示される製造方法によれば、ウエハを最初に分割する際のダイヤモンドブレードの幅を薄くできるのでダイヤモンドブレードで削る部分が少なくなり、ウエハ面内のチップ取り数が増加する。また、２回の分割工程において同一のダイヤモンドブレードを用いることができるため、製造装置を簡略化することができる。 According to the manufacturing method shown in the second embodiment, since the width of the diamond blade when the wafer is first divided can be reduced, the portion to be cut with the diamond blade is reduced, and the number of chips on the wafer surface is increased. . In addition, since the same diamond blade can be used in the two dividing steps, the manufacturing apparatus can be simplified.

　また、上述の製造方法において、図４に示すように、半導体ウエハ５の図示しない電極パッド上にワイヤボンディング方式でスタッドバンプ電極２'を形成してもよい。この場合、ウエハの品種に応じてホトリソマスクを作成する必要がなく、部材コストを削減できる。また、一般に、ホトリソ・メッキ方式でバンプを形成する場合には多額な設備投資が必要となるが、スタッドバンプ方式の場合はワイヤボンダーがあればことが足りてしまうので、従来工程で用いている設備を用いることができ、設備コストも低減できる。 Further, in the above manufacturing method, as shown in FIG. 4, a stud bump electrode 2 ′ may be formed on an electrode pad (not shown) of the semiconductor wafer 5 by a wire bonding method. In this case, it is not necessary to create a photolithographic mask according to the type of wafer, and the member cost can be reduced. In general, a large amount of capital investment is required when bumps are formed by the photolithography / plating method, but in the case of the stud bump method, a wire bonder is sufficient, so it is used in the conventional process. Equipment can be used and equipment costs can be reduced.

　また、図５に示すように、半導体ウエハ５上のバンプ電極２あるいはスタッドバンプ電極２'の表面の高さをツール１６を用いて揃えてもよい。この場合、半導体ウエハ５をステージ１５の上に載せ、ツール１０を温度１００℃、荷重約５０ｇｆバンプ、程度の条件として、バンプ電極を押さえる。このように、ツール１６を用いてバンプ電極の表面高さを揃える場合、処理するウエハの厚さにばらつきがあったとしても、バンプ電極を適切な高さに揃えることができる。 Further, as shown in FIG. 5, the surface height of the bump electrode 2 or the stud bump electrode 2 ′ on the semiconductor wafer 5 may be aligned using a tool 16. In this case, the semiconductor wafer 5 is placed on the stage 15, and the bump electrode is pressed under the condition that the tool 10 has a temperature of 100 ° C. and a load of about 50 gf. As described above, when the surface height of the bump electrode is aligned using the tool 16, the bump electrode can be aligned at an appropriate height even if the thickness of the wafer to be processed varies.

　また、個片に分割されたＬＳＩチップの裏面にも樹脂を形成してもよい。樹脂は、たとえば、ＬＳＩチップを再度分割後、裏面に樹脂を塗布する。あるいは回路素子の形成されたウエハ５上にバンプ電極２を形成した後、ウエハ裏面にスピンコート法で樹脂を塗布することにより形成する。この場合、チップ裏面の欠けも防ぐことができ、さらに信頼性の高いチップサイズパッケージを提供することが可能となる。 Also, a resin may be formed on the back surface of the LSI chip divided into individual pieces. For example, after dividing the LSI chip again, the resin is applied to the back surface. Alternatively, the bump electrode 2 is formed on the wafer 5 on which circuit elements are formed, and then the resin is applied to the back surface of the wafer by spin coating. In this case, chipping of the chip back surface can be prevented, and a more reliable chip size package can be provided.

　次に、図６（ａ）〜（ｆ）を用いて本発明の製造方法の第３の実施形態を説明する。図２および図３と対応する箇所には同一の符号を付し、その詳細な説明を省略する。
　図６（ａ）に示すように、回路素子の形成されたウエハ５上の図示しないアルミ電極上にバンプ電極２を金めっき等で形成する。バンプ電極２の大きさは１辺が約５０〜１００μｍ、高さ約１５μｍとする。 Next, a third embodiment of the manufacturing method of the present invention will be described with reference to FIGS. Parts corresponding to those in FIGS. 2 and 3 are denoted by the same reference numerals, and detailed description thereof is omitted.
As shown in FIG. 6A, a bump electrode 2 is formed by gold plating or the like on an aluminum electrode (not shown) on a wafer 5 on which circuit elements are formed. The size of the bump electrode 2 is about 50 to 100 μm on one side and about 15 μm in height.

　次に、図６（ｂ）に示すように、このバンプ電極が形成されたウエハ７を金型に入れる。上下の金型で挟んだ際に上金型を１バンプ当たり５０ｇｆ程度の圧力で押さえ、金型温度は約１８０℃でプレスすることにより、金バンプ２の表面高さを揃える。ここで、上金型１７の表面にはウエハを個片チップに分割する際の対応する位置に突起部１８が設けられている。その後ゲート１１より、樹脂を注入する。
　このようにして注入された樹脂は、図６（ｃ）に示すように、封止樹脂１２の上金型１７の突起部１８に対応する位置に凹部１９が形成されている。
　次に、図６（ｄ）に示すように、バンプ電極２の上面にハンダボール４を搭載する。 Next, as shown in FIG. 6B, the wafer 7 on which the bump electrodes are formed is placed in a mold. When the upper mold is sandwiched between upper and lower molds, the upper mold is pressed with a pressure of about 50 gf per bump, and the mold temperature is pressed at about 180 ° C., so that the surface height of the mold bumps 2 is made uniform. Here, a protrusion 18 is provided on the surface of the upper mold 17 at a position corresponding to when the wafer is divided into individual chips. Thereafter, resin is injected from the gate 11.
As shown in FIG. 6C, the resin injected in this way has a recess 19 formed at a position corresponding to the protrusion 18 of the upper mold 17 of the sealing resin 12.
Next, as shown in FIG. 6D, the solder ball 4 is mounted on the upper surface of the bump electrode 2.

　次に、図６（ｅ）に示すように、樹脂１２表面に形成されている凹部１９を目印としてダイヤモンドブレード１４によりウエハ５を個々のチップに分割し、図６（ｆ）に示すようなチップサイズパッケージが得られる。
　この第３の実施形態によれば、一般的には不透明である樹脂１２の分割する位置に凹部を設けているため、個々のチップに切断する際に目印となり、作業効率が向上する。さらに、凹部に沿って切断するため、切断する樹脂部の厚さが薄くなり、ダイヤモンドブレード１４の消耗量も低減できる。 Next, as shown in FIG. 6E, the wafer 5 is divided into individual chips by the diamond blade 14 using the concave portions 19 formed on the surface of the resin 12 as marks, and the chips as shown in FIG. A size package is obtained.
According to the third embodiment, since the concave portion is provided at the position where the resin 12 that is generally opaque is divided, it becomes a mark when cutting into individual chips, and the working efficiency is improved. Further, since the cutting is performed along the concave portion, the thickness of the resin portion to be cut is reduced, and the consumption of the diamond blade 14 can be reduced.

　また、上述の図６（ｂ）の工程で、バンプ電極２の表面から所定間隔の逃げ部を有し、ウエハ５表面近傍まで達する凸部を有する金型を用いて樹脂を注入してもよい。その場合、ウエハ５上に形成された封止樹脂からはバンプ電極が露出していないので、研磨等により露出させる。このようにすると、金型のクリアランスを余裕を持って設計することが可能となり、金型製造コストを低減することができるとともに、処理する個々のウエハの厚さおよびバンプ電極の高さに多少のばらつきがあってもそれを吸収することができる。 Further, in the step of FIG. 6B described above, the resin may be injected by using a mold having a relief portion having a predetermined interval from the surface of the bump electrode 2 and having a convex portion reaching the surface of the wafer 5. . In that case, since the bump electrode is not exposed from the sealing resin formed on the wafer 5, it is exposed by polishing or the like. In this way, it is possible to design the mold clearance with a margin, and it is possible to reduce the mold manufacturing cost, and to reduce the thickness of individual wafers to be processed and the height of the bump electrodes. Even if there is variation, it can be absorbed.

　また、上述の各実施例においては、バンプ電極の材質として金を用いているが、ハンダを用いてもよい。ハンダを用いた場合は、その後形成するハンダボールとの相性が良くなり、密着強度が向上する。また、ハンダは安価であるので材料コストを低減できる。 In each of the above embodiments, gold is used as the material of the bump electrode, but solder may be used. When solder is used, compatibility with a solder ball to be formed thereafter is improved and adhesion strength is improved. Further, since the solder is inexpensive, the material cost can be reduced.

本発明の第１の実施形態を示すチップの断面図である。It is sectional drawing of the chip | tip which shows the 1st Embodiment of this invention. 本発明の製造方法の第１の実施形態の製造工程図である。It is a manufacturing-process figure of 1st Embodiment of the manufacturing method of this invention. 本発明の製造方法の第２の実施形態の製造工程図である。It is a manufacturing-process figure of 2nd Embodiment of the manufacturing method of this invention. 本発明の製造方法の第２の実施形態の変形例を示す図である。It is a figure which shows the modification of 2nd Embodiment of the manufacturing method of this invention. 本発明の製造方法の第２の実施形態の他の変形例を示す図である。It is a figure which shows the other modification of 2nd Embodiment of the manufacturing method of this invention. 本発明の製造方法の第３の実施形態を示す図である。It is a figure which shows 3rd Embodiment of the manufacturing method of this invention.

符号の説明Explanation of symbols

　１ ＬＳＩチップ
　２ バンプ電極
　２'スタッドバンプ電極
　３ エポキシ樹脂
　４ ハンダボール
　５ ウエハ
　７ スクライブシート
　８ スクライブリング
　９ ダイヤモンドブレード
　１０ 金型
　１１ ゲート
　１２ 樹脂
　１４ ダイヤモンドブレード
　１５ ステージ
　１６ ツール
　１７ 上金型
　１８ 突起部
　１９ 凹部 DESCRIPTION OF SYMBOLS 1 LSI chip 2 Bump electrode 2 'Stud bump electrode 3 Epoxy resin 4 Solder ball 5 Wafer 7 Scribe sheet 8 Scribe ring 9 Diamond blade 10 Mold 11 Gate 12 Resin 14 Diamond blade 15 Stage 16 Tool 17 Upper mold 18 Protrusion 19 Recess

Claims (6)

　電極パッドが形成された表面と、ダイシングによって形成された側面とを有する半導体チップと、
　前記半導体チップの表面及び側面を覆い、該側面を覆う厚さは少なくとも２０μｍである封止樹脂と、
　一部は前記電極パッドと接続し、他の一部は前記封止樹脂から露出するバンプ電極とにより構成されることを特徴とする半導体装置。 A semiconductor chip having a surface on which electrode pads are formed and side surfaces formed by dicing;
A sealing resin that covers the surface and side surfaces of the semiconductor chip, and has a thickness of at least 20 μm covering the side surfaces;
A part is connected to the electrode pad, and the other part is constituted by a bump electrode exposed from the sealing resin. 　前記半導体チップは、ウエハを少なくとも６０μｍの幅を有するダイシングブレードによって切断することにより個片化されたこと特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor chip is separated into pieces by cutting the wafer with a dicing blade having a width of at least 60 μm. 　前記半導体チップの側面に形成された封止樹脂は、最初は少なくとも１００μｍの厚みを有し、ダイシングによって厚みを調整されることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the sealing resin formed on the side surface of the semiconductor chip has a thickness of at least 100 μm at first, and the thickness is adjusted by dicing. 　前記半導体チップの側面に形成された封止樹脂は、少なくとも４０μｍの幅を有するダイシングブレードによって厚みを調整されることを特徴とする請求項３記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the thickness of the sealing resin formed on the side surface of the semiconductor chip is adjusted by a dicing blade having a width of at least 40 μm. 　前記バンプ電極は、前記電極パッド上に、金めっきによって形成されることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the bump electrode is formed on the electrode pad by gold plating. 　前記バンプ電極は、１辺が少なくとも５０μｍで高さが少なくとも１５μｍであることを特徴とする請求項５記載の半導体装置。 6. The semiconductor device according to claim 5, wherein the bump electrode has a side of at least 50 μm and a height of at least 15 μm.
JP2003374084A 2003-11-04 2003-11-04 Semiconductor device Pending JP2004111987A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125633A (en) * 1988-11-04 1990-05-14 Nec Corp Integrated circuit
JPH0621456A (en) * 1992-06-30 1994-01-28 Hitachi Ltd Semiconductor device and manufacture thereof
JPH11121507A (en) * 1997-10-08 1999-04-30 Oki Electric Ind Co Ltd Semiconductor device and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125633A (en) * 1988-11-04 1990-05-14 Nec Corp Integrated circuit
JPH0621456A (en) * 1992-06-30 1994-01-28 Hitachi Ltd Semiconductor device and manufacture thereof
JPH11121507A (en) * 1997-10-08 1999-04-30 Oki Electric Ind Co Ltd Semiconductor device and its manufacture

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