JP2004111046A - Information recording device and information recording method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information recording device etc., capable of recording correct information even in an information recording medium in which parts of synchronizing signals are recorded at intervals different from other parts of the synchronizing signals. <P>SOLUTION: In the information recording device for recording the recorded information to a DVD-R 1 in which parts of pre-information are recorded at the intervals different from other parts of the pre-information, a prepit signal reproduced signal SPP is generated by detecting the pre-information, a reference signal pulse SREF is generated on the basis of the signal SPP, the recorded information is temporarily stored and the stored recorded information is read out synchronously with the pulse SPEF, and the read-out recorded information is recorded in the DVD-R1. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a rotation control device that controls a rotation state of a motor such as a spindle motor for rotating an optical disk or the like.

2. Description of the Related Art Conventionally, in rotation control of a motor such as a spindle motor, a sync signal (synchronization signal) recorded at a constant interval together with information data corresponding to information data to be reproduced on an optical disk or the like is detected. The detected cycle and a predetermined fixed cycle set in advance (the cycle is set as a cycle in which recorded information is reproduced in the best condition when an optical disc or the like is rotated by the cycle. Are compared, and the rotation speed of the motor is controlled so that the difference becomes zero, in other words, the period of the detected synchronization signal matches the period of the reference signal. .

However, in the above-described conventional rotation control device, it is assumed that the synchronization signal is recorded at a fixed interval (period), and the synchronization signal is, for example, a part of the other synchronization signals. In the case of an optical disk or the like recorded at an interval different from that of a conventional rotation control device and phase synchronization circuit, an accurate rotation state (CLV (Constant Linear Velocity, constant linear velocity) or CAV (Constant Angular Velocity, It is impossible to maintain the constant rotational angular velocity)).

That is, when the conventional rotation control device is applied to an optical disc or the like in which some of the synchronization signals are recorded at a different interval from the other synchronization signals, the interval between the synchronization signals having an interval different from that of the other synchronization signals is obtained. Is also controlled to match the period of the reference signal (corresponding to the interval of the other synchronization signal), so that a synchronization signal whose interval is different from that of the other synchronization signal is detected. In such a portion, the number of rotations is shifted from the originally obtained number of rotations (increases or decreases) by an amount corresponding to the difference between the synchronization signal intervals. That is, there is a problem that the rotation control at the cycle of the reference signal causes rotation unevenness.

Therefore, the present invention has been made in view of the above problems, and the problem is that even in an information recording medium in which a part of a synchronization signal is recorded at a different interval from other synchronization signals. An object of the present invention is to provide an information recording device and an information recording method capable of recording accurate information.

In order to solve the above problem, an invention according to claim 1 is an information recording apparatus that records recording information on an information recording medium in which a part of pre-information is recorded at a different interval from other pre-information. A pre-information detecting means for detecting the pre-information and generating a pre-information signal; a clock generating means for generating a clock signal based on the pre-information signal; and temporarily storing the recording information. A memory for reading stored recording information in synchronization with the clock signal; and a recording unit for recording the read recording information on the recording medium.

In order to solve the above problem, an invention according to claim 11 is an information recording method for recording recording information on an information recording medium in which part of pre-information is recorded at intervals different from other pre-information. A pre-information detecting step of detecting the pre-information and generating a pre-information signal, a clock generating step of generating a clock signal based on the pre-information signal, and temporarily storing the recording information by using a memory. The method includes a storing and reading step of storing and reading the stored recording information in synchronization with the clock signal, and a recording step of recording the read recording information on the recording medium.

Next, a preferred embodiment of the present invention will be described with reference to the drawings.

The embodiment described below has been actively developed in recent years. The recording density has been dramatically improved as compared with a conventional CD (Compact Disk) or the like, and one movie or the like can be stored on one optical disc. 1 shows an embodiment in which the present invention is applied to a WO (Write Once) type DVD-R that is recordable among high-density optical disks (hereinafter, referred to as DVDs) capable of recording a DVD.

(1) Configuration of DVD-R Before describing a specific embodiment corresponding to the present invention, an outline of a DVD-R to which the present embodiment is applied will be described with reference to FIGS. explain.

In general, in an optical disk or the like that can be written once, pre-information for position search at the time of writing recording information is recorded on the optical disk or the like in advance in a pre-formatting stage at the time of manufacturing the optical disk or the like. Here, the pre-information includes address information indicating the write position of the recording information on the optical disk, and the like.

In addition, a write-once optical disc usually includes a groove track for recording information and a land track for guiding an irradiation position of a light beam for recording information to the groove track on its information recording surface. In the DVD-R, pre-information is recorded by forming pre-pits on the land track by a cutting device or the like.

Next, a specific configuration example of the DVD-R will be described with reference to FIG.

As shown in FIG. 1, the DVD-R 1 is a dye-type DVD-R having a dye film 5 and capable of writing information only once, and has a groove track 2 and a reproduction light or a recording light on the groove track 2. A land track 3 for guiding the light beam B is formed by a cutting device or the like. Further, a protective film 7 for protecting them and a gold vapor-deposited film 6 for reflecting the light beam B when reproducing recorded information are provided. Then, pre-pits 4 corresponding to the pre-information are formed on the land tracks 3 by a cutting device or the like. The pre-pits 4 are formed before shipping the DVD-R1.

When recording information data (information data such as image information to be originally recorded other than the pre-information) is recorded on the DVD-R1, the pre-information is obtained in advance by detecting the pre-pit 4 in a predetermined information recording device. Based on the information, the number of rotations of the DVD-R1 (in the case of the DVD-R1, so-called CLV rotation) and the like are set, and address information corresponding to the record information is obtained. Based on the information, the recording information is recorded at the corresponding recording position on the DVD-R1.

Here, at the time of recording the recording information, the recording information is formed by irradiating the light beam B such that the center thereof coincides with the center of the groove track 2 to form recording information pits corresponding to the recording information on the groove track 2. Form. At this time, the size of the light spot SP is set so that a part thereof is irradiated not only on the groove track 2 but also on the land track 3 as shown in FIG. Then, pre-information is detected from the pre-pits 4 prior to recording of recording information by a tangential push-pull method described later using a part of the reflected light of the light spot SP applied to the land track 3.

Next, the recording format of the pre-information on the DVD-R1 will be described with reference to FIG.

(2) As shown in FIG. 2, pre-information on the DVD-R1 is recorded for each sync frame. Further, one recording sector is formed by 26 sync frames. Then, one ECC (Error Correcting Code) block is formed by the 16 recording sectors. Further, one sync frame has a length of 1488 times (1488T) a unit length (hereinafter, simply referred to as “T”) corresponding to a bit interval defined by a recording format when recording information is recorded. are doing. In the present embodiment, a sync frame cycle having a length of 1488T is hereinafter referred to as a unit cycle. In FIG. 2, a plurality of recording sectors are recorded on one land track 3 continuously.

Here, the pre-information is recorded at a position of 2T from the start position of each sync frame in the first 14T length portion of each sync frame. At this time, in one recording sector, Pre-information is recorded only in even-numbered sync frames (hereinafter, referred to as EVEN frames) or only in odd-numbered sync frames (hereinafter, referred to as ODD frames). Note that the pre-information to be recorded is classified into a synchronization pre-signal and a data pre-information corresponding to a synchronization signal in the pre-information. Among these, the synchronization pre-signal is recorded with the pre-information at the head of each recording sector. The synchronization pre-signal (EVEN synchronization pre-signal) recorded at the position of the sync frame to be recorded and recorded in the EVEN frame and the synchronization pre-signal (ODD synchronization pre-signal) recorded in the ODD frame are as shown in FIG. By recording the information in a different pattern and reading it when recording information is recorded, it can be determined whether the pre-information is recorded in the EVEN frame or the ODD frame.

As described above, the reason why the pre-information is dispersedly recorded in the first 14T portion of the sync frame in the EVEN frame or the ODD frame is that when the DVD-R1 is manufactured, the pre-pits 4 are concentrated in one place. When the material forming the dye film 5 is applied by spin coating or the like, the material flows into the pre-pits 4 formed in advance at that portion, so that the material is designed on the groove track 2. When the dye film 5 having a predetermined thickness is not formed at the time (if the dye film 5 is not formed to a predetermined thickness, adverse effects such as a change in a DC component when reproducing recorded information occur) That is.)

On the other hand, the data pre-information is dispersedly recorded in a plurality of sync frames, and in one sync frame, as shown in FIG. 2, only the data pre-information corresponding to “1” is the start position of each sync frame. Is recorded at a position of 2T from the length of 2T. Therefore, data pre-information corresponding to “0” is not formed as a pre-pit.

FIG. 2 shows an example in which pre-information is recorded in an EVEN frame in recording sector 0 and pre-information is recorded in an ODD frame in recording sector 2.

Furthermore, the recording information recorded by the information recording device based on the detected pre-information is also recorded in the same format as the recording format shown in FIG. At this time, in the recording information, a synchronization signal is recorded with a length of 14T at the beginning of every sync frame, and data such as image information to be recorded at a position other than the beginning 14T in one sync frame is recorded. In the pre-information, no information is recorded in a position other than the first 14T in one sync frame.

Here, as described above, in the DVD-R1, the pre-information is recorded only in the EVEN frame or only in the ODD frame, and among them, the synchronization pre-signal is recorded in the position of the head EVEN frame or the position of the ODD frame of each recording sector. Since these are detected when recording the recording information, when the recording position of the pre-information changes from the EVEN frame to the ODD frame or when the ODD frame changes to the EVEN frame, the EVEN frame is The period of the detected synchronization pre-signal changes as compared to the case where the synchronization pre-signal is continuous or the case where the ODD frame is continuous.

That is, as shown in FIG. 3, when the EVEN frames are continuous (hereinafter, referred to as pattern 1) or when the ODD frames are continuous (hereinafter, referred to as pattern 4), the synchronization pre-signal is exactly one recording sector. However, if the EVEN frame changes to the ODD frame (hereinafter, referred to as pattern 2), the interval of the synchronization pre-signal at the time of the change is the interval of one recording sector. In the case of changing from an ODD frame to an EVEN frame (hereinafter referred to as pattern 3), the interval of the synchronization pre-signal at the time of the change is longer than the interval of one recording sector. Is also shortened by one sync frame. Even in the case of pattern 2 or pattern 3, after each change, the period of the synchronization pre-signal returns to the length of one recording sector.

As described above, according to the present invention, it is possible to maintain an accurate CLV rotation even in a DVD-R1 in which some synchronization pre-signals are recorded at different intervals from other synchronization pre-signals. You can do it.

(2) Embodiment Next, an embodiment corresponding to the present invention will be described with reference to FIGS.

First, the overall configuration of the rotation control device according to the present embodiment will be described with reference to FIG. FIG. 4 shows only the part related to the rotation control device of the present embodiment in the configuration of the information recording device for recording the recording information on the DVD-R1, and the encoding of the recording information, The other components of the information recording apparatus, such as the focus servo and tracking servo for the beam B, have the same configuration as that of the related art, so that illustration and detailed description are omitted.

As shown in FIG. 4, the rotation control device SS1 of the present embodiment includes a laser diode (not shown), an objective lens, a beam splitter, a photodetector, and the like (not shown), and pre-information is recorded by forming pre-pits 4. A pickup 10 for irradiating the DVD-R1 with a light beam B as recording light, receiving a reflected light from the prepit 4 and outputting a detection signal SP for detecting pre-information by a tangential push-pull method; A pre-pit signal reproduction circuit 11 for generating a reproduction signal SPP as pre-information corresponding to the pre-pit 4 from the detection signal SP, and a synchronization pre-signal separated from the reproduction signal SPP and detected. Synchronous pre-signal detector 12 that outputs a corresponding timing signal ST, corresponding to the bit interval of recorded information A reference signal generator 13 for generating a periodic signal (reference signal) having a unit length T and a reference signal output from the reference signal generator 13 generates a unit periodic signal corresponding to a sync frame period (1488T). Similarly, the phase comparison circuit 14 serving as first phase comparison means for comparing the phase of the unit period signal with the timing signal ST output from the synchronization pre-signal detector 12 and outputting the phase difference signal SPD1 has A phase comparison circuit 15 as second phase comparison means for comparing the phase of the reproduction signal SPP output from the prepit signal reproduction circuit 11 and outputting a phase difference signal SPD2, and rotating the output signal SPD1 from the phase comparison circuit 14 An output signal SPD2 from the phase comparison circuit 15 as well as an amplitude / phase equalization circuit 16 for defining the required gain and phase characteristics of the control system. An amplitude / phase equalizing circuit 17 for defining required gain and phase characteristics, and an addition for adding the output signals SPD11 and SPD21 from the amplitude / phase equalizing circuits 16 and 17 to generate a rotation control signal SC. The circuit 18 includes a circuit 18 and a driver circuit 19 that converts the rotation control signal SC output from the addition circuit 18 into a current signal and applies the current signal to the motor 20.

Next, the overall operation will be described.

The pre-information detected and reproduced from the DVD-R 1 by the pickup 10 and the pre-pit signal reproduction circuit 11 is input to the synchronization pre-signal detector 12 and the phase comparison circuit 15 as a reproduction signal SPP. The signal is detected, and a timing signal ST corresponding to the synchronization pre-signal is output. Then, the phase comparison circuit 15 compares the phase of a later-described reference signal with the input reproduction signal SPP, and outputs a precision error signal SPD2 for rotation control to the addition circuit 18 via the amplitude-phase equalization circuit 17. Is entered.

On the other hand, the timing signal ST output from the synchronization pre-signal detector 12 is input to a phase comparison circuit 14, where the phase is compared with a reference signal, which will be described later, to obtain an amplitude phase signal as a coarse error signal SPD1 for rotation control. The signal is input to the addition circuit 18 via the equalization circuit 16.

The addition circuit 18 adds the coarse error signal SPD1 and the fine error signal SPD2 to generate a rotation control signal SC, and the rotation control signal SC is applied to the spindle motor 20 via the driver circuit 19.

Next, detection of pre-information by the tangential push-pull method will be described with reference to FIGS. 5 and 6, together with detailed configurations of the pickup 10 and the pre-pit signal reproducing circuit 11.

The detection by the tangential push-pull method means the detection by the push-pull method in the rotation direction of the DVD-R1, and the detection from the light spot SP by the light beam B formed on the land track 3 of the DVD-R1. The reflected light is divided by a dividing line optically perpendicular to the moving direction of the pre-pits 4 (the direction of rotation of the disk) based on the difference signal between the partial detectors in the two partial detectors. This is a method for reproducing pre-information.

More specifically, as shown in FIG. 5, a light beam B serving as recording light (reproducing light for the pre-pit 4) generated by a laser diode or the like (not shown) is a deflection beam splitter. The light is reflected by 31, and is condensed on the groove track 2 and the land track 3 of the DVD-R1 (see FIG. 1) by the objective lens 30. Then, the reflected light of the light beam B modulated by the pre-pits 4 and whose polarization plane has been rotated by the reflection by the DVD-R1 is transmitted through the deflection beam splitter 31 by the rotation of the deflection plane, and in the rotation direction of the DVD-R1. The light receiving surface of the photodetector 32 divided into two partial detectors 32a and 32b by an optically vertical dividing line is irradiated and detected. The light-receiving outputs of the respective partial detectors 32B1 and 32B2 (the outputs of the respective partial detectors are denoted by reference numerals B1 and B2 in the following description) are subtracted by a subtractor 33 included in the pre-pit signal reproduction circuit 11, and the difference between them is obtained. The signals (B1-B2) are compared with reference voltages + V0 and -V0 input from reference voltage units 37 and 38 by subtracters 34 and 35, respectively, and outputs of the subtracters 34 and 35 are input to a flip-flop circuit 36, respectively. Is done. Then, the output of the flip-flop circuit 36 is output to the synchronization pre-signal detector 12 and the phase comparison circuit 15 as a reproduction signal (pre-pit information) SPP.

Next, the generation of the difference signal (tangential push-pull signal) (B1-B2) and the reproduction signal SPP by the photodetector 32 and the pre-pit signal reproduction circuit 11 will be described with reference to FIG.

In FIG. 6, when the reflected light from the pre-pit 4 having the shape shown in FIG. 6 (a) as a cross-sectional view in the rotation direction of the DVD-R1 is received by the photodetector 32, the received light output of the partial detectors 32A and 32B is Based on the positional shift, the partial detectors 32A and 32B output the RF (Radio Frequency) signals (B1 and B2) whose phases are shifted as shown in FIG. 6B. Then, a difference signal (tangential push-pull signal) (B1-B2) shown in FIG. 6B is generated by subtracting each RF signal by the subtracter 33. This difference signal is input to subtracters 34 and 35, respectively, and compared with reference voltages + V0 and -V0, respectively, and the flip-flop circuit 36 is operated using the respective comparison results, whereby the reproduction shown in FIG. A signal SPP is generated. As a result, the pre-information (including the synchronization pre-signal and the data pre-information) included in the reproduction signal SPP is output to the synchronization pre-signal detector 12 and the phase comparator 15.

Next, the phase comparison operation in the phase comparison circuit 14 and the phase comparison circuit 15 will be described with reference to FIGS.

First, the configuration of the phase comparison circuits 14 and 15 will be described with reference to FIG.

As shown in FIG. 7A, the phase comparison circuit 14 includes a counter 141 for counting a reference signal pulse SREF having a unit length T corresponding to a bit interval of recording information from the reference signal generator 13, and a reference signal Is divided by 744 to generate a clear pulse signal at intervals of a sync frame period (1488T), and the count value output from the counter 141 is used as a synchronous pre-signal detection signal ST by the synchronous pre-signal detector 12. And a latch circuit 143 that latches at the timing output from the latch circuit 143.

As shown in FIG. 7B, the phase comparison circuit 15 outputs a signal for determining the latch timing in the latch circuit 153 in a predetermined width in synchronization with the rising edge of the timing signal SPP output from the pre-pit signal reproduction circuit 11. This pulse signal is generated by an MMV (Mono Multi Vibrator) 154. The reason that the MMV 154 is interposed is that the synchronization pre-signal in the pre-pit reproduction signal SPP has two pulse signals in one sync frame as shown in FIG. If the SRAMP signal is latched by the next pulse signal following the existing first pulse signal, the timing of the phase comparison is shifted from the timing by another data pre-signal, and this timing shift is recognized as a disturbance, This has an effect on the rotation control. In order to prevent this, the pulse width of the pulse signal output from the MMV 154 (this MMV does not accept an input pulse signal that arrives while the MMV outputs the pulse signal) is set to 8T or more, and the synchronization preamble is set. The next pulse signal following the first pulse signal of the signal is masked. The other configuration except this configuration is the same as that of the phase comparison circuit 14, and the description thereof is omitted.

Next, the phase comparison operation performed in the above configuration will be described with reference to FIGS. 8 is a waveform diagram in each block of the phase comparison circuit 14 shown in FIG. 7A, and FIG. 9 is a waveform diagram in each block of the phase comparison circuit 15 shown in FIG. 7B. .

The counter 141 sequentially counts the input reference signal pulses SREF. On the other hand, the clear pulse generator 142 generates a pulse signal having a predetermined width in response to, for example, a falling edge of a frequency-divided signal (FIG. 8B) having a period of 1488T obtained by dividing the reference signal SREF by 744 (FIG. 8B). In FIG. 8D, this is input to the counter 141 as a clear pulse signal. The counter 141 resets the count value to zero at the timing when the clear pulse signal is input, and starts the counting operation again. Therefore, the count value output from the counter 141 is, as shown in FIG. The ramp signal is a monotone increasing function having a sync frame period (1488T) which is a unit period in the recording format of -R1. This ramp signal SRAMP is input to the latch circuit 143, and is latched at the rising timing of the synchronization pre-signal detection signal ST (FIG. 8C) supplied from the synchronization pre-signal detection circuit 12. That is, the amplitude level (count value of the counter 141) of the ramp signal at the rising timing of the detection signal ST is held as a sample value until the next detection signal arrives (FIG. 8 (f)). As shown in FIG. 2, the synchronization pre-signal is recorded from a position 2T from the start position of either the first or second sync frame of each recording sector regardless of the EVEN synchronization pre-signal and the ODD synchronization pre-signal. Therefore, the amplitude level of the ramp signal SRAMP in the sync frame cycle latched at the timing of detecting the synchronization pre-signal includes the phase difference information from the reference signal.

That is, when the detection timing of the synchronization pre-signal (the rotation phase of the DVD-R1) and the phase of the reference signal pulse SREF match, the ramp signal SRAMP generated from the reference signal pulse SREF always has a predetermined amplitude level. For example, the intermediate level value (the amplitude level at the point x in FIG. 8E) is held at the rising timing of the detection signal ST of the synchronization pre-signal.

When the detection timing of the synchronization pre-signal is ahead of the reference signal, a level value smaller than the intermediate level value (amplitude level at point x-1 in FIG. 8E) is held. When the pre-pit detection timing is later than the reference signal, a level value (amplitude level at point x + 1 in FIG. 8E) larger than the intermediate value level is held.

(4) The output signal SPD1 from the latch circuit 143 is output as a phase error signal.

In the phase comparison circuit 15, the timing signal input to the latch circuit 153 is a pulse signal SPPmmv generated via the MMV 154 based on the timing signal SPP (FIG. 9A) output from the pre-pit signal reproduction circuit 11. (FIG. 9C). The pre-pit signal is composed of a synchronization pre-signal and a data pre-signal. Since the data pre-signal is recorded from the position 2T from the start position of the sync frame similarly to the synchronization pre-signal, the pre-pit signal is latched at the detection timing of the pre-pit signal. The amplitude level of the ramp signal SRAMP (FIG. 9 (e)) in the sync frame cycle includes the phase difference information from the reference signal SREF, and is output as the phase error signal SPD2 (FIG. 9 (f)).

The minimum interval at which the pre-pit signal is detected is two sync frame intervals. Therefore, the phase difference signal extracted by the phase comparison circuit 15 (hereinafter, referred to as a fine phase difference signal) is extracted by the phase comparison circuit 14 at a phase interval of approximately one recording sector (hereinafter, referred to as a coarse phase difference signal). ) Has a finer phase difference component.

The coarse phase difference signal SPD1 output from the phase comparison circuit 14 generated as described above and the fine phase difference signal SPD2 output from the phase comparison circuit 15 are added by the addition circuit 18 to generate a rotation control signal SC. The rotation speed of the motor 20 is output to the spindle motor 2 so that the synchronous pre-signal detection timing and the pre-pit signal detection timing always latch the intermediate level value of the ramp signal.

In the above embodiment, an example was described in which a ramp signal was used as a monotonically increasing function having a unit period. However, as the monotonically increasing function, for example, a phase comparison with a pre-pit detection timing, such as a trapezoidal wave, is used. The same effect as the phase comparison circuit in the present embodiment can be expected even with a signal waveform that monotonically increases only in the range where it is necessary to perform, or a waveform signal that monotonically decreases in the left and right directions with respect to the ramp signal in the present embodiment. it can.

Further, in the above embodiment, the example in which the unit period is set to the sync frame period has been described. However, the unit period is shorter than the sync frame period, and the period interval in which the pre-pit exists (in this embodiment, 2 sync periods). It is also possible to set a cycle having a relationship of an integral multiple of the frame cycle) to a unit cycle.

By the way, according to the recording format of the DVD-R pre-information described above, the synchronization pre-signal changes from the EVEN frame to the ODD frame (pattern 2) as shown in FIG. In this case (pattern 3), the interval of the synchronization pre-signal at the time of the change becomes longer or shorter by one sync frame than the interval of one recording sector. As described above, even when a part of the synchronization pre-signal is recorded at a different interval from the other synchronization pre-signals, according to the phase comparison circuit of the present embodiment, the recording of the synchronization pre-signal is performed. The phase error signal can be accurately extracted without being affected by the change in the interval. That is, the ramp signal to be compared with the synchronization pre-signal is not a recording sector cycle but a signal having a repetition cycle of a sync frame as a unit block constituting the recording sector. Since the phase difference from the reference signal is detected by sampling / holding at the detection timing of the synchronization pre-signal, the recording interval of the synchronization pre-signal is set in sync frame units as in pattern 2 or pattern 3 in FIG. As long as it changes, it is possible to accurately extract the phase error signal.

On the other hand, the data pre-signal is recorded according to the pre-data, and as described above, the “0” data is not recorded as a pre-pit. Therefore, the output timing of the timing signal SPP output from the pre-pit signal reproducing circuit 11 varies depending on the pre-data to be recorded. For example, when the pre-data to be recorded is “1011001...”, The output intervals of the timing signal SPP are 4 sync frames, 2 sync frames, 6 sync frames,.

However, even in such a case, since the recording interval of the pre-pits varies in sync frame units, according to the phase comparison circuit 15 of the present embodiment for comparing the phase with the ramp signal of the sync frame period, an accurate It is possible to extract a phase difference signal.

As described above, according to the rotation control device SS1 of the present embodiment, rotation control is performed using, as a control signal, a signal obtained by sampling / holding the ramp signal of the sync frame cycle at the detection timing of the pre-information recorded on the information recording medium. Therefore, even if the period at which the pre-pit signal including the synchronization pre-signal and the data pre-signal is detected changes in sync frame units, the rotation state (CLV) of the DVD-R1 can be maintained without changing.

By the way, in the case of recording information data on an optical disk such as a DVD-R on which information data is writable, even if the rotation phase of the optical disk is controlled by the rotation control device as described in this embodiment, Since a fine fluctuation component (jitter) on the time axis due to the eccentricity of the optical disc remains, when recording information data on the optical disc, the timing of recording the information data is determined by the fluctuation component due to the jitter. You need to synchronize exactly. Therefore, a phase synchronizer suitable for an optical disk or the like in which a part of the synchronization pre-signal is recorded at a different interval from the other synchronization pre-signals, such as the DVD-R1, will be described below.

FIG. 10 shows an information recording apparatus capable of writing information data on a DVD-R1 which is rotationally driven by the above-mentioned rotation control apparatus.

First, the overall configuration will be described. In FIG. 10, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

The information recording apparatus shown in FIG. 10 has a RAM (Random Access Memory) 50 in which information data is stored in advance, and the recording information data read from the RAM 50 corresponds to the bit interval of the recording information data supplied from the reference signal generator 13. Is temporarily stored based on a write clock signal SREF which is a periodic signal (reference signal) having a unit length T, and is the same as a write clock signal SREF given from a phase locked loop (PLL (Phase Locked Loop) circuit) 52 described later. In order to generate a FIFO (First In First Out) memory 51 for reading in the order of accumulation based on the read clock signal SCKV1 which is a frequency, and a read clock signal SCKV1 synchronized in phase with a jitter component included in a pre-pit signal read from the DVD-R1. PLL circuit 52 and the residual error component of the PLL circuit 52 are absorbed. FF for and a (Feed Forward) circuit 53.

Next, a specific configuration of the PLL circuit 52 will be described.

The PLL circuit 52 includes a VCO (Voltage Controlled Oscillator) 521 that generates the above-described read clock signal, and a phase comparison circuit 522 that compares the phase of the read clock signal SCKV1 from the VCO 521 with the prepit signal output from the prepit signal reproduction circuit 11. And an amplitude / phase equalization circuit 523 for defining an output signal from the phase comparison circuit 522 to have required gain and phase characteristics in the PLL circuit 52.

The FF circuit 53 includes a VCO 531 whose oscillation frequency is controlled by a phase error signal which is not subjected to the band limitation by the amplitude / phase equalization circuit 523 output from the phase comparison circuit 522, and the recording information data output from the FIFO 51 to the VCO 521. And a FIFO 532 that temporarily stores the clock signal SCKV1 supplied from the VCO 5 and reads the stored data in the order of storage based on the clock signal SCKV2 supplied from the VCO 531.

Next, the overall operation based on the above configuration will be described.

When a periodic signal of one recording sector period obtained by dividing the reference signal output from the reference signal oscillator 13 by the frequency dividing circuit 131 at a predetermined dividing ratio is input to the RAM 50, the RAM 50 is designated by a CPU (not shown). The recorded information data recorded at the designated address is read, and the read recorded information data is converted into serial data by a parallel / serial converter (not shown) and output to the FIFO 51. The FIFO 51 writes the record information data based on the write clock signal SREF given from the reference signal generator 13. At the same time, the read information is read from the FIFO 51 in the order in which the record information data is written, based on the read clock signal SCKV1 supplied from the PLL circuit 52. At this time, since the clock signal SCKV1 output from the PLL circuit 52 includes a phase change synchronized with the low-frequency component of the jitter component accompanying the rotation control of the DVD-R1, the data sequence of the recording information data read from the FIFO 51 is , Which is phase-synchronized with the low-frequency component of the jitter component. The recording information data string read from the FIFO 51 is further input to the FF 53. The FF 53 is provided to synchronize the phase of a high-frequency jitter component that cannot be synchronized by the PLL circuit 52, and the recording information data phase-synchronized with the low-frequency variation of the jitter component output from the FIFO 51. The column is written into the FIFO 532 in synchronization with the clock signal sCKV1, and is read based on the clock signal sCKV2 which is an output signal from the VCO 531. The oscillation frequency of the output signal sCKV2 from the VCO 531 serving as the read clock signal of the FIFO 532 fluctuates based on the phase difference signal output from the phase comparison circuit 522 in the PLL circuit 52. This phase difference signal is a so-called residual error component from which an error component that can be phase-synchronized by the PLL circuit 52 has been removed. Therefore, the FF circuit 53 can synchronize the phase even with the jitter component whose phase is not synchronized in the FIFO 51.

As described above, with the two-stage configuration of the FIFO 51 and the FF circuit 53, it is possible to generate a record information data sequence that is phase-synchronized over the entire range of the jitter component generated due to the rotation control of the DVD-R1. Become. The recording information data string output from the FF circuit 53 is supplied to an APC (Auto Power Control) circuit (not shown) for controlling the irradiation power of the light beam B, and the irradiation power is controlled according to the data. At this time, the fluctuation on the time axis of the recording information data sequence is synchronized with the fluctuation on the time axis due to the rotation control of the DVD-R1 by the FIFO 51 and the FF circuit 53. Can be recorded as a pit train having a pit length of.

Note that if the operation band of the PLL circuit 52 is sufficiently wide, the FF circuit 53 may not be necessarily provided.

Next, the operation of the PLL circuit 52 will be described.

The PLL circuit 52 is provided to change the phase of the clock signal SCKV1 output from the VCO 521 in synchronization with the time-axis fluctuation of the pre-pit signal reproduced from the DVD-R1.

Generally, a PLL circuit includes a synchronization signal recorded on a recording medium at regular intervals and a frequency-divided signal generated by dividing a clock signal generated from a VCO so as to have the same cycle as the synchronization signal. Are compared and the oscillation period of the VCO is adjusted so that this phase difference becomes zero, thereby performing phase synchronization with respect to a fluctuation component due to jitter included in the reproduction signal (synchronization signal). However, when the synchronization signal is recorded at a different interval from some of the other synchronization signals, such as a synchronization pre-signal in DVD-R1, such a general signal is used. In the PLL circuit configuration, it is impossible to maintain a phase synchronization state for a predetermined frequency.

That is, when a general PLL circuit is applied to an optical disc or the like in which some of the synchronization signals are recorded at a different interval from the other synchronization signals, the interval of the synchronization signal having an interval different from that of the other synchronization signals is obtained. Is also compared with the phase of the frequency-divided signal generated by dividing the clock signal obtained from the VCO (corresponding to the interval of the other synchronization signal). In a portion where a synchronization signal different from the synchronization signal is detected, the phase difference increases by an amount corresponding to the difference between the synchronization signals, and the oscillation frequency of the VCO deviates from the original frequency (whether the frequency is increased or not). Or make it smaller). In other words, a portion where the synchronization signal interval is different is recognized as a change on the time axis due to some disturbance applied to the recording medium, and the oscillation frequency is changed to follow the change due to the disturbance. It is.

Therefore, in the PLL circuit 52 used in the present embodiment, as shown in FIG. 11, the phase comparator 522 employs the same configuration as the phase comparator 15 described in FIG.

That is, a counter 522a that counts a clock signal SCKV1 having a period component of a unit length T corresponding to a bit interval of recording information data generated by the VCO 521, a 744 frequency division of the clock signal SCKV1, and a sync frame period (1488T ) A clear pulse generator 522b that generates a clear pulse signal at intervals, and a count value output from the counter is latched by a timing signal output from the MMV 522d synchronized with the timing of the timing signal SPP output from the prepit signal reproducing circuit. And a latch circuit 522c.

Like the pre-pit signal formed on the DVD-R1 by the phase comparison circuit 522, even when the interval of some synchronization signals to be compared is formed differently from the intervals of other synchronization signals, The reason why the phases can be accurately compared is as described in the phase comparison circuits 14 and 15.

That is, based on the clock signal SCKV1 from the VCO, a ramp signal having a sync frame period (1488T), which is a unit period in the recording format of the DVD-R1, is sampled / held at the timing of detecting the pre-information recorded on the information recording medium. The oscillation period of the clock signal SCKV1 output from the VCO 521 is controlled using the resulting signal as a phase difference signal. Therefore, even if the period in which the pre-pit signal composed of the synchronization pre-signal and the data pre-signal is detected changes in sync frame units, the predetermined period is maintained. It is possible to generate the clock signal SCKV1 maintaining the phase synchronization state for the frequency of.

According to the above-described embodiment, at the timing when the pre-pits 4 are detected, the phase difference from the unit period which is an integral multiple of the period interval of the pre-pits 4 is compared, and this phase difference is canceled. Since the rotation of the spindle motor 20 is controlled, a predetermined rotation state can be accurately obtained even when the pre-pits 4 cannot be obtained at predetermined intervals.

Therefore, even in the case of a DVD-R1 in which the recording interval of some of the synchronization signals is changed from a predetermined interval, it is possible to perform accurate information recording and reproduction by maintaining an accurate rotation state. Can be.

Also, since the ramp signal SRAMP having a unit cycle is generated and the phase difference is detected based on the amplitude value of the ramp signal SRAMP at the timing of detecting the pre-pit 4, the phase difference can be detected by a simple process.

Further, a coarse phase difference signal SPD1 obtained by comparing a phase difference with a unit cycle, which is a cycle of an integral multiple of the cycle interval of the synchronous pit, at a synchronous pit detection timing detected at a relatively coarse interval, At the detection timing of the pre-pits 4 detected at relatively small intervals composed of the synchronization pre-signal and the data pre-signal, the phase difference is obtained by comparing the phase difference with the unit period which is one integral multiple of the period interval of the pre-pits 4. The rotation of the spindle motor 20 is controlled so as to cancel the phase difference based on the precise phase difference signal obtained and the added phase difference signal SC obtained by adding the coarse phase difference signal and the fine phase difference signal. Even if the rotation is not obtained at a predetermined cycle interval, it is possible to accurately obtain a predetermined rotation state, and in addition to a rotation control with a higher accuracy than the rotation control using only the synchronization pit. It is possible to perform.

Therefore, even in the case of a DVD-R1 in which the recording interval of some of the synchronizing signals is changed from the predetermined interval, accurate recording and reproduction of information can be performed by maintaining an accurate rotation state. it can.

FIG. 3 is a perspective view showing an example of a DVD-R in which prepits are formed on land tracks. FIG. 4 is a diagram illustrating a recording format of pre-information or recording information. FIG. 9 is a diagram illustrating a detection pattern of a synchronization pre-signal. It is a block diagram showing a schematic structure of a rotation control device of an embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of a pickup and a pre-pit signal reproduction circuit according to the embodiment. FIG. 3 is a diagram illustrating generation of a tangential push-pull signal. FIG. 3 is a block diagram illustrating a configuration of phase comparison circuits 14 and 15 according to the embodiment. FIG. 4 is a waveform chart in each block of the phase comparison circuit 14 of the embodiment. FIG. 4 is a waveform chart in each block of the phase comparison circuit 15 of the embodiment. It is a block diagram showing a schematic structure of an information recording device using a rotation control device of an embodiment. 11 is a block diagram illustrating a configuration of a phase comparison circuit 522 of the information recording device in FIG.

Explanation of reference numerals

1 DVD-R
Reference Signs List 2 groove track 3 land track 4 pre-pit 5 dye film 6 gold deposition film 7 protective layer 10 pickup 11 pre-pit signal reproduction circuit 12 synchronous pre-signal detector 13 reference signal generator 14, 15 phase comparison circuit 16, 17 amplitude / phase equalization circuit 18 Adder circuit 19 Driver circuit 20 Spindle motor SREF Reference signal pulse SPD1 Coarse phase error signal SPD2 Fine phase error signal SC Addition phase error signal ST Synchronous pre-signal detection signal SPP Pre-pit signal reproduction signal

Claims (20)

An information recording apparatus that records recording information on an information recording medium in which a part of pre-information is recorded at a different interval from other pre-information,
A pre-information detecting means for detecting the pre-information and generating a pre-information signal;
Clock generation means for generating a clock signal based on the pre-information signal,
A memory for temporarily storing the recording information and reading the stored recording information in synchronization with the clock signal;
Recording means for recording the read recording information on the recording medium,
An information recording device comprising: The pre-information is a period interval of m times (m is an integer) of a unit period or an interval deviated by k times (k is an integer and k <m) of the unit period from the period interval according to a recording position. 2. The information recording apparatus according to claim 1, wherein the information is recorded on the information recording medium. 3. The information recording apparatus according to claim 1, wherein the clock generation unit is a PLL circuit. The PLL circuit comprises:
A voltage-controlled oscillator that generates the clock signal;
A phase comparison circuit that compares the pre-information signal with the clock signal and generates a phase comparison output signal;
An equivalent circuit for adjusting the phase comparison output signal,
The information recording apparatus according to claim 3, comprising: Further comprising reference signal generating means for generating a reference signal,
5. The information recording apparatus according to claim 1, wherein the memory stores the recording information in synchronization with the reference signal. The information recording apparatus according to any one of claims 1 to 5, further comprising: a feedforward circuit that removes a residual phase error component in recording information read from the memory. A feedforward circuit that removes a residual phase error component in recorded information read from the memory,
The feedforward circuit is
A second voltage-controlled oscillator that generates a second clock signal according to the phase comparison output signal;
A second memory that writes the recording information read from the memory based on the clock signal and that reads the written recording information based on the second clock signal;
The information recording device according to claim 4, comprising: The information recording apparatus according to claim 4, wherein the reference signal is a periodic signal having a unit length corresponding to a bit length defined by a recording format of the recording information. The information recording apparatus according to claim 7, wherein the unit period is 1488 times the unit length. The information recording apparatus according to any one of claims 1 to 9, wherein the unit cycle is one sync frame. An information recording method for recording recording information on an information recording medium in which part of pre-information is recorded at a different interval from other pre-information,
A pre-information detecting step of detecting the pre-information and generating a pre-information signal;
A clock generation step of generating a clock signal based on the pre-information signal;
Using a memory, temporarily storing the recording information, and reading out the stored recording information in synchronization with the clock signal;
A recording step of recording the read recording information on the recording medium,
An information recording method comprising: According to the recording position, the pre-information is a period interval of m times (m is an integer) of a unit period or an interval deviated from the period interval by k times of the unit period (k is an integer and k <m). 12. The information recording method according to claim 11, wherein the information is recorded on the information recording medium. 13. The information recording method according to claim 11, wherein in the clock generating step, the clock signal is generated using a PLL circuit. The clock generation step includes:
A generation step of generating the clock signal using a voltage-controlled oscillator,
A phase comparison step of comparing the pre-information signal and the clock signal to generate a phase comparison output signal;
Adjusting the phase comparison output signal using an equivalent circuit,
14. The information recording method according to claim 13, comprising: A reference signal generating step of generating a reference signal;
15. The information recording method according to claim 11, wherein in the storing and reading step, the recording information is stored in synchronization with the reference signal. 16. The information recording method according to claim 11, further comprising a removing step of removing a residual phase error component in the recording information read in the storing / reading step using a feedforward circuit. . The method further includes a removing step of removing a residual phase error component in the recorded information read in the storing and reading step by using a feedforward circuit.
The removing step includes:
A second generation step of generating a second clock signal according to the phase comparison output signal using a second voltage controlled oscillator;
Using a second memory, writing the record information read from the memory based on the clock signal, and reading the written record information based on the second clock signal; ,
The information recording method according to claim 14, comprising: 15. The information recording method according to claim 14, wherein the reference signal is a periodic signal having a unit length corresponding to a bit length defined by a recording format of the recording information. 18. The information recording method according to claim 17, wherein the unit cycle is 1488 times the unit length. 20. The information recording method according to claim 11, wherein the unit cycle is one sync frame.

Images