JP3889739B2 - Information recording apparatus and information recording method - Google Patents

Description

  The present invention relates to a rotation control device for controlling the rotation state of a motor such as a spindle motor for rotating an optical disk or the like.

  Conventionally, in rotation control of a motor such as a spindle motor, a sync signal (synchronization signal) recorded at regular intervals along with the information data corresponding to the information data to be reproduced on an optical disk or the like is detected. Detected period and a predetermined constant period set in advance (this period is set as a period in which recorded information is reproduced in the best condition when an optical disc or the like is rotated by the period. The number of rotations of the motor is controlled so that the difference is zero, in other words, the period of the detected synchronization signal matches the period of the reference signal. .

  However, in the conventional rotation control device, it is assumed that the synchronization signal is recorded at a constant interval (period), and the synchronization signal is, for example, a part of the synchronization signal and other synchronization signals. In the case of an optical disk or the like that is recorded at a different interval, the conventional rotation control device and phase synchronization circuit have an accurate rotation state (CLV (Constant Linear Velocity, constant linear velocity)) or CAV (Constant Angular Velocity, It is impossible to maintain a constant rotation angular velocity)).

  That is, when a conventional rotation control device is applied to an optical disc or the like in which some synchronization signals are recorded at intervals different from those of other synchronization signals, the intervals of the synchronization signals differing from other synchronization signals. Is also controlled to match the period of the reference signal (corresponding to the interval of the other synchronization signal), so that a synchronization signal whose interval is different from other synchronization signals is detected. In this part, the rotation speed is deviated from the originally obtained rotational speed (becomes faster or slower) by the difference in the interval between the synchronization signals. That is, there is a problem that rotation control with the period of the reference signal causes rotation unevenness.

  Therefore, the present invention has been made in view of the above problems, and the problem is that even if the information recording medium is such that a part of the synchronization signal is recorded at a different interval from other synchronization signals. An object of the present invention is to provide an information recording apparatus and an information recording method capable of accurately recording information.

In order to solve the above problems, the invention according to claim 1, an information recording apparatus for recording record information in Purijo Hogaki recording information recording medium, the pre-information, the pre-information Depending on the recording position, a period interval of m times (m is a natural number of 2 or more) a unit period corresponding to a recording unit in a recording format to which the recording information should comply, or k times the unit period from the period interval. (K is a natural number and k <m) is recorded on the information recording medium at an interval deviated by an interval, pre-information detecting means for detecting the pre-information and generating a pre-information signal, and the pre-information signal A clock generation means for generating a clock signal based on the memory, a memory for temporarily storing the recording information, and reading the stored recording information in synchronization with the clock signal, and the reading Recording means for recording the record information in the recording medium, the 備Ru.

In order to solve the above problems, the invention according to claim 10, an information recording method for recording record information in Purijo Hogaki recording information recording medium, the pre-information, the pre-information Depending on the recording position, a period interval of m times (m is a natural number of 2 or more) a unit period corresponding to a recording unit in a recording format to which the recording information should comply, or k times the unit period from the period interval. A pre-information detection step for detecting the pre-information and generating a pre-information signal, wherein the pre-information signal is recorded on the information recording medium at an interval deviated by an interval of (k is a natural number and k <m); A clock generation step for generating a clock signal based on the memory and a memory for temporarily storing the recording information and reading the stored recording information in synchronization with the clock signal. A step configured to include a recording step of recording the read out record information on the recording medium.

  Next, preferred embodiments of the present invention will be described with reference to the drawings.

  Note that the embodiments described below have been actively developed in recent years, and the recording density has been dramatically improved as compared with a conventional CD (Compact Disk) or the like. In the present embodiment, the present invention is applied to a WO (Write Once) type DVD-R that can be additionally written, among high-density optical discs (hereinafter referred to as DVDs) capable of recording.

(1) Configuration of DVD-R First, before describing a specific embodiment corresponding to the present invention, an outline of a DVD-R to which this embodiment is applied will be described with reference to FIGS. explain.

  Generally, in an additionally writable optical disc or the like, pre-information for position search when recording information is written is recorded in advance on the optical disc or the like at a pre-format stage at the time of manufacturing the optical disc or the like. Here, the pre-information includes address information indicating the writing position of the recording information on the optical disc.

  In addition, a write-once optical disk is usually provided with a groove track for information recording and a land track on the information recording surface for guiding the irradiation position of the light beam for information recording on the groove track. In the DVD-R, pre-information is recorded by forming pre-pits on the land track with a cutting device or the like.

  Next, a specific configuration example of the DVD-R will be described with reference to FIG.

  As shown in FIG. 1, the DVD-R 1 is a dye-type DVD-R having a dye film 5 and capable of writing information only once. The groove track 2 and the groove track 2 are used as reproduction light or recording light. A land track 3 for guiding the light beam B is formed by a cutting device or the like. Further, a protective film 7 for protecting them and a gold vapor deposition film 6 for reflecting the light beam B when reproducing recorded information are provided. A pre-pit 4 corresponding to the pre-information is formed on the land track 3 by a cutting device or the like. This pre-pit 4 is formed in advance before the DVD-R 1 is shipped.

  Then, when recording information data (information data such as image information to be originally recorded other than the pre-information) is recorded on the DVD-R 1, the pre-information is acquired in advance by detecting the pre-pit 4 in a predetermined information recording device. Based on this, the rotational speed of the DVD-R1 (so-called CLV rotation in the case of DVD-R1) is set, and address information corresponding to the recording information is acquired. Based on this, the record information is recorded at the corresponding recording position on the DVD-R1.

  Here, at the time of recording the recording information, the recording information is recorded by forming the recording information pit corresponding to the recording information on the groove track 2 by irradiating the center of the light beam B with the center of the groove track 2. Form. At this time, the size of the light spot SP is set so that a part of the light spot SP is irradiated not only on the groove track 2 but also on the land track 3 as shown in FIG. Then, the pre-information is detected from the pre-pit 4 prior to recording of the record information by the tangential push-pull method described later using a part of the reflected light of the light spot SP irradiated on the land track 3.

  Next, the pre-information recording format in the DVD-R 1 will be described with reference to FIG.

  As shown in FIG. 2, pre-information in DVD-R1 is recorded for each sync frame. Furthermore, one recording sector is formed by 26 sync frames. One ECC (Error Correcting Code) block is formed by 16 recording sectors. Furthermore, one sync frame has a length of 1488 times (1488T) a unit length (hereinafter simply referred to as “T”) corresponding to a bit interval defined by a recording format when recording information is recorded. is doing. In the present embodiment, the sync frame period having the length of 1488T is hereinafter referred to as a unit period. In FIG. 2, a plurality of recording sectors are continuously recorded on one land track 3.

  Here, the pre-information is recorded at the position of 2T from the start position of each sync frame in the first 14T length portion of each sync frame. At this time, in one recording sector, Pre-information is recorded only in even-numbered sync frames (hereinafter referred to as EVEN frames) or only in odd-numbered sync frames (hereinafter referred to as ODD frames). The recorded pre-information is classified into a sync pre-signal corresponding to the sync signal in the pre-information and data pre-information. Of these, the sync pre-signal records the pre-information at the head of each recording sector. The synchronization pre-signal (EVEN synchronization pre-signal) recorded at the position of the sync frame to be recorded and recorded in the EVEN frame and the synchronization pre-signal (ODD synchronization pre-signal) recorded in the ODD frame are as shown in FIG. In addition, it is possible to determine whether the pre-information is recorded in the EVEN frame or the ODD frame by reading the recorded information in a different pattern and recording the recorded information.

  As described above, the pre-information is distributed and recorded in the head 14T portion of the sync frame in the EVEN frame or the ODD frame because the pre-pits 4 are concentrated in one place when the DVD-R 1 is manufactured. In this portion, when the material constituting the dye film 5 is applied by spin coating or the like, the material flows into the pre-pit 4 formed in advance, and is designed on the groove track 2. This is because the dye film 5 having a predetermined thickness is not formed (if the dye film 5 is not formed to have a predetermined thickness, adverse effects such as change of a direct current component occur during reproduction of recorded information. It will be.)

  On the other hand, data pre-information is distributed and recorded in a plurality of sync frames. In one sync frame, as shown in FIG. 2, only the data pre-information corresponding to “1” is the start position of each sync frame. Is recorded at a position 2T to a length of 2T. Therefore, data pre-information corresponding to “0” is not formed as pre-pits.

  Note that FIG. 2 shows a state where pre-information is recorded in the EVEN frame in the recording sector 0 and pre-information is recorded in the ODD frame in the recording sector 2 as an example.

  Further, the recording information recorded by the information recording apparatus based on the detected pre-information is recorded in the same format as the recording format shown in FIG. At this time, in the recording information, a synchronization signal is recorded at a length of 14T at the head of all the sync frames, and data such as image information to be recorded at a position other than the head 14T in one sync frame. In the pre-information, no information is recorded at positions other than the head 14T in one sync frame.

  Here, as described above, in the DVD-R1, pre-information is recorded only in the EVEN frame or only in the ODD frame, and the synchronization pre-signal is included in the position of the first EVEN frame or ODD frame in each recording sector. Since these are recorded, when these are detected during recording of recording information, when the recording position of the pre-information changes from the EVEN frame to the ODD frame, or when the ODD frame changes to the EVEN frame, the EVEN frame is The period of the detected synchronization pre-signal changes as compared to the case where the ODD frames are continuous or the case where they are continuous.

  That is, as shown in FIG. 3, when the EVEN frame is continuous (hereinafter referred to as pattern 1) or the ODD frame is continuous (hereinafter referred to as pattern 4), the synchronization pre-signal is exactly one recording sector. However, when the EVEN frame changes to the ODD frame (hereinafter referred to as pattern 2), the interval of the synchronization pre-signal at the time of the change is the interval of one recording sector. In the case of changing from an ODD frame to an EVEN frame (hereinafter referred to as pattern 3), the interval of the sync pre-signal at the time of the change is longer than the interval of one recording sector. Is shortened by one sync frame. Even in the case of pattern 2 or pattern 3, after each change, the period of the synchronization pre-signal returns to the length of one recording sector.

  As described above, according to the present invention, accurate CLV rotation can be maintained even if a DVD-R1 is recorded in which some sync pre-signals are recorded at intervals different from other sync pre-signals. Can do it.

(2) Embodiment Next, an embodiment corresponding to the present invention will be described with reference to FIGS.

  First, the overall configuration of the rotation control device according to the present embodiment will be described with reference to FIG. FIG. 4 shows only the portion related to the rotation control device of the present embodiment in the configuration of the information recording device for recording the recording information on the DVD-R 1. Since the configuration of other parts of the information recording apparatus such as the focus servo and tracking servo for the beam B is the same as that of the prior art, illustration and detailed description thereof are omitted.

  As shown in FIG. 4, the rotation control device SS1 of the present embodiment includes a laser diode (not shown), an objective lens (to be described later), a beam splitter, a photodetector, and the like, and pre-information is recorded by forming a pre-pit 4. A pickup 10 that irradiates a DVD-R 1 with a light beam B as recording light, receives reflected light from the pre-pit 4, and outputs a detection signal SP for pre-information detection by the tangential push-pull method; , A pre-pit signal reproduction circuit 11 that generates a reproduction signal SPP as pre-information corresponding to the pre-pit 4 from the detection signal SP, and a synchronization pre-signal is detected separately from the reproduction signal SPP, and the timing at which the synchronization pre-signal is detected It corresponds to the synchronous pre-signal detector 12 that outputs the corresponding timing signal ST and the bit interval of the recording information. A unit signal corresponding to a sync frame period (1488T) is generated from a reference signal generator 13 that generates a periodic signal (reference signal) of unit length T and a reference signal output from the reference signal generator 13, The phase comparison circuit 14 as the first phase comparison means for comparing the phase of the unit period signal and the timing signal ST output from the synchronous pre-signal detector 12 to output the phase difference signal SPD1, and similarly, the pre-pit The phase comparison circuit 15 as a second phase comparison means for comparing the phase of the reproduction signal SPP output from the signal reproduction circuit 11 and outputting the phase difference signal SPD2, and the output signal SPD1 from the phase comparison circuit 14 are controlled to rotate. An amplitude / phase equalization circuit 16 for defining the required gain and phase characteristics of the system, and an output signal SPD2 from the phase comparison circuit 15 in the same manner. Addition for generating the rotation control signal SC by adding the amplitude phase equalization circuit 17 for defining the gain and phase characteristics to be important and the output signals SPD11 and SPD21 from the amplitude phase equalization circuits 16 and 17 The circuit 18 includes a driver circuit 19 that converts the rotation control signal SC output from the adder circuit 18 into a current signal and applies the current signal to the motor 20.

  Next, the overall operation will be described.

  The pre-information detected and reproduced from the DVD-R 1 by the pickup 10 and the pre-pit signal reproduction circuit 11 is input to the synchronous pre-signal detector 12 and the phase comparison circuit 15 as a reproduction signal SPP. A signal is detected and a timing signal ST corresponding to the synchronous pre-signal is output. Then, the phase comparison circuit 15 compares the phase of a reference signal, which will be described later, with the input reproduction signal SPP, and sends it to the addition circuit 18 via the amplitude phase equalization circuit 17 as a precision error signal SPD2 for rotation control. Entered.

  On the other hand, the timing signal ST output from the synchronous pre-signal detector 12 is input to the phase comparison circuit 14 and subjected to phase comparison with a reference signal, which will be described later, and as the coarse error signal SPD1 for rotation control, The signal is input to the adder circuit 18 through the equalizer circuit 16.

  The adder circuit 18 adds the rough error signal SPD1 and the fine error signal SPD2 to generate a rotation control signal SC, and this rotation control signal SC is applied to the spindle motor 20 via the driver circuit 19.

  Next, detection of pre-information by the above-described tangential push-pull method will be described with reference to FIGS. 5 and 6 together with detailed configurations of the pickup 10 and the pre-pit signal reproduction circuit 11.

  The detection by the tangential push-pull method means detection using the push-pull method in the rotation direction of the DVD-R1, and the detection from the light spot SP by the light beam B formed on the land track 3 of the DVD-R1. The reflected light is based on the difference signal of the partial detector in the photodetector divided by the two partial detectors by a dividing line that is optically perpendicular to the moving direction of the prepit 4 (disk rotation direction). This is a method for reproducing pre-information.

  More specifically, as shown in FIG. 5, the light beam B as the recording light (reproduced light for the pre-pit 4) generated by a laser diode (not shown) or the like is a deflection beam splitter. The light is reflected by 31 and is focused on the groove track 2 and land track 3 of the DVD-R 1 (see FIG. 1) by the objective lens 30. Then, the reflected light of the light beam B, which is modulated by the pre-pit 4 and whose polarization plane is rotated by reflection by the DVD-R1, is transmitted through the deflection beam splitter 31 by the rotation of the deflection surface, and in the rotation direction of the DVD-R1. Each light receiving surface of the photodetector 32 divided into the two partial detectors 32a and 32b is irradiated and detected by an optically vertical dividing line. The light receiving outputs of the partial detectors 32B1 and 32B2 (in the following description, the outputs of the partial detectors are denoted by reference numerals B1 and B2) are subtracted by the subtractor 33 constituting the prepit signal reproduction circuit 11, and the difference between them is subtracted. The signals (B1-B2) are compared with the reference voltages + V0 and -V0 input from the reference voltage units 37 and 38 by the subtractors 34 and 35, respectively, and the outputs of the subtracters 34 and 35 are input to the flip-flop circuit 36, respectively. Is done. The output of the flip-flop circuit 36 is output to the synchronous pre-signal detector 12 and the phase comparison circuit 15 as a reproduction signal (pre-pit information) SPP.

  Next, generation of a difference signal (tangential push-pull signal) (B1-B2) and a reproduction signal SPP by the photodetector 32 and the pre-pit signal reproduction circuit 11 will be described with reference to FIG.

  In FIG. 6, when the reflected light from the pre-pit 4 having the shape shown in the sectional view in the rotation direction of the DVD-R 1 in FIG. 6 (a) is received by the photodetector 32, the light reception outputs of the partial detectors 32A and 32B are as follows. Based on the positional shift, RF (Radio Frequency) signals (B1 and B2) having a phase shift as shown in FIG. 6B are output from the respective partial detectors 32A and 32B. Then, the difference signal (tangential push-pull signal) (B1-B2) shown in FIG. 6B is generated by taking the difference between the respective RF signals by the subtractor 33. The difference signals are input to the subtracters 34 and 35, respectively, compared with the reference voltages + V0 and -V0, respectively, and the flip-flop circuit 36 is operated using the respective comparison results, whereby the reproduction shown in FIG. A signal SPP is generated. As a result, the pre-information (including the sync pre-signal and the data pre-information) included in the reproduction signal SPP is output to the sync pre-signal detector 12 and the phase comparator 15.

  Next, phase comparison operations in the phase comparison circuit 14 and the phase comparison circuit 15 will be described with reference to FIGS.

  First, the configuration of the phase comparison circuits 14 and 15 will be described with reference to FIG.

  As shown in FIG. 7A, the phase comparison circuit 14 includes a counter 141 that counts a reference signal pulse SREF having a unit length T corresponding to the bit interval of recording information from the reference signal generator 13, and the reference signal. Is divided by 744, and a clear pulse generator 142 that generates a clear pulse signal at an interval of sync frame period (1488T), and a count value output from the counter 141 is used as a sync pre signal detection signal ST. And a latch circuit 143 that latches at a timing outputted from the.

  As shown in FIG. 7B, the phase comparison circuit 15 outputs a signal that determines the latch timing in the latch circuit 153 in synchronization with the rising edge of the timing signal SPP output from the prepit signal reproduction circuit 11. This pulse signal is generated by an MMV (Mono Multi Vibrator) 154. The reason why this MMV 154 is interposed is that the sync pre-signal in the pre-pit reproduction signal SPP has two pulse signals in one sync frame as shown in FIG. If the SRAMP signal is latched by the next pulse signal following the existing first pulse signal, the phase comparison timing will be shifted from the timing by other data pre-signals, and this timing shift is recognized as disturbance, This will affect the rotation control. To prevent this, the pulse width of the pulse signal output from the MMV 154 (this MMV does not accept an input pulse signal that arrives while the MMV outputs a pulse signal) is set to 8T or more, and the synchronization pre- The next pulse signal following the first pulse signal of the signal is masked. Since the other configuration except this configuration is the same as that of the phase comparison circuit 14, the description thereof is omitted.

  Next, the phase comparison operation performed in the above configuration will be described with reference to FIGS. 8 is a waveform diagram in each block of the phase comparison circuit 14 shown in FIG. 7A, and FIG. 9 is a waveform diagram in each block of the phase comparison circuit 15 shown in FIG. 7B. .

  The counter 141 sequentially counts input reference signal pulses SREF. On the other hand, the clear pulse generator 142 generates a pulse signal having a predetermined width in accordance with, for example, a falling edge of a divided signal (FIG. 8B) having a period of 1488T obtained by dividing the reference signal SREF by 744 ( In FIG. 8D, this is input to the counter 141 as a clear pulse signal. The counter 141 resets the count value to zero at the timing when the clear pulse signal is input, and starts the counting operation again. Therefore, the count value output from the counter 141 is a DVD as shown in FIG. The ramp signal SRAMP is a monotonically increasing function having a sync frame period (1488T) which is a unit period in the recording format of -R1. The ramp signal SRAMP is input to the latch circuit 143, and is latched at the rising timing of the detection signal ST (FIG. 8C) of the synchronization pre-signal supplied from the synchronization pre-signal detection circuit 12. That is, the amplitude level of the ramp signal (count value of the counter 141) at the rising timing of the detection signal ST is used as a sample value and held until the next detection signal arrives (FIG. 8 (f)). As shown in FIG. 2, the sync pre-signal is recorded from a position 2T from the start position of either the first or second sync frame of each recording sector regardless of the EVEN sync pre-signal and the ODD sync pre-signal. Therefore, the amplitude level of the ramp signal SRAMP having the sync frame period latched at the detection timing of the synchronous pre-signal includes phase difference information with respect to the reference signal.

  That is, when the synchronization pre-signal detection timing (rotation phase of DVD-R1) and the reference signal pulse SREF are in phase, the ramp signal SRAMP generated from the reference signal pulse SREF is always at a predetermined amplitude level. For example, the intermediate level value (the amplitude level at the point x in FIG. 8E) is held at the rising timing of the detection signal ST of the synchronous pre-signal.

  Further, when the detection timing of the synchronization pre-signal is advanced from the reference signal, a level value smaller than the intermediate level value (amplitude level at the point x−1 in FIG. 8E) is held. When the pre-pit detection timing is delayed from the reference signal, a level value (amplitude level at point x + 1 in FIG. 8 (e)) larger than the intermediate value level is held.

  The output signal SPD1 from the latch circuit 143 is output as a phase error signal.

  In the phase comparison circuit 15, the timing signal input to the latch circuit 153 is a pulse signal SPPmmv generated via the MMV 154 based on the timing signal SPP (FIG. 9A) output from the pre-pit signal reproduction circuit 11. (FIG. 9C). The pre-pit signal is composed of a sync pre-signal and a data pre-signal, and the data pre-signal is recorded from a position 2T from the start position of the sync frame in the same manner as the sync pre-signal, and is latched at the detection timing of this pre-pit signal. The amplitude level of the ramp signal SRAMP (FIG. 9 (e)) having the sync frame period includes the phase difference information with respect to the reference signal SREF, and is output as the phase error signal SPD2 (FIG. 9 (f)).

  Note that the minimum interval at which the prepit signal is detected is an interval of two sync frames. Therefore, the phase difference signal extracted by the phase comparison circuit 15 (hereinafter referred to as a fine phase difference signal) is a phase difference signal (hereinafter referred to as a coarse phase difference signal) extracted by the phase comparison circuit 14 at almost one recording sector interval. .)) And a finer phase difference component.

  The coarse phase difference signal SPD1 output from the phase comparison circuit 14 generated as described above and the fine phase difference signal SPD2 output from the phase comparison circuit 15 are added by the addition circuit 18 to obtain the rotation control signal SC. The rotation speed of the motor 20 is controlled so that the detection timing of the synchronous pre-signal and the detection timing of the pre-pit signal always latch the intermediate level value of the ramp signal, which is output to the spindle motor 2.

  In the above embodiment, an example in which a ramp signal is used as a monotonically increasing function having a unit period has been described. However, as a monotonic increasing function, for example, a phase comparison with a detection timing of a prepit is performed like a trapezoidal wave. Even if the signal waveform monotonously increases only in the range that needs to be performed, or the ramp signal in the present embodiment is a monotonously decreasing waveform signal that is the waveform of the right and left, an effect equivalent to that of the phase comparison circuit in the present embodiment is expected. it can.

  In the above embodiment, the example in which the unit period is the sync frame period has been described. However, the period is shorter than the sync frame period and the period interval in which the prepit exists (in this embodiment, two sync periods). It is also possible to set a period that is an integral multiple of (frame period) as a unit period.

  By the way, according to the DVD-R pre-information recording format described above, the sync pre-signal changes from the EVEN frame to the ODD frame (pattern 2) and from the ODD frame to the EVEN frame as shown in FIG. In this case (pattern 3), the interval of the sync pre-signal at the time of the change becomes longer or shorter by one sync frame than the interval of one recording sector. As described above, even when some of the synchronization pre-signals are recorded at intervals different from those of other synchronization pre-signals, the phase comparison circuit according to the present embodiment records the synchronization pre-signals. The phase error signal can be accurately extracted without being affected by the change in the interval. That is, the ramp signal to be phase-compared with the sync pre-signal is not a recording sector period but a signal having a repetition period of a sync frame that is a unit block constituting the recording sector. Since the phase difference from the reference signal is detected by sampling / holding at the detection timing of the synchronization pre-signal, the recording interval of the synchronization pre-signal is in sync frame units as in patterns 2 and 3 in FIG. As long as it changes, it is possible to extract the phase error signal accurately.

  On the other hand, the data pre-signal is recorded according to the pre-data, and “0” data is not recorded as pre-pits as described above. Therefore, the output timing of the timing signal SPP output from the prepit signal reproduction circuit 11 varies depending on the predata to be recorded. For example, when the pre-data to be recorded is “1011001...”, The output intervals of the timing signal SPP are 4 sync frames, 2 sync frames, 6 sync frames,.

  However, even in such a case, since the recording interval of the pre-pit is a fluctuation in sync frame units, the phase comparison circuit 15 in the present embodiment that performs phase comparison with the ramp signal having the sync frame period is accurate. A phase difference signal can be extracted.

  As described above, according to the rotation control device SS1 of the present embodiment, rotation control is performed using a signal obtained by sampling / holding the ramp signal of the sync frame period at the detection timing of the pre-information recorded on the information recording medium as a control signal. Therefore, even if the cycle in which the pre-pit signal composed of the sync pre-signal and the data pre-signal is detected changes in sync frames, the rotation state (CLV) of the DVD-R 1 can be maintained without being changed.

  By the way, in an optical disk in which information data can be written, such as a DVD-R, even when the information data is recorded, the optical disk whose rotation phase is controlled by the rotation control device as described in this embodiment. Since a minute fluctuation component (jitter) on the time axis due to eccentricity of the optical disc remains, when recording information data on the optical disc, the timing of recording the information data is set to the fluctuation component due to the jitter. It needs to be accurately synchronized. Therefore, a phase synchronization apparatus suitable for an optical disc or the like in which some sync pre-signals are recorded at intervals different from other sync pre-signals such as the DVD-R1 described above will be described below.

  FIG. 10 shows an information recording apparatus capable of writing information data on the DVD-R1 that is rotationally driven by the above-described rotation control apparatus.

  First, the overall configuration will be described. In FIG. 10, the same components as those in FIG. 4 are denoted by the same reference numerals and description thereof is omitted.

  The information recording apparatus shown in FIG. 10 corresponds to a RAM (Random Access Memory) 50 that stores information data in advance, and the recording information data read from the RAM 50 corresponds to the bit interval of the recording information data given from the reference signal generator 13. Is temporarily stored based on a write clock signal SREF, which is a periodic signal (reference signal) of unit length T, and is the same as a write clock signal SREF given from a phase locked loop (PLL) circuit 52 described later. In order to generate a FIFO (First In First Out) memory 51 that reads out in the order stored based on a read clock signal SCKV1 that is a frequency, and a read clock signal SCKV1 that is phase-synchronized with a jitter component included in a pre-pit signal read from a DVD-R1 PLL circuit 52 and the residual error component of PLL circuit 52 are absorbed. Because of FF and a (Feed Forward) circuit 53.

  Next, a specific configuration of the PLL circuit 52 will be described.

  The PLL circuit 52 compares the phase of the above-described VCO (Voltage Controlled Oscillator) 521 that generates the read clock signal, the read clock signal SCKV1 from the VCO 521, and the prepit signal output from the prepit signal reproduction circuit 11. And an amplitude phase equalization circuit 523 for defining the output signal from the phase comparison circuit 522 so as to have the required gain and phase characteristics in the PLL circuit 52.

  The FF circuit 53 also outputs a VCO 531 whose oscillation frequency is controlled by a phase error signal not subject to band limitation by the amplitude phase equalization circuit 523 output from the phase comparison circuit 522, and recording information data output from the FIFO 51 to the VCO 521. The FIFO 532 is temporarily stored on the basis of the clock signal SCKV1 supplied from the CPU and read out in the order of storage based on the clock signal SCKV2 supplied from the VCO 531.

  Next, the overall operation based on the above configuration will be described.

  The RAM 50 is designated by a CPU (not shown) when a periodic signal of one recording sector period obtained by dividing the reference signal output from the reference signal oscillator 13 by the frequency dividing circuit 131 at a predetermined dividing ratio is input. The record information data recorded at the address is read out, and the read record information data is converted into serial data by a parallel / serial converter (not shown) and output to the FIFO 51. The FIFO 51 writes the record information data based on the write clock signal SREF given from the reference signal generator 13. At the same time, the information is read from the FIFO 51 in the order in which the record information data is written based on the read clock signal SCKV1 supplied from the PLL circuit 52. At this time, since the clock signal SCKV1 output from the PLL circuit 52 includes a phase fluctuation component synchronized with the low frequency component of the jitter component accompanying the rotation control of the DVD-R1, the data sequence of the recording information data read from the FIFO 51 is The phase is synchronized with the low frequency component of the jitter component. The record information data string read from the FIFO 51 is further input to the FF 53. The FF 53 is provided for phase synchronization with respect to a high-frequency jitter component that cannot be synchronized by the PLL circuit 52, and the recording information data phase-synchronized with the low-frequency fluctuation component of the jitter component output from the FIFO 51 The column is written in the FIFO 532 in synchronization with the clock signal sCKV1, and is read based on the clock signal sCKV2 that is an output signal from the VCO531. The oscillation frequency of the output signal sCKV2 from the VCO 531 serving as a read clock signal of the FIFO 532 varies based on the phase difference signal output from the phase comparison circuit 522 in the PLL circuit 52. This phase difference signal is a so-called residual error component from which an error component that can be phase-synchronized by the PLL circuit 52 is removed. Therefore, the FF circuit 53 can achieve phase synchronization even for a jitter component that cannot be phase synchronized by the FIFO 51.

  As described above, the two-stage configuration of the FIFO 51 and the FF circuit 53 makes it possible to generate a recording information data sequence in which phase synchronization is achieved over the entire jitter component generated along with the rotation control of the DVD-R 1. Become. The recording information data string output from the FF circuit 53 is supplied to an APC (Auto Power Control) circuit (not shown) that controls the irradiation power of the light beam B, and the irradiation power is controlled according to the data. At this time, the fluctuation on the time axis of the recorded information data string is synchronized with the fluctuation on the time axis accompanying the rotation control of the DVD-R 1 by the FIFO 51 and the FF circuit 53, so that the desired recording position on the disc is desired. It is possible to record as a pit row having a pit length of.

  Note that the FF circuit 53 is not necessarily provided when the operation band of the PLL circuit 52 is sufficiently wide.

  Next, the operation of the PLL circuit 52 will be described.

  The PLL circuit 52 is provided in order to change the phase of the clock signal SCKV1 output from the VCO 521 in synchronization with the fluctuation on the time axis of the pre-pit signal reproduced from the DVD-R1.

  In general, a PLL circuit includes a synchronization signal recorded on a recording medium at regular intervals, and a divided signal generated by dividing the clock signal generated from the VCO so as to have the same cycle as the synchronization signal. The phase of the VCO is adjusted and the oscillation period of the VCO is adjusted so that the phase difference becomes zero, so that the phase synchronization is performed with respect to the fluctuation component due to jitter included in the reproduction signal (synchronization signal). However, when the sync signal is recorded at intervals different from the other sync signals for some sync signals, such as the sync pre-signal in DVD-R1, such a general signal is used. In the PLL circuit configuration, it is impossible to maintain a phase synchronization state with respect to a predetermined frequency.

  That is, when a general PLL circuit is applied to an optical disk or the like in which some synchronization signals are recorded at intervals different from those of other synchronization signals, the intervals of the synchronization signals differing from other synchronization signals. Since the phase of the divided signal generated by dividing the clock signal obtained from the VCO is compared with the phase of the divided signal (corresponding to the interval of the other synchronization signal), the interval is different. In the part where the synchronization signal different from the synchronization signal is detected, the phase difference increases by the difference in the interval of the synchronization signal, and the oscillation frequency of the VCO is deviated from the original frequency (whether the frequency should be increased). (Or make it smaller). In other words, the part where the interval of the synchronization signal is different is recognized as a change on the time axis due to some disturbance applied to the recording medium, and the oscillation frequency is changed to follow the fluctuation due to the disturbance. It is.

  Therefore, in the PLL circuit 52 used in the present embodiment, as shown in FIG. 11, the same configuration as the phase comparison circuit 15 described in FIG.

  That is, the counter 522a that counts the clock signal SCKV1 having a periodic component of unit length T corresponding to the bit interval of the recording information data generated by the VCO 521, and the sync frame period (1488T) by dividing the clock signal SCKV1 by 744. ) A clear pulse generator 522b that generates a clear pulse signal at intervals, and a count value output from the counter is latched by a timing signal output from the MMV 522d synchronized with the timing of the timing signal SPP output from the prepit signal reproduction circuit And a latch circuit 522c.

  Even in the case where the interval of some of the synchronization signals to be compared is different from the interval of the other synchronization signals, such as the pre-pit signal formed on the DVD-R1 by the phase comparison circuit 522, The reason why the phase comparison can be performed accurately is as described in the phase comparison circuits 14 and 15.

  That is, based on the clock signal SCKV1 from the VCO, a ramp signal having a sync frame period (1488T) which is a unit period in the recording format of DVD-R1 is sampled / held at the detection timing of pre-information recorded on the information recording medium. Since the oscillation period of the clock signal SCKV1 output from the VCO 521 is controlled using the processed signal as a phase difference signal, even if the period in which the pre-pit signal composed of the synchronization pre-signal and the data pre-signal is detected changes in units of sync frames It is possible to generate the clock signal SCKV1 in which the phase synchronization state with respect to the frequency is maintained.

  According to the embodiment described above, the phase difference with the unit period which is a period of an integral multiple of the period interval of the prepit 4 is compared at the timing when the prepit 4 is detected, and this phase difference is canceled out. Since the rotation of the spindle motor 20 is controlled, a predetermined rotational state can be accurately obtained even when the prepits 4 cannot be obtained at predetermined intervals.

  Therefore, even if the recording interval of some of the synchronization signals is recorded from a predetermined interval, DVD-R1 is recorded and reproduced accurately by maintaining an accurate rotation state. Can do.

  Further, since the ramp signal SRAMP having a unit cycle is generated and the phase difference is detected based on the amplitude value of the ramp signal SRAMP at the detection timing of the prepit 4, the phase difference can be detected with a simple process.

  Furthermore, a coarse phase difference signal SPD1 obtained by comparing a phase difference with a unit period which is a period of an integral multiple of the period interval of the synchronization pits at the detection timing of the synchronization pits detected at a relatively coarse interval; It is obtained by comparing the phase difference with the unit period which is a period of an integral multiple of the period interval of the prepit 4 at the detection timing of the prepit 4 detected at a relatively dense interval composed of the synchronous pre signal and the data pre signal. Since the rotation of the spindle motor 20 is controlled so as to cancel out the phase difference based on the fine phase difference signal to be obtained and the addition phase difference signal SC obtained by adding the coarse phase difference signal and the fine phase difference signal, the prepit 4 In addition to being able to accurately obtain a predetermined rotation state even when the frequency cannot be obtained at a predetermined cycle interval, the rotation control is more accurate than the rotation control using only synchronous pits. It can be carried out to become.

  Therefore, even in the DVD-R1 in which the recording interval of some of the synchronization signals is recorded from a predetermined interval, accurate information recording / reproduction can be performed by maintaining an accurate rotation state. it can.

It is a perspective view which shows the example of DVD-R which formed the prepit in the land track. It is a figure which shows the recording format of pre information or recording information. It is a figure which shows the detection pattern of a synchronous pre signal. It is a block diagram which shows schematic structure of the rotation control apparatus of embodiment. 1 is a block diagram showing a schematic configuration of a pickup and pre-pit signal reproduction circuit of an embodiment. It is a figure explaining the production | generation of a tangential push pull signal. It is a block diagram which shows the structure of the phase comparison circuits 14 and 15 of embodiment. It is a wave form diagram in each block of phase comparison circuit 14 of an embodiment. It is a wave form diagram in each block of phase comparison circuit 15 of an embodiment. It is a block diagram which shows the schematic structure of the information recording device using the rotation control apparatus of embodiment. It is a block diagram which shows the structure of the phase comparison circuit 522 of the information recording device in FIG.

Explanation of symbols

1 DVD-R
2 Groove track 3 Land track 4 Prepit 5 Dye film 6 Gold vapor deposition film 7 Protective layer 10 Pickup 11 Prepit signal reproduction circuit 12 Synchronous presignal detector 13 Reference signal generator 14, 15 Phase comparison circuit 16, 17 Amplitude phase equalization circuit 18 addition circuit 19 driver circuit 20 spindle motor SREF reference signal pulse SPD1 coarse phase error signal SPD2 fine phase error signal SC addition phase error signal ST synchronous pre-signal detection signal SPP pre-pit signal reproduction signal

Claims (18)

An information recording apparatus for recording record information in Purijo Hogaki recording information recording medium,
The pre-information is a period interval of m times (m is a natural number of 2 or more) a unit period corresponding to a recording unit in a recording format to which the recording information should conform, or the period interval, depending on the recording position of the pre-information. To k times the unit period (k is a natural number and k <m) and is recorded on the information recording medium at an interval deviated by an interval of
Pre-information detecting means for detecting the pre-information and generating a pre-information signal;
Clock generating means for generating a clock signal based on the pre-information signal;
A memory that temporarily stores the recording information and reads the stored recording information in synchronization with the clock signal;
Recording means for recording the read recording information on the recording medium;
An information recording apparatus comprising: The information recording apparatus according to claim 1, wherein the clock generation unit is a PLL circuit . The PLL circuit includes:
A voltage controlled oscillator for generating the clock signal;
A phase comparison circuit that compares the pre-information signal and the clock signal and generates a phase comparison output signal;
An equivalent circuit for adjusting the phase comparison output signal;
The information recording apparatus according to claim 2 , further comprising: Reference signal generating means for generating a reference signal is further provided,
Wherein the memory information recording apparatus according to any one of claims 1 to 3, characterized in that storing the record information in synchronization with the reference signal. 5. The information recording apparatus according to claim 1 , further comprising a feedforward circuit that removes a residual phase error component included in the recording information when the recording information is read from the memory . A feedforward circuit for removing a residual phase error component included in the recording information when the recording information is read from the memory;
The feedforward circuit is
A second voltage controlled oscillator that generates a second clock signal in response to the phase comparison output signal;
A second memory for writing the recording information read from the memory based on the clock signal, and for reading the written recording information based on the second clock signal;
The information recording apparatus according to claim 3 , further comprising: The information recording apparatus according to claim 6 , wherein the unit period is 1488 times the unit length . 5. The information recording apparatus according to claim 4 , wherein the reference signal is a periodic signal having a unit length corresponding to a bit length defined by a recording format of the recording information. The unit period, the information recording apparatus according to any one of claims 1 to 8, characterized in that it is one sync frame.   An information recording method for recording record information on an information recording medium on which pre-information is recorded,
  The pre-information is a period interval of m times (m is a natural number of 2 or more) a unit period corresponding to a recording unit in a recording format to which the recording information should conform, or the period interval, depending on the recording position of the pre-information. To k times the unit period (k is a natural number and k <m) and is recorded on the information recording medium at an interval deviated by an interval of
  A pre-information detection step of detecting the pre-information and generating a pre-information signal;
  A clock generation step of generating a clock signal based on the pre-information signal;
  A storage and reading step of temporarily storing the recording information using a memory and reading the stored recording information in synchronization with the clock signal;
  A recording step of recording the read recording information on the recording medium;
  An information recording method comprising: The clock in the generating step, the information recording method according to claim 1 0, characterized in that to generate the clock signal using a PLL circuit. The clock generation step includes
Generating the clock signal using a voltage controlled oscillator;
A phase comparison step of comparing the pre-information signal and the clock signal to generate a phase comparison output signal;
An adjustment step of adjusting the phase comparison output signal using an equivalent circuit;
The information recording method according to claim 11 , further comprising : A reference signal generating step for generating a reference signal;
13. The information recording method according to claim 10 , wherein in the storing / reading step, the recording information is stored in synchronization with the reference signal . 14. The method according to claim 10 , further comprising a removal step of removing a residual phase error component included in the recording information by using a feedforward circuit when the recording information is read from the memory in the storing / reading step. An information recording method according to any one of the above. And further comprising a removal step of removing a residual phase error component included in the recording information using a feedforward circuit when the recording information is read from the memory in the storing and reading step,
The removing step includes
A second generation step of generating a second clock signal in response to the phase comparison output signal using a second voltage controlled oscillator;
A writing / reading step of writing the recording information read from the memory based on the clock signal and reading the written recording information based on the second clock signal using a second memory; ,
The information recording method according to claim 12 , further comprising : The information recording method according to claim 15 , wherein the unit period is 1488 times the unit length . 14. The information recording method according to claim 13 , wherein the reference signal is a periodic signal having a unit length corresponding to a bit length defined by a recording format of the recording information . The information recording method according to claim 10 , wherein the unit period is one sync frame .

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