JP2004104989A - Abnormality detection device of battery pack - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a detector which detects disconnection of a battery pack with a simple configuration, using a circuit that detects an overcharging and an over-discharging of a cell. <P>SOLUTION: When a signal (H level) diagnosing any failure is output from a charge-and-discharge control circuit 5, MOS transistors Q1, Q3 to Qn-1 corresponding to cells s1, s3 to sn-1 are forced to turn off, while MOS transistors Q2, Q4 to Qn corresponding to cells s2, s4 to sn are forced to turn on. At this time, if disconnection has been caused between a positive electrode terminal of the cell s2 and a detection terminal C2, the voltage of the detection terminal C2 becomes equal to a voltage of the negative electrode terminal of the cell s2. With such constitution, an abnormality detection circuit b2 outputs a signal indicating that a voltage between terminals C1 and C2 is abnormal, while an abnormality detection circuit b3 outputs a signal indicating that a voltage between terminals C2 and C3 is abnormal, by which the disconnection is detected. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a battery pack abnormality detecting device configured by connecting a plurality of cells in series, and more particularly to a device for detecting a disconnection of a line connecting a cell and a circuit for controlling a state of the cell. About.

A device for detecting overcharge or overdischarge of a cell based on a voltage between the two detection terminals, having a detection terminal connected to each of both terminals of the cell constituting the battery pack, A method for detecting a connection failure is known (see Patent Document 1). In this connection failure detection method, the discharge circuit connected to each cell is short-circuited for a predetermined time, and then the discharge circuit is opened. If the voltage at the time of opening is almost the same as the short-circuited voltage, the cell and the detection terminal It is determined that the connection between them is bad.

JP 2001-15767 A

However, in the above-described conventional method, when the voltage in the short-circuit state and the voltage in the open state are compared using the voltage comparison circuit used in the over-discharge detection circuit, the connection between the cell and the over-discharge state is made. It is indistinguishable from a defective state. Therefore, there is a problem that it is necessary to prepare two voltage comparison circuits for judging a connection failure and for judging an overdischarge state in order to distinguish between the two.

An abnormality detection device for a battery pack according to the present invention is provided for each of a plurality of cells and a detection terminal connected to both terminals of the plurality of cells, and detects abnormality of a corresponding cell based on a voltage between the detection terminals. Abnormality detection circuit, a short circuit that alternately short-circuits the detection terminals corresponding to a plurality of cells respectively, a control circuit that activates the short circuit, and an abnormality detection circuit when the control circuit activates the short circuit. And a disconnection detecting circuit for detecting a disconnection of a connection line between the cell and the corresponding detection terminal based on the output signal.

According to the abnormality detection device for a battery pack according to the present invention, when the short-circuiting circuit that short-circuits the detection terminals corresponding to the plurality of cells every other one is activated, based on the signal output from the abnormality detection circuit, Since the disconnection of the connection line between the terminal and the corresponding detection terminal is detected, the disconnection can be reliably detected with a simple circuit configuration.

-1st Embodiment-
FIG. 1 is a diagram showing a configuration of a first embodiment of a battery pack abnormality detecting device according to the present invention. The assembled battery 1 is configured by connecting n chargeable / dischargeable cells s1 to sn in series. The detection terminals C0 to Cn are connected to the positive terminal or the negative terminal of each of the cells s1 to sn. For example, the detection terminal C0 is connected to the negative terminal of the cell s1, and the detection terminal C1 is connected to the positive terminal of the cell s1 and the negative terminal of the cell s2.

The current bypass voltage detection circuits a1 to an are provided for each of the cells s1 to sn. When detecting that the voltage between the terminals of the corresponding cells s1 to sn has risen above the first predetermined voltage V1, the circuits have the H level. Outputs a signal to the logic circuit. The logic circuits are AND circuits AND1 to ANDn-1 and OR circuits OR2 to ORn. For example, the output of the current bypass voltage detection circuit a1 is input to the AND circuit AND1, and the output of the current bypass voltage detection circuit a2 is input to the OR circuit OR2.

That is, in the battery pack abnormality detecting device according to the first embodiment, the AND circuits AND1 to ANDn-1 and the OR circuits OR2 to ORn are alternately connected to the current bypass voltage detecting circuits a1 to an. Note that here, a state in which a current is flowing is a state in which an H-level signal is being output, and a state in which no current is flowing is a state in which an L-level signal is being output.

The output from the charge / discharge control circuit 5 is input to the other input terminals of the AND circuits AND1 to ANDn-1 and the OR circuits OR2 to ORn. However, the signals input from the charge / discharge control circuit 5 to the AND circuits AND1 to ANDn-1 are input after the signal levels are inverted by the inverter circuits INV1 to INVn-1. The output terminals of the AND circuits AND1 to ANDn-1 and the OR circuits OR2 to ORn are connected to the gate terminals of the N-type MOS transistors Q1 to Qn. The drain terminals of the MOS transistors Q1 to Qn are connected to the resistors R1 to Rn.

電流 A current bypass circuit is constituted by the above-described current bypass voltage detection circuits a1 to an, a logic circuit, MOS transistors Q1 to Qn, and resistors R1 to Rn. As described above, when the current bypass voltage detection circuits a1 to an detect that the voltage between the terminals of the corresponding cells s1 to sn has risen above the first predetermined voltage V1 and is in a state close to full charge, the current bypass voltage detection circuits a1 to an A level signal is output, and MOS transistors Q1 to Qn are turned on via a logic circuit. When the MOS transistors Q1 to Qn are turned on, a part of the current flowing to the corresponding cells s1 to sn flows through the resistors R1 to Rn connected in series with the turned on MOS transistors Q1 to Qn. As a result, it is possible to suppress variation in capacitance between cells. The operation of the logic circuit will be described later.

The abnormality detection circuits b1 to bn are provided for each of the cells s1 to sn, and the terminal voltage (detection terminal voltage) of the corresponding cells s1 to sn is set to a second predetermined voltage V2 (overcharge determination threshold voltage). In addition to detecting that the battery voltage has risen to be overcharged, it also detects that the voltage between the terminals of the cell has dropped below a third predetermined voltage V3 (overdischarge determination threshold voltage) and has become overdischarged. When an overcharge state or an overdischarge state of the cell is detected, an abnormal detection signal (H level) is output to the OR circuit 4. When any one of the abnormality detection circuits b1 to bn outputs an abnormality detection signal, the OR circuit 4 outputs to the charge / discharge control circuit 5 a signal indicating that an abnormality has occurred in the cell. The magnitude relationship between the three predetermined voltages V1, V2, and V3 is set to V2> V1> V3.

The charge / discharge control circuit 5 controls the charge / discharge of the battery pack 1 based on the signal from the OR circuit 4. Further, the charge / discharge control circuit 5 outputs a failure diagnosis execution signal for performing a failure diagnosis of the abnormality detection circuits b1 to bn to the logic circuits AND1 to ANDn-1, OR2 to ORn. The timing of outputting the failure diagnosis execution signal is when the charge / discharge control circuit 5 is started (when the power is turned on) or when the battery pack 1 is suspended for a certain period of time.

{Operations of the AND circuits AND1 to ANDn-1 among the logic circuits will be described using the AND circuit AND1 as a representative. The AND circuit AND1 outputs the logical product of the output signal of the current bypass voltage detection circuit a1 and the signal obtained by inverting the failure diagnosis execution signal from the charge / discharge control circuit 5 by the inverter circuit INV1 to the gate terminal of the MOS transistor Q1. I do. When a failure diagnosis execution signal is not output from the charge / discharge control circuit 5, that is, when an L level signal is output from the charge / discharge control circuit 5, the AND circuit AND1 is connected to the H level via the inverter circuit INV1. Since the level signal is input, the output of the current bypass voltage detection circuit a1 becomes the output of the AND circuit AND1 as it is. Therefore, when an H level signal is output from the current bypass voltage detection circuit a1, the MOS transistor Q1 is turned on, and when an L level signal is output, the MOS transistor Q1 is turned off.

On the other hand, when the failure diagnosis execution signal is output from the charge / discharge control circuit 5, that is, when the H level signal is output, the AND circuit AND1 receives the L level signal via the inverter circuit INV1. Will be entered. Therefore, regardless of the level of the output signal of the current bypass voltage detection circuit a1, the output signal of the AND circuit AND1 goes low, and the MOS transistor Q1 is forcibly turned off.

Next, the operation of the OR circuits OR2 to ORn will be described using the OR circuit OR2 as a representative. The OR circuit OR2 outputs, to the gate terminal of the MOS transistor Q2, the logical sum of two signals of the output signal of the current bypass voltage detection circuit a2 and the failure diagnosis execution signal from the charge / discharge control circuit 5. When the failure diagnosis execution signal is not output from the charge / discharge control circuit 5, that is, when the L-level signal is output, the output of the current bypass voltage detection circuit a2 becomes the output of the OR circuit OR2 as it is. Therefore, when an H level signal is output from the current bypass voltage detection circuit a2, the MOS transistor Q2 is turned on, and when an L level signal is output, the MOS transistor Q2 is turned off.

On the other hand, when the failure diagnosis execution signal is output from the charge / discharge control circuit 5, that is, when the H level signal is output, regardless of the level of the output signal of the current bypass voltage detection circuit a2, the OR operation is performed. The output signal of the circuit OR2 also becomes H level. Therefore, a positive voltage is applied to the gate terminal of the MOS transistor Q2, and the MOS transistor Q2 is forcibly turned on.

Although the description is omitted, the operation of the AND circuits AND3, AND5, ANDn-1 corresponding to the cells s3, s5,..., Sn-1, and the OR circuits OR4, OR6, corresponding to the cells s4, s6,. The same applies to the operation of ORn. As described above, when the failure diagnosis execution signal is output from the charge / discharge control circuit 5, the MOS transistors connected to the AND circuits AND1 to ANDn-1 are forcibly turned off and connected to the OR circuits OR2 to ORn. The MOS transistor in question is forcibly turned on. Therefore, among the plurality of cells s1 to sn connected in series, every other cell, that is, between the detection terminals is short-circuited, and between the short-circuited detection terminals, the adjacent detection terminals are opened. .

Here, consider the case where the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken. It is assumed that the voltage between the terminals of the cells s2 and s3 immediately before the disconnection occurs is higher than the first predetermined voltage V1 and lower than the second predetermined voltage V2. Before the disconnection, the H level signals are output from the current bypass voltage detection circuits a2 and a3, so that the MOS transistors Q2 and Q3 are turned on, and bypass currents flow through the resistors R2 and R3, respectively. Since the cells s2 and s3 have not been overcharged, no abnormality detection signal (H level) is output from the abnormality detection circuits b2 and b3.

In this state, when the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken, the bypass current flowing for each of the cells s2 and s3 is changed in resistance from the positive terminal of the cell s3. It flows to the negative terminal of cell s2 via R3, MOS transistor Q3, resistor R2 and MOS transistor Q2. Normally, the resistance values of the resistors R1 to Rn are the same, and the ON resistances of the MOS transistors Q1 to Qn are also the same value. Therefore, the voltage of the detection terminal C2 is the sum of the voltages between the terminals of the cells s2 and s3. 1/2 of the value, that is, the average voltage.

Here, when a failure diagnosis execution signal (H level) is output from the charge / discharge control circuit 5, the MOS transistor Q2 connected to the OR circuit OR2 is forcibly turned on, and the MOS transistor Q2 connected to the AND circuit AND3 is turned on. Transistor Q3 is forcibly turned off. Therefore, the bypass current flowing from the positive terminal of the cell s3 to the negative terminal of the cell s2 stops flowing. In this state, the voltage of the detection terminal C2 becomes equal to the voltage of the negative terminal of the cell s2 via the MOS transistor Q2 and the resistor R2 which are turned on. It is detected that the voltage is lower than the third predetermined voltage V3. Further, since the added value of the voltage between the terminals of the cell s2 and the voltage between the terminals of the cell S3 is applied between the detection terminals C2 and C3, the abnormality detection circuit b3 operates at a voltage higher than the second predetermined voltage V2. Detect that there is.

That is, when the charge / discharge control circuit 5 outputs a failure diagnosis execution signal (H level), the abnormality detection circuit b2 outputs an abnormality signal (H level) indicating overdischarge, and the abnormality detection circuit b3 Outputs an abnormal signal (H level) indicating overcharging. As a result, an H-level signal, that is, a signal indicating that a disconnection has occurred, is input to the charge / discharge control circuit 5 via the OR circuit 4.

に つ い て The same applies to the case where a disconnection occurs between another cell and the detection terminal. For example, when the connection line between the positive terminal of the cell s1 (the negative terminal of the cell s2) and the detection terminal C1 is broken, when the charge / discharge control circuit 5 outputs a failure diagnosis execution signal, the MOS transistor Q1 is forcibly activated. And the MOS transistor Q2 is forcibly turned on. Accordingly, the voltage of the detection terminal C1 becomes equal to the voltage of the positive terminal of the cell s2 via the MOS transistor Q2 and the resistor R2 which are turned on, so that the abnormality detection circuit b2 detects the voltage between the detection terminals C1 and C2. It is detected that the voltage is lower than the third predetermined voltage V3. Further, since the added value of the voltage between the terminals of the cell s1 and the voltage between the terminals of the cell S2 is applied between the detection terminals C0 and C1, the abnormality detection circuit b1 operates at a voltage higher than the second predetermined voltage V2. Detect that there is. As a result, an H-level signal is input to the charge / discharge control circuit 5 via the OR circuit 4, so that the charge / discharge control circuit 5 can detect that a disconnection has occurred.

In the above description, the voltage between the terminals of the cells s2 and s3 immediately before the occurrence of the disconnection is higher than the first predetermined voltage V1 and lower than the second predetermined voltage V2. However, even when the voltage between the terminals of the cells s2 and s3 immediately before the occurrence of the disconnection is higher than the third predetermined voltage V3 and lower than the first predetermined voltage V1, the disconnection can be detected. In this case, the operation after the failure diagnosis execution signal is output from the charge / discharge control circuit 5 is the same, except that the current bypass function is not activated before the disconnection. However, when a signal indicating an abnormality (overcharge or overdischarge) of the cells s1 to sn is output from the abnormality detection circuits b1 to bn, it is not possible to determine the presence or absence of disconnection. No diagnosis shall be made.

FIG. 8 illustrates a configuration of a battery pack abnormality detection device that does not include a logic circuit or a signal line for outputting a failure diagnosis execution signal as provided in the battery pack abnormality detection device according to the first embodiment. FIG. The effects of the battery pack abnormality detection device according to the first embodiment will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted.

同 様 Similar to the above description, consider a case where the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken. It is assumed that the voltage between the terminals of the cells s2 and s3 immediately before the disconnection occurs is higher than the first predetermined voltage V1 and lower than the second predetermined voltage V2. Before the disconnection, the H level signals are output from the current bypass voltage detection circuits a2 and a3, so that the MOS transistors Q2 and Q3 are turned on, and bypass currents flow through the resistors R2 and R3, respectively. Since the cells s2 and s3 have not been overcharged, no abnormality detection signal (H level) is output from the abnormality detection circuits b2 and b3.

In this state, when the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken, the bypass current flowing for each of the cells s2 and s3 is changed in resistance from the positive terminal of the cell s3. It flows to the negative terminal of cell s2 via R3, MOS transistor Q3, resistor R2 and MOS transistor Q2. At this time, for the above-described reason, the voltage of the detection terminal C2 is １ ／ of the sum of the voltages between the terminals of the cells s2 and s3, that is, the average voltage. Since the voltage between the terminals of the cells s2 and s3 is higher than the first predetermined voltage V1 and lower than the second predetermined voltage V2, the average voltage is also higher than V1 and lower than V2. Accordingly, since no abnormality detection signal is output from the abnormality detection circuits b2 and b3, a disconnection cannot be detected.

According to the battery pack abnormality detecting device in the first embodiment, at the time of disconnection failure diagnosis, every other cell, that is, between the detection terminals, is connected to every other cell s1 to sn constituting the battery pack 1. By short-circuiting and opening, disconnection of the connection line between the cell and the corresponding detection terminal can be reliably detected based on the signals from the abnormality detection circuits b1 to bn. The circuit for short-circuiting between the detection terminals is constituted by logic circuits of AND circuits AND1 to ANDn-1, OR circuits OR2 to ORn and inverter circuits INV1 to INVn-1, and MOS transistors Q1 to Qn which are semiconductor switches. The disconnection between the cell and the corresponding detection terminal can be detected with a simple configuration without adding a large-scale circuit for detecting the disconnection.

Further, the short circuit constituted by the logic circuit and the semiconductor switch described above also functions as a current bypass circuit for bypassing a part of the current flowing to the corresponding cell when the voltage between the detection terminals becomes equal to or higher than the first predetermined voltage V1. Therefore, the disconnection can be detected with a simple configuration while providing the abnormality detection circuit for detecting the abnormality of the cell and the current bypass circuit. Further, at the time of disconnection failure diagnosis, by outputting one failure diagnosis execution signal from the charge / discharge control circuit 5, disconnection of all connection lines between the cell and the corresponding detection terminal can be detected.

-2nd Embodiment-
FIG. 2 is a diagram illustrating a configuration of the battery pack abnormality detection device according to the second embodiment. The same components as those of the battery pack abnormality detecting device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. In the battery pack abnormality detection device according to the second embodiment, the signal line from which the failure diagnosis execution signal is output from the charge / discharge control circuit 5 is double-tracked, and the logic circuit to which the failure diagnosis execution signal is input is: Further, a logic circuit has been added.

ロ ジ ッ ク The logic circuits newly added to the battery pack abnormality detecting device according to the first embodiment are OR circuits OR22 to OR2n-1. That is, OR circuits OR22 to OR2n-1 are added to OR circuits and AND circuits corresponding to cells s2 to sn-1 except for cells s1 and sn.

The failure diagnosis execution signal F1 output from the charge / discharge control circuit 5 is input to the inverter circuit INV1 corresponding to the cell s1, and is input to the OR circuit OR2 corresponding to the cell s2 via the OR circuit OR22. You. The failure diagnosis signal F2 is input to the OR circuit OR2 corresponding to the cell s2 via the OR circuit OR22, and is input to the inverter circuit INV3 corresponding to the cell s3 via the OR circuit OR23. . The same applies to the failure diagnosis signals F3 to Fn-2. The failure diagnosis signal Fn-1 is input to the inverter circuit INVn-1 corresponding to the cell sn-1 via the OR circuit OR2n-1 and to the OR circuit ORn corresponding to the cell sn.

(4) The failure diagnosis execution signal F1 is output when the disconnection of the connection line between the positive terminal of the cell s1 (the negative terminal of the cell s2) and the detection terminal C1 is detected. Further, the failure diagnosis execution signal F2 is output when the disconnection of the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is detected. The same applies to the failure diagnosis execution signals F3, F4,..., And the failure diagnosis signal Fn-1 is a signal of the connection line between the positive terminal of the cell sn-1 (the negative terminal of the cell sn) and the detection terminal Cn-1. Output when detecting disconnection.

Here, consider the case where the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken. As described in the first embodiment, the voltage between the terminals of the cells s2 and s3 immediately before disconnection occurs is higher than the first predetermined voltage V1 and lower than the second predetermined voltage V2. . The charge / discharge control circuit 5 outputs a failure diagnosis execution signal F2 (H level) in order to detect a disconnection at the above location.

(4) When the failure diagnosis execution signal F2 is output from the charge / discharge control circuit 5, the output of the OR circuit OR22 becomes H level, so that the output of the OR circuit OR2 also becomes H level, and the MOS transistor Q2 is forcibly turned on. Further, since the output of the OR circuit OR23 becomes H level, a signal of L level is inputted to the AND circuit AND3 via the inverter circuit INV3. Therefore, the output of the AND circuit AND3 goes low, and the MOS transistor Q3 is forcibly turned off.

As a result, similarly to the first embodiment, the bypass current flowing from the positive terminal of the cell s3 to the negative terminal of the cell s2 via the resistor R3, the MOS transistor Q3, the resistor R2, and the MOS transistor Q2 flows. Since the voltage disappears, the voltage of the detection terminal C2 becomes equal to the voltage of the negative terminal of the cell s2. Accordingly, the abnormality detection circuit b2 detects that the voltage between the detection terminals C1 and C2 is lower than the third predetermined voltage V3, and charges and discharges an abnormality detection signal (H level) indicating overdischarge. Output to the control circuit 5. Further, since the added value of the voltage between the terminals of the cell s2 and the voltage between the terminals of the cell S3 is applied between the detection terminals C2 and C3, the abnormality detection circuit b3 operates at a voltage higher than the second predetermined voltage V2. It detects that there is, and outputs an abnormality detection signal indicating overcharge to the charge / discharge control circuit 5.

In this case, an H-level signal is input to the charge / discharge control circuit 5 via the OR circuit 4. That is, the charge / discharge control circuit 5 outputs the failure diagnosis execution signal F2 and receives the H-level signal, whereby the connection between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is established. It is possible to detect that the wire is broken.

に つ い て The same applies to the case where disconnection between another cell and the detection terminal is detected. For example, when the disconnection of the connection line between the positive terminal of the cell s1 (the negative terminal of the cell s2) and the detection terminal C1 is detected, the failure diagnosis execution signal F1 is output from the charge / discharge control circuit 5. As a result, the MOS transistor Q1 is forcibly turned off and the MOS transistor Q2 is forcibly turned on. If the disconnection occurs at the above location, the voltage of the detection terminal C1 becomes equal to the voltage of the positive terminal of the cell s2. Therefore, the abnormality detection circuit b2 sets the voltage between the detection terminals C1 and C2 to the third predetermined value. Upon detecting that the voltage is lower than the voltage V3, the abnormality detection circuit b1 detects that the voltage is higher than the second predetermined voltage V2.

Also in this case, the charge / discharge control circuit 5 outputs the failure diagnosis execution signal F1 and then inputs the H-level signal via the OR circuit 4, thereby causing the positive terminal of the cell s1 (the negative terminal of the cell s2). It is possible to detect that the connection line between the detection terminal C1 and the detection terminal C1 is disconnected.

According to the battery pack abnormality detection device in the second embodiment, the charge / discharge control circuit 5 uses the failure diagnosis execution signals F1 to Fn-1 to connect every other cell, that is, between the detection terminals. Since the circuits to be short-circuited and opened are individually controlled, disconnection between the cell and the corresponding detection terminal can be detected, and the location of the disconnection can be easily specified.

-Third embodiment-
FIG. 3 is a diagram illustrating a configuration of a battery pack abnormality detection device according to the third embodiment. The same components as those of the battery pack abnormality detecting device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. In the battery pack abnormality detecting device according to the third embodiment, a current bypass circuit is formed by the resistors R1 to Rn and the Zener diodes D1 to Dn.

The Zener voltage VZ of the Zener diodes D1 to Dn is set to a fourth predetermined voltage V4 lower than the full charge voltage of the cells s1 to sn, and the magnitude of the second, third, and fourth predetermined voltages V2, V3, V4 is set. The relationship is V2> V4> V3. When the voltage between the terminals of the cells s1 to sn rises above the fourth predetermined voltage V4, current starts to flow through the Zener diodes D1 to Dn. That is, the bypass current flows through the resistors R1 to Rn connected in series with the Zener diodes D1 to Dn. The current bypass function operates in this way.

A series circuit of N-type MOS transistors Q12 to Q1n and resistors R12 to R1n is connected in parallel to cells located at even-numbered positions from the lowest, such as cells s2, s4, s6,..., Sn. ing. For example, a series circuit of a resistor R12 and a MOS transistor Q12 is connected in parallel with the cell s2. A failure diagnosis execution signal from the charge / discharge control circuit 5 is input to the gate terminal of the MOS transistor Q12. The source terminal of the MOS transistor Q12 is connected to the negative electrode of the corresponding cell s2, and the drain terminal is connected to the positive electrode of the cell s2 via a resistor R12.

When a failure diagnosis execution signal (H level) is output from the charge / discharge control circuit 5, the MOS transistors Q12 to Q1n are turned on, and every other cell s1 to sn constituting the battery pack 1 is connected to every other cell. That is, the detection terminals are short-circuited. On the other hand, when the failure diagnosis execution signal is not output (L level), the MOS transistors Q12 to Q1n are turned off. The resistances of the resistors R12 to R1n connected in series with the MOS transistors Q12 to Q1n are set to values sufficiently smaller than the resistances of the resistors R1 to Rn. Therefore, when the MOS transistors Q12 to Q1n are turned on while the current bypass function is operating, most of the bypass current flows to the resistors R12 to R1n connected in series with the turned on MOS transistors Q12 to Q1n.

Here, consider the case where the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken. It is assumed that the voltage between the terminals of the cells s2 and s3 immediately before the disconnection occurs is higher than the fourth predetermined voltage V4 and lower than the second predetermined voltage V2. Before the disconnection occurs, a current flows through the Zener diodes D2 and D3, thereby activating the current bypass function. However, since the cells s2 and s3 have not reached an overcharged state, no abnormality detection signals (H level) are output from the abnormality detection circuits b2 and b3.

In this state, when the connection line between the positive terminal of the cell s2 (negative terminal of the cell s3) and the detection terminal C2 is broken, the bypass current flowing for each of the cells s2 and s3 becomes a resistance from the positive terminal of the cell s3. It flows to the negative terminal of the cell s2 via R3, Zener diode D3, resistor R2 and Zener diode D2. Since the resistance values of the resistors R1 to Rn are the same and the Zener voltages of the Zener diodes D1 to Dn are also the same value, the voltage of the detection terminal C2 is the sum of the voltages of the terminals of the cells s2 and s3. 1/2, that is, the average voltage.

Here, when a failure diagnosis execution signal (H level) is output from the charge / discharge control circuit 5, the MOS transistor Q12 is turned on, and the bypass current flowing through the resistor R2 and the Zener diode D2 becomes equal to the resistance R12. It also branches and starts flowing to the series circuit composed of the MOS transistor Q12. As described above, since the resistance value of the resistor R12 is set to a value sufficiently smaller than the resistance value of the resistor R2 (R3), most of the bypass current flows to the series circuit of the resistor R12 and the MOS transistor Q12. Therefore, the voltage of the detection terminal C2 is very close to the voltage of the negative terminal of the cell s2. As a result, the abnormality detection circuit b2 detects that the voltage between the detection terminals C1 and C2 is lower than the third predetermined voltage V3, and the abnormality detection circuit b3 determines that the voltage between the detection terminals C2 and C3 is lower than the third predetermined voltage V3. 2 is higher than the predetermined voltage V2.

As described above, the abnormality detection circuit b2 outputs an abnormality detection signal (H level) indicating overdischarge, and the abnormality detection circuit b3 outputs an abnormality detection signal (H level) indicating overcharge. Therefore, an H-level signal is input to the charge / discharge control circuit 5 via the OR circuit 4.

に つ い て The same applies to the case where a disconnection occurs between another cell and the detection terminal. For example, a case where the connection line between the positive terminal of the cell s3 (the negative terminal of the cell s4) and the detection terminal C3 is broken will be described. The voltage between the terminals of the cells s3 and s4 immediately before the disconnection occurs is higher than the fourth predetermined voltage V4 and lower than the second predetermined voltage V2. In this case, since current flows through the Zener diodes D3 and D4, the current bypass function operates. However, since the cells s3 and s4 have not reached the overcharged state, no abnormality detection signal (H level) is output from the abnormality detection circuits b3 and b4.

In this state, when the connection line between the positive terminal of the cell s3 (the negative terminal of the cell s4) and the detection terminal C3 is broken, the bypass current flowing for each of the cells s3 and s4 becomes a resistance from the positive terminal of the cell s4. It flows to the negative terminal of the cell s3 via R4, Zener diode D4, resistor R3 and Zener diode D3. Therefore, for the above-described reason, the voltage of the detection terminal C3 is 1/2 of the sum of the voltages between the terminals of the cells s3 and s4, that is, the average voltage.

Here, when a failure diagnosis execution signal (H level) is output from the charge / discharge control circuit 5, the MOS transistor Q14 is turned on, and the bypass current flowing through the resistor R4 and the Zener diode D4 becomes equal to the resistance R14. It also branches and starts flowing to the series circuit composed of the MOS transistor Q14. In this case, as described above, the voltage at the detection terminal C3 is very close to the voltage at the positive terminal of the cell s4 due to the magnitude relationship between the resistors R4 (R3) and R14. As a result, the abnormality detection circuit b3 detects that the voltage between the detection terminals C2 and C3 is higher than the second predetermined voltage V2, and the abnormality detection circuit b4 determines that the voltage between the detection terminals C3 and C4 is higher than the second predetermined voltage V2. 3 is lower than the predetermined voltage V3. Therefore, an H-level signal is input to the charge / discharge control circuit 5 via the OR circuit 4. As described above, the charge / discharge control circuit 5 can detect that the disconnection has occurred by inputting the H-level signal after outputting the failure diagnosis execution signal.

FIG. 9 shows a configuration of a battery pack abnormality detection device that does not include a MOS transistor or a signal line for outputting a failure diagnosis execution signal as provided in the battery pack abnormality detection device according to the third embodiment. FIG. The effect of the battery pack abnormality detecting device according to the third embodiment will be described with reference to FIG. The same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.

{Similar to the above description, consider a case where the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken. It is assumed that the voltage between the terminals of the cells s2 and s3 immediately before the disconnection occurs is higher than the fourth predetermined voltage V4 and lower than the second predetermined voltage V2. In this case, although a bypass current flows through the Zener diodes D3 and D4, since the cells s2 and s3 have not been overcharged, no abnormality detection signal (H level) is output from the abnormality detection circuits b2 and b3.

In this state, when the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken, the bypass current flowing for each of the cells s2 and s3 is changed in resistance from the positive terminal of the cell s3. It flows to the negative terminal of the cell s2 via R3, Zener diode D3, resistor R2 and Zener diode D2. Therefore, for the above-described reason, the voltage of the detection terminal C2 is 1/2 of the sum of the voltages between the terminals of the cells s2 and s3, that is, the average voltage. Since the voltage between the terminals of the cells s2 and s3 is higher than V4 and lower than V2, the average voltage is also higher than V4 and lower than V2. Therefore, since no abnormality detection signal is output from the abnormality detection circuits b2 and b3, the disconnection cannot be detected.

According to the battery pack abnormality detecting device of the third embodiment, even when the Zener diodes D1 to Dn, which are semiconductor switches, are used as the current bypass circuit, the connection between the cells s1 to sn and the detection terminals C1 to Cn is possible. It can be reliably detected that a disconnection has occurred in the connection line. That is, when a voltage between the detection terminals becomes equal to or higher than a predetermined voltage, a semiconductor switch connected between the detection terminals is turned on, and a circuit including a current bypass circuit for partially bypassing a current flowing to a corresponding cell is provided. Disconnection of the connection line between the cell and the corresponding detection terminal can be reliably detected based on a signal output from the abnormality detection circuit when the semiconductor switch is forcibly turned on and off alternately. Therefore, there is no need to add a large-scale disconnection detecting circuit for detecting disconnection.

(4) At the time of disconnection failure diagnosis, by outputting one failure diagnosis execution signal from the charge / discharge control circuit 5, disconnection of all connection lines between the cell and the corresponding detection terminal can be detected.

-Fourth embodiment-
FIG. 4 is a diagram illustrating a configuration of a battery pack abnormality detection device according to the fourth embodiment. The same components as those of the battery pack abnormality detecting device according to the third embodiment shown in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. In the abnormality detection device for a battery pack according to the fourth embodiment, the signal line from which the failure diagnosis execution signal is output from the charge / discharge control circuit 5 is double-tracked.

The failure diagnosis execution signal F2 is transmitted between the connection line between the positive terminal of the cell s1 (the negative terminal of the cell s2) and the detection terminal C1, and the connection between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2. The signal is output when the disconnection of the connection line between the terminals is detected, and is input to the gate terminal of the MOS transistor Q12. The failure diagnosis execution signal F4 is transmitted between the connection line between the positive terminal of the cell s3 (the negative terminal of the cell s4) and the detection terminal C3, and between the positive terminal of the cell s4 (the negative terminal of the cell s5) and the detection terminal C4. The signal is output when the disconnection of the connection line is detected, and is input to the gate terminal of the MOS transistor Q14. The same applies to the failure diagnosis execution signals F6, F8,..., And the failure diagnosis signal Fn is a connection line between the positive terminal of the cell sn-2 (the negative terminal of the cell sn-1) and the detection terminal Cn-1, The signal is output when the disconnection of the connection line between the positive terminal of the cell sn-1 (the negative terminal of the cell sn) and the detection terminal Cn is detected, and is input to the gate terminal of the MOS transistor Q1n.

Here, consider a case where the connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 is broken. The operation immediately before the disconnection occurs is the same as that of the third embodiment, and the description is omitted. When the failure diagnosis execution signal F2 (H level) is output from the charge / discharge control circuit 5, the MOS transistor Q12 is turned on, and the bypass current flowing through the resistor R2 and the Zener diode D2 is reduced by the resistor R12 and the MOS transistor. It also branches and starts flowing to the series circuit composed of Q12. For the above-described reason, the voltage of the detection terminal C2 is very close to the voltage of the negative terminal of the cell s2. Therefore, the abnormality detection circuit b2 sets the voltage between the detection terminals C1 and C2 lower than the third predetermined voltage V3. When the voltage is detected, the abnormality detection circuit b3 detects that the voltage between the detection terminals C2 and C3 is higher than the second predetermined voltage V2.

As described above, the abnormality detection circuit b2 outputs an abnormality detection signal (H level) indicating overdischarge, and the abnormality detection circuit b3 outputs an abnormality detection signal (H level) indicating overcharge. Therefore, an H-level signal is input to the charge / discharge control circuit 5 via the OR circuit 4. The charge / discharge control circuit 5 outputs a connection line between the positive terminal of the cell s2 (the negative terminal of the cell s3) and the detection terminal C2 because the H-level signal is input after outputting the failure diagnosis execution signal F2. Alternatively, it is possible to detect that one of the connection lines between the positive terminal of the cell s1 (the negative terminal of the cell s2) and the detection terminal C1 is broken.

に つ い て The same applies to the case where a disconnection occurs between another cell and the detection terminal. For example, when the disconnection of the connection line between the positive terminal of the cell s3 (the negative terminal of the cell s4) and the detection terminal C3 is detected, the charge / discharge control circuit 5 outputs a failure diagnosis execution signal F4. Note that the operation in the case where a disconnection occurs in the connection line between the positive terminal of the cell s3 (the negative terminal of the cell s4) and the detection terminal C3 has been described in the third embodiment. The description is omitted.

According to the battery pack abnormality detection device of the fourth embodiment, when the Zener diodes D1 to Dn are used as the current bypass circuits, the disconnection of the connection line between the cells s1 to sn and the detection terminals C1 to Cn is performed. In addition to being able to detect, it is possible to specify the disconnection point. That is, since the charge / discharge control circuit 5 individually controls the MOS transistors Q12 to Q1n using the failure diagnosis execution signals F2, F4,..., Fn, the disconnection point between the cell and the corresponding detection terminal can be easily specified. can do.

-Fifth embodiment-
FIG. 5 is a diagram illustrating a configuration of a battery pack abnormality detection device according to the fifth embodiment. The same components as those of the battery pack abnormality detecting device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

The battery pack abnormality detecting device according to the fifth embodiment has a diagnostic signal dividing circuit 6 and OR circuits OR1, OR3 in addition to the configuration of the battery pack abnormality detecting device according to the first embodiment shown in FIG. , ..., ORn-1, AND circuits AND2, AND4, ..., ANDn, inverter circuits INV2, INV4, ..., INVn, and two for transmitting failure diagnosis execution signals Chk-A and Chk-B to be described later. Signal lines.

ORn-1 are provided corresponding to AND circuits AND1, AND3,..., ANDn-1 provided every other cell s1 to sn-1. The OR circuits OR1, OR3,..., ORn-1 respectively output the output signals of the corresponding current bypass voltage detecting circuits a1, a3,. A logical sum with A is calculated, and the calculation result is output to the corresponding AND circuits AND1, AND3,..., ANDn-1.

, ANDn and the inverter circuits INV2, INV4,... INVn correspond to OR circuits OR2, OR4,..., ORn provided every other cell s2 to sn. Is provided. , ANDn respectively output the output signals of the corresponding current bypass voltage detection circuits a2, a4,..., An and the diagnostic signal Chk-A output from the diagnostic signal dividing circuit 6, which will be described later, to an inverter circuit. Calculates the logical product of the signals inverted by INV2, INV4,..., INVn, and outputs the operation result to the corresponding OR circuit OR2, OR4,.

The diagnostic signal dividing circuit 6 divides the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5 into two failure diagnosis execution signals Chk-A and Chk-B and outputs the divided signals. The failure diagnosis execution signal Chk-A is input to AND circuits AND2, AND4,..., ANDn via inverter circuits INV2, INV4,... INVn, and also to OR circuits OR1, OR3,. You. The failure diagnosis execution signal Chk-B is input to the inverter circuits INV1, INV3,..., INVn-1 and the OR circuits OR2, OR4,.

FIG. 6 is a diagram showing the output timing of the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5 and the output timing of the failure diagnosis execution signals Chk-A and Chk-B output from the diagnostic signal dividing circuit 6. It is. As shown in FIG. 6, the pulses (H level) of the failure diagnosis execution signals Chk-A and Chk-B are output alternately. For example, the odd-numbered pulse (H level) of the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5 is output from the diagnosis signal division circuit 6 as a pulse (H level) of the failure diagnosis execution signal Chk-A. The even-numbered pulse of the failure diagnosis execution signal Chk is output from the diagnosis signal dividing circuit 6 as a pulse (H level) of the failure diagnosis execution signal Chk-B.

<Operation of logic circuit provided corresponding to cell positioned at odd-numbered stage>
Among the logic circuits, the operation of the logic circuits provided corresponding to the cells s1, s3,..., Sn-1 located at the odd-numbered stages of the battery pack 1 will be described using the cell s1 as an example.

~ (Chk-A, Chk-B) = (L, L) ~
When the failure diagnosis execution signal Chk is not output from the charge / discharge control circuit 5, that is, when both the failure diagnosis execution signals Chk-A and Chk-B output from the diagnosis signal dividing circuit 6 are at the L level, An L-level signal is input to the OR circuit OR1, and an H-level signal is input to the AND circuit AND1 via the inverter circuit INV1. In this case, the output of the current bypass voltage detection circuit a1 becomes the output of the OR circuit OR1 and the AND circuit AND1 as it is. Therefore, when an H-level signal is output from the current bypass voltage detection circuit a1, the N-type MOS transistor Q1 turns on, and when an L-level signal is output, the MOS transistor Q1 turns off.

~ (Chk-A, Chk-B) = (H, L) ~
When the odd-numbered pulse of the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, that is, when the failure diagnosis execution signal Chk-A output from the diagnosis signal division circuit 6 is at the H level, the failure diagnosis execution signal The case where Chk-B is at the L level will be described. In this case, an H-level signal is input to the OR circuit OR1, and an H-level signal is input to the AND circuit AND1 via the inverter circuit INV1. Accordingly, regardless of the level of the output signal of the current bypass voltage detection circuit a1, the output of the OR circuit OR1 and the output signal of the AND circuit AND1 become H level, and the MOS transistor Q1 is forcibly turned on.

~ (Chk-A, Chk-B) = (L, H) ~
When the even-numbered pulse of the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, that is, when the failure diagnosis execution signal Chk-A output from the diagnosis signal division circuit 6 is at L level, the failure diagnosis execution signal The case where Chk-B is at the H level will be described. In this case, an L-level signal is input to the AND circuit AND1 via the inverter circuit INV1, so that the output signal of the AND circuit AND1 is low regardless of the level of the output signal of the current bypass voltage detection circuit a1. Become. Therefore, the MOS transistor Q1 is forcibly turned off.

<Operation of logic circuit provided corresponding to cell positioned at even-numbered stage>
Next, the operation of the logic circuits provided corresponding to the cells s2, s4,..., Sn located at the even-numbered stages of the battery pack 1 will be described using the cell s2 as an example.

~ (Chk-A, Chk-B) = (L, L) ~
When the failure diagnosis execution signal Chk is not output from the charge / discharge control circuit 5, that is, when both the failure diagnosis execution signals Chk-A and Chk-B output from the diagnosis signal dividing circuit 6 are at the L level, An L-level signal is input to the OR circuit OR2, and an H-level signal is input to the AND circuit AND2 via the inverter circuit INV2. In this case, the output of the current bypass voltage detection circuit a2 becomes the output of the AND circuit AND2 and the OR circuit OR2 without change. Therefore, when an H-level signal is output from the current bypass voltage detection circuit a2, the N-type MOS transistor Q2 is turned on, and when an L-level signal is output, the MOS transistor Q2 is turned off.

~ (Chk-A, Chk-B) = (H, L) ~
When the odd-numbered pulse of the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, that is, when the failure diagnosis execution signal Chk-A output from the diagnosis signal division circuit 6 is at the H level, the failure diagnosis execution signal The case where Chk-B is at the L level will be described. In this case, an L-level signal is input to the AND circuit AND2 via the inverter circuit INV2, and an L-level signal is input to the OR circuit OR2. Therefore, regardless of the level of the output signal of the current bypass voltage detection circuit a2, the output signals of the AND circuit AND2 and the OR circuit OR2 become L level, and the MOS transistor Q2 is forcibly turned off.

~ (Chk-A, Chk-B) = (L, H) ~
When the even-numbered pulse of the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, that is, when the failure diagnosis execution signal Chk-A output from the diagnosis signal division circuit 6 is at L level, the failure diagnosis execution signal The case where Chk-B is at the H level will be described. In this case, an H-level signal is input to the AND circuit AND2 via the inverter circuit INV2, and an H-level signal is input to the OR circuit OR2. Therefore, regardless of the level of the output signal of the current bypass voltage detection circuit a2, the output signal of the OR circuit OR2 becomes H level, and the MOS transistor Q2 is forcibly turned on.

Although the description is omitted, the operation of the logic circuit corresponding to the other cells s3, s5,..., Sn-1 located at the odd-numbered stages and the other cells s4, s6,. The same applies to the operation of the logic circuit corresponding to. Therefore, when the odd-numbered pulse of the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, the MOS transistors provided corresponding to the cells s1, s3,. Are forcibly turned on, and the MOS transistors provided corresponding to the cells s2, s4,..., Sn located at the even-numbered stages are forcibly turned off.

When the even-numbered pulse of the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, the MOS transistors provided corresponding to the cells s1, s3,. Are forcibly turned off, and the MOS transistors provided corresponding to the cells s2, s4,..., Sn located at the even-numbered stages are forcibly turned on.

Therefore, when the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, every other cell among the plurality of cells s1 to sn connected in series, that is, the detection terminals are short-circuited. The adjacent detection terminals are opened between the short-circuited detection terminals. Thus, similarly to the abnormality detection device for a battery pack according to the first embodiment, it is possible to detect a disconnection of a connection line between a cell and a corresponding detection terminal.

In the battery pack abnormality detection device according to the first embodiment, when the charge / discharge control circuit 5 outputs a failure diagnosis execution signal at the H level, the MOS transistors Q1, Q3,. Qn-1 is turned off, and the MOS transistors Q2, Q4,..., Qn located at the even-numbered stages are turned on. Therefore, when the disconnection diagnosis of the connection line is performed, since the power of the cells s2, s4,..., Sn in which the current bypass circuit operates is consumed, the cells s1, s3,. There will be a voltage (capacity) difference between -1.

On the other hand, in the battery pack abnormality detection device according to the fifth embodiment, the MOS transistor to be turned on / off is switched for each pulse of the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5. That is, each time the disconnection detection process is performed, the detection terminals connected to both terminals of the plurality of cells s1 to sn are alternately short-circuited / opened (switching between short-circuiting / opening). Even when the operation is performed, there is no difference in voltage (capacity) between the cells s1 to sn constituting the assembled battery 1.

-Sixth embodiment-
FIG. 7 is a diagram illustrating a configuration of a battery pack abnormality detection device according to the sixth embodiment. The same components as those of the battery pack abnormality detecting device according to the third embodiment shown in FIG. 3 and the battery pack abnormality detecting device according to the fifth embodiment shown in FIG. 5 are denoted by the same reference numerals. The description is omitted.

The battery pack abnormality detecting device according to the sixth embodiment has a diagnostic signal dividing circuit 6 and resistors R11, R13, R13, and R3 in addition to the configuration of the battery pack abnormality detecting device according to the third embodiment shown in FIG. , R1n-1, N-type MOS transistors Q11, Q13,..., Q1n-1, and two signal lines for transmitting failure diagnosis execution signals Chk-A and Chk-B.

直列 The series circuit of the resistor R11 and the MOS transistor Q11 is connected in parallel with the cell s1. Similarly, a series circuit of the resistor R13 and the MOS transistor Q13 is connected in parallel with the cell s3, and a series circuit of the resistor R1n-1 and the MOS transistor Q1n-1 is connected in parallel with the cell sn-1. .

Similarly to the battery pack abnormality detection device according to the fifth embodiment, the diagnostic signal dividing circuit 6 converts the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5 into two failure diagnosis execution signals Chk-A and Chk. Divide into -B. The failure diagnosis execution signal Chk-A is supplied to the gates of the MOS transistors Q1, Q3,..., Q1n-1 provided corresponding to the cells s1, s3,. Input to the terminal. The failure diagnosis execution signal Chk-B is connected to the gate terminals of the MOS transistors Q2, Q4,..., Qn provided corresponding to the cells s2, s4,. Will be entered.

The output timing of the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5 and the output timing of the failure diagnosis execution signals Chk-A and Chk-B output from the diagnosis signal dividing circuit 6 are the same as those in the fifth embodiment. FIG. 6 shows the same as the embodiment. That is, the odd-numbered pulse of the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5 is output from the diagnosis signal division circuit 6 as a pulse of the failure diagnosis execution signal Chk-A, and the even-numbered pulse of the failure diagnosis execution signal Chk is output. The third pulse is output from the diagnostic signal dividing circuit 6 as a pulse of the failure diagnosis execution signal Chk-B.

In the battery pack abnormality detecting device according to the sixth embodiment, when the failure diagnosis execution signal Chk outputs the odd-numbered pulse (H level), the cells s1, s3,. , Q1n-1 provided in correspondence with the above-mentioned are turned on, and the MOS transistors Q2, Q4,. When the even-numbered pulse of the failure diagnosis execution signal Chk is output, the MOS transistors Q2, Q4,..., Qn provided corresponding to the cells s2, s4,. , Q1n-1 are turned off, and the MOS transistors Q1, Q3,.

Therefore, when the failure diagnosis execution signal Chk is output from the charge / discharge control circuit 5, every other cell among the plurality of cells s1 to sn connected in series, that is, the detection terminals are short-circuited. The adjacent detection terminals are opened between the short-circuited detection terminals. This makes it possible to detect a disconnection of a connection line between a cell and a corresponding detection terminal, similarly to the abnormality detection device for a battery pack according to the third embodiment.

(4) Similarly to the abnormality detection device for a battery pack according to the fifth embodiment, the MOS transistor to be turned on / off is switched for each pulse of the failure diagnosis execution signal Chk output from the charge / discharge control circuit 5. That is, each time the disconnection detection process is performed, the detection terminals connected to both terminals of the plurality of cells s1 to sn are alternately short-circuited / opened (switching between short-circuiting / opening). Even when the operation is performed, there is no voltage (capacity) difference between the cells s1 to sn constituting the assembled battery 1.

That is, in the battery pack abnormality detection device according to the third embodiment, when the charge / discharge control circuit 5 outputs the H-level failure diagnosis execution signal, the MOS provided in each even-numbered cell is always provided. Since the transistors Q12, Q14,..., Q1n are turned on and the power of the cells s2, s4,..., Sn is consumed, the voltage (capacity) difference between the cells s1, s3,. Will occur. However, according to the battery pack abnormality detecting device of the sixth embodiment, the MOS transistor is provided for every cell, and the MOS transistor to be turned on / off is replaced at the time of failure diagnosis, so that the power of a specific cell is reduced. Can be prevented from being consumed.

The present invention is not limited to the above embodiments. For example, in the battery pack abnormality detecting device according to the first embodiment, a MOS transistor is used as a semiconductor switch constituting a current bypass circuit, but a bipolar transistor may be used.

The circuit for short-circuiting between the detection terminals connected to both terminals of each of the cells s1 to sn and the circuit for opening the circuit are also provided in the abnormality detection device for the assembled battery in the first to sixth embodiments described above. The present invention is not limited to the configurations of the short circuit and the open circuit used in the above.

The correspondence between the components of the claims and the components of the first and second embodiments is as follows. That is, detection terminals C1 to Cn are detection terminals, abnormality detection circuits b1 to bn are abnormality detection circuits, OR circuits OR2 to ORn, MOS transistors Q2, Q4,..., Qn are short-circuit circuits, and MOS transistors Q1 to Qn are The semiconductor switch, the charge / discharge control circuit 5 is a control circuit, the OR circuit 4 and the charge / discharge control circuit 5 are disconnection detection circuits, AND circuits AND1 to ANDn-1, inverter circuits INV1 to INVn-1, and MOS transistors Q1 and Q3. ,..., Qn-1 each constitute an open circuit.

Regarding the correspondence with the components of the third and fourth embodiments, the Zener diodes D1 to Dn and the resistors R1 to Rn control the current bypass circuit, and the charge / discharge control circuit 5 and the MOS transistors Q12 to Q1n control the current bypass circuit. Configure each circuit. Further, regarding the correspondence with the components of the fifth and sixth embodiments, the MOS transistors Q1, Q3,..., Qn-1, the resistors R1,. 1, inverter circuits INV1, ..., INVn-1, OR circuits OR1, ..., ORn-1, MOS transistors Q2, Q4, ..., Qn, resistors R2, ..., Rn, AND circuits AND2, ..., ANDn, OR , ORn and the inverter circuits INV2,..., INVn form a short circuit / open circuit. Note that each component is not limited to the above configuration as long as the characteristic functions of the present invention are not impaired.

FIG. 2 is a diagram illustrating a configuration of a battery pack abnormality detection device according to the first embodiment. FIG. 6 is a diagram illustrating a configuration of a battery pack abnormality detection device according to a second embodiment. The figure which shows the structure of the abnormality detection apparatus of a battery pack in 3rd Embodiment. The figure which shows the structure of the abnormality detection apparatus of a battery pack in 4th Embodiment. The figure which shows the structure of the abnormality detection apparatus of the assembled battery in 5th Embodiment. The figure which shows the output timing of the failure diagnosis execution signal Chk output from a charge / discharge control circuit, and the output timing of the failure diagnosis execution signals Chk-A and Chk-B output from a diagnostic signal division circuit. The figure which shows the structure of the abnormality detection apparatus of a battery pack in 6th Embodiment. FIG. 2 is a configuration diagram of an assembled battery abnormality detection device for describing the effect of the assembled battery abnormality detection device according to the first embodiment. Configuration diagram of an assembled battery abnormality detection device for describing the effect of the assembled battery abnormality detection device according to the third embodiment.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... assembled battery, 4 ... OR circuit, 5 ... charge / discharge control circuit, 6 ... diagnostic signal division circuit, s1-sn ... cell, a1-an ... current bypass voltage detection circuit, b1-bn ... abnormality detection circuit, AND1- ANDn: AND circuit, OR1 to ORn, OR22 to OR2n-1: OR circuit, R1 to Rn, R11 to R1n: resistor, Q1 to Qn, Q11 to Q1n: N-type MOS transistor, C1 to Cn: detection terminal, INV1 to INVn: Inverter circuit, D1 to Dn: Zener diode

Claims (10)

In a battery pack abnormality detection device configured by connecting a plurality of rechargeable cells in series,
A detection terminal connected to both terminals of the plurality of cells,
An abnormality detection circuit that is provided for each of the plurality of cells and detects abnormality of a corresponding cell based on a voltage between the detection terminals,
A plurality of short-circuits for short-circuiting the detection terminals corresponding to the plurality of cells every other one,
A control circuit for operating the short circuit;
A disconnection detection circuit that detects disconnection of a connection line between the cell and a corresponding detection terminal based on a signal output from the abnormality detection circuit when the control circuit activates the short circuit. An abnormality detection device for a battery pack, comprising: The abnormality detection device for an assembled battery according to claim 1,
The abnormality detecting device for a battery pack, wherein the short circuit includes a semiconductor switch, and the detection terminals are short-circuited by turning on / off the semiconductor switch. The abnormality detecting device for a battery pack according to claim 1 or 2,
The abnormality detection device for a battery pack, wherein the control circuit individually controls the short circuit to be operated. The abnormality detecting device for a battery pack according to claim 1 or 2,
An abnormality detection device for a battery pack, wherein the control circuit controls all of the short circuits at the same time. The apparatus for detecting abnormality of a battery pack according to any one of claims 1 to 4,
The abnormality detection device for a battery pack, wherein the short circuit also functions as a current bypass circuit that bypasses a part of a current flowing to a corresponding cell when a voltage between the detection terminals becomes equal to or higher than a first predetermined voltage. . The battery pack abnormality detection device according to any one of claims 1 to 5,
The abnormality detection circuit detects an overcharged state of a corresponding cell by comparing a voltage between the detection terminals with a second predetermined voltage, and determines a voltage between the detection terminals and a third predetermined voltage. By detecting the over-discharge state of the corresponding cell by comparing,
The disconnection detection circuit, when the control circuit operates the short circuit, when the abnormality detection circuit outputs a signal indicating an overcharge state or an overdischarge state of the corresponding cell, the disconnection occurs An abnormality detection device for a battery pack, characterized in that it is determined that the battery pack is present. The abnormality detection device for a battery pack according to any one of claims 1 to 6,
A plurality of open circuits that open between the detection terminals short-circuited by the short-circuit and between adjacent detection terminals are further provided,
The control circuit activates the open circuit simultaneously when activating the short circuit,
The disconnection detection circuit disconnects a connection line between the cell and a corresponding detection terminal based on a signal output from the abnormality detection circuit when the control circuit operates the short circuit and the open circuit. An abnormality detection device for a battery pack, which detects the presence or absence of a battery. The apparatus for detecting abnormality of a battery pack according to any one of claims 1 to 4,
A current that is provided for each of the plurality of cells and that turns on a semiconductor switch connected between the detection terminals when a voltage between the detection terminals becomes equal to or higher than a predetermined voltage, thereby bypassing a part of a current flowing to a corresponding cell. An abnormality detection device for a battery pack, further comprising a bypass circuit. The abnormality detection device for a battery pack according to claim 7,
The short-circuit and the open circuit are a short-circuit / open circuit that can short-circuit and open the detection terminals corresponding to the plurality of cells, respectively,
The disconnection detection circuit outputs an output from the abnormality detection circuit when the control circuit short-circuits the plurality of short-circuit / open circuits alternately and opens a short-circuit / open circuit adjacent to the short-circuit / open circuit to be short-circuited. An abnormality detection device for an assembled battery, wherein a disconnection of a connection line between the cell and a corresponding detection terminal is detected based on a received signal. The abnormality detection device for a battery pack according to claim 9,
An abnormality detection device for a battery pack, wherein the control circuit alternately short-circuits and opens each of the plurality of short-circuit / open circuits each time the disconnection detection processing is performed.

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