JP2004103949A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be miniaturized and to provide a manufacturing method thereof. <P>SOLUTION: In a wafer 1, a plurality of chip regions 3a divided by a cut line 2 are disposed on a substrate 11. On a lower surface of a substrate 11, a cavity 12 is provided over adjacent two chip regions, and the cavity 12 is filled with resin. When a chip is formed by cutting the wafer 1 along the cut line 2, the cavity 12 is divided into a plurality of chips. Thereby, a chip area can be reduced. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, communication devices such as mobile phones have been required to have a smaller wireless portion. The part that handles high-frequency signals in the wireless part is composed of passive components in addition to ordinary semiconductor components. The passive components refer to filters, baluns, chip capacitors, chip inductors, chip resistors, and the like, and it is difficult to form them on a semiconductor substrate. In recent years, miniaturization has been realized by forming a module in which a part of these passive elements is embedded between layers of a multilayer ceramic substrate or a multilayer resin substrate.
[0003]
Hereinafter, the structure of a conventional semiconductor device will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a structure proposed in Patent Literature 1 among conventional chip structures of a semiconductor device. In this structure, a module is configured by combining a semiconductor component and a small chip component.
[0004]
As shown in FIG. 7, a chip 50 of a conventional semiconductor device includes a substrate 41 having a cavity 41a on the lower surface (back surface) side, a wiring 42a provided on an upper surface (main surface) of the substrate 41, A chip component 48 provided on the upper surface and electrically connected to the wiring 42a; a wiring 42b fixedly provided on the lower surface of a portion of the substrate 41 serving as the bottom of the cavity 41a; A semiconductor chip 45 provided on the lower surface of the bottom portion of the cavity 41a and electrically connected to the wiring 42b by the wire bond 46, and penetrates the bottom portion of the cavity 41a of the substrate 41 to form the wiring 42a An inner via hole 49 for electrically connecting the substrate 41 to the wiring 42b; an electrode 43 provided on the lower surface of a portion of the substrate 41 which will be a side portion of the cavity 41a; 41, an end face through-hole electrode 44 provided to penetrate a portion to be a side portion of the cavity 41a to establish electrical connection between the wiring 42a, the wiring 42b and the electrode 43, and a resin 47 filling the cavity 41a. Have been.
[0005]
The chip component 48 specifically refers to a semiconductor element, a capacitance element, an inductor element, a resistance element, and the like. The chip component 48 is soldered on the upper surface of the substrate 41.
[0006]
Here, a process of dividing the wafer to obtain chips as shown in FIG. 7 will be described with reference to FIGS. FIG. 8 is a diagram showing an upper surface of a wafer on which a plurality of chip regions are arranged, and FIG. 9 is a perspective view showing a structure of a chip obtained by cutting the wafer.
[0007]
In a wafer 51 as shown in FIG. 8, a plurality of chip regions 50 a partitioned by a cutting line 53 are arranged on a substrate 41. Further, a through hole 52 a penetrating through the substrate 41 is formed along the cutting line 53. At this time, cavities and elements as shown in FIG. 7 have already been formed in the substrate 41, but these are not shown.
[0008]
By cutting the wafer 51 by a method such as dicing, a chip 50 as shown in FIG. 9 is obtained. In the side wall of the chip 50, a through hole 52a is divided to form a concave portion 52. The chip 50 is composed of a plurality of layers, and the wiring 42 is formed on the surface of each layer. The wiring 42 is provided so as to avoid a region where the inner via hole 49 is arranged.
[0009]
As another technique related to the present invention, there is a technique proposed in Patent Document 2. Patent Document 2 discloses a structure in which a semiconductor chip 45 and a substrate 41 are connected by flip chips instead of being connected by wire bonds 46 in the configuration shown in FIG. With this structure, it is possible to further reduce the thickness.
[0010]
[Patent Document 1]
Japanese Patent No. 2689956 [Patent Document 2]
Japanese Patent No. 3061014
[Problems to be solved by the invention]
However, in the above-described structure, there is a limit in reducing the size of the element.
[0012]
In the semiconductor device as described above, when forming the through-hole electrode 44 on the side surface of the substrate 41 as shown in FIG. 7, it is necessary to use a hole system of several hundred μm or more from the viewpoint of processing accuracy. Therefore, when a plurality of through-hole electrodes 44 are formed, the distance between them is required to be at least about several hundred μm. In recent years, with the integration of semiconductor elements, many end face through-hole electrodes 44 are provided as input / output terminals, so that the external size of the semiconductor device is increased.
[0013]
An object of the present invention is to provide a semiconductor device which can be further reduced in size and a method for manufacturing the same.
[0014]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a substrate having a recess provided on the lower surface side, a side wall provided on the side of the recess, a first conductor member provided on a lower surface of the side wall, A second conductor member provided on an upper surface of a substrate, wherein a part of an outer edge of the substrate is the concave portion, and another of the outer edges is the side wall portion. There is a feature.
[0015]
Thereby, the planar area of the side wall portion can be reduced as compared with the related art in which the outer edge portion of the semiconductor device is the side wall portion, and thus the semiconductor device can be downsized.
[0016]
The substrate is formed by dividing a wafer having a plurality of chip regions for each of the chip regions, and the concave portion of the substrate is formed over two adjacent chip regions of the wafer. Thus, the size of the semiconductor device can be reduced by an easy method.
[0017]
It is preferable that the side wall has a U-shape or a U-shape in which one side of a square ring along the outer edge of the substrate is missing when viewed in plan.
[0018]
In the recess, a semiconductor chip that is flip-chip mounted with the substrate is further provided, and a gap between the substrate and the semiconductor chip is filled with resin, so that a gap between the substrate and the semiconductor chip is formed. Thermal stress due to a difference in expansion coefficient can be reduced.
[0019]
The substrate includes a plurality of insulating layers, and further includes at least one via hole penetrating the insulating layer and filled with a conductor, and at least one wiring pattern interposed between the insulating layers. Is also good.
[0020]
Since the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern, the first conductor member and the second conductor member are formed by the via hole and the wiring pattern having high processing accuracy. Can be electrically connected to the semiconductor device, so that the size of the semiconductor device can be further reduced.
[0021]
The first conductor member and the second conductor member may be electrically connected by a side electrode provided on a side surface of the substrate.
[0022]
A second semiconductor device according to the present invention has a concave portion provided on a lower surface side, a side wall portion provided on a side of the concave portion, and a substrate formed of a plurality of insulating layers; A first conductor member provided on the lower surface of the substrate, a second conductor member provided on the upper surface of the substrate, at least one via hole penetrating the insulating layer and filled with a conductor, and A semiconductor device having at least one wiring pattern interposed therebetween, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern. .
[0023]
Thus, the first conductor member and the second conductor member can be electrically connected by the via hole and the wiring pattern having high processing accuracy, so that the semiconductor device can be reduced in size. Further, more first conductor members can be provided, and a wiring pattern can be formed with a higher degree of freedom. Further, since there is no through hole, the occurrence of distortion can be reduced.
[0024]
Since the recess is filled with the resin, the stress when the substrate is mounted on the printed board can be reduced.
[0025]
A first element may be provided in the recess, and the first element may be electrically connected to at least one of the via holes by flip chip connection or wire bond connection.
[0026]
A first element is provided in the recess, and the first element may be formed in a land grid array shape or a ball grid array shape.
[0027]
According to a first method of manufacturing a semiconductor device of the present invention, a step (a) of forming a concave portion for each of a plurality of chip regions on a lower surface side of a substrate and a step (b) of dividing the substrate into each of the chip regions ) And a step (c) of forming a first conductor member on the lower surface of the side wall of the recess and forming a second conductor member on the upper surface of the substrate.
[0028]
Thus, it is possible to manufacture a semiconductor device in which the area occupied by the side wall portion is smaller than that in the related art, so that the semiconductor device can be reduced in size.
[0029]
In the step (a), a chip having high physical stability can be manufactured by forming the concave portion at a portion other than the outer edges of the two chip regions.
[0030]
In the step (a), the concave portion is formed in the substrate by stacking a plurality of insulating layers, and before the step (a), a via hole that penetrates the insulating layer is formed and filled with a conductor. The method further includes a step (d) of forming a wiring pattern on the surface of the layer, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern, thereby being processed. Since the first conductor member and the second conductor member can be electrically connected by the highly accurate via hole and the wiring pattern, a smaller semiconductor device can be manufactured.
[0031]
According to a second method of manufacturing a semiconductor device of the present invention, a step (a) of forming a via hole penetrating an insulating layer and filling the same with a conductor; and a step (b) of forming a conductive pattern on the surface of the insulating layer. (C) forming a substrate having a recess on the lower surface side by stacking a plurality of the insulating layers, (d) dividing the substrate into chip regions, and (E) forming a first conductor member and forming a second conductor member on the upper surface of the substrate, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern. It is characterized in that it is electrically connected.
[0032]
Thereby, the first conductor member and the second conductor member can be electrically connected by the via hole and the wiring pattern with high processing accuracy, so that a smaller semiconductor device can be manufactured. Further, more first conductor members can be provided, and a wiring pattern can be formed with a higher degree of freedom. Further, since there is no through hole, a semiconductor device in which distortion is unlikely to be generated can be manufactured.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
(1st Embodiment)
In the first embodiment, after describing the outer shape of the substrate, the connection form of the wiring will be described.
[0034]
First, the outer shape of the substrate will be described with reference to FIGS. 1 (a) and 1 (b) and FIG. FIGS. 1A and 1B are diagrams showing an upper surface (main surface) and a lower surface (back surface) of a wafer in which a plurality of chip regions are arranged, and FIG. 2 shows a chip obtained by cutting the wafer. It is the top view, longitudinal section, and cross section which show a structure. Note that FIGS. 1A, 1B, and 2 show only the substrate of the semiconductor device, and do not show the wiring or electronic components provided on or inside the substrate.
[0035]
As shown in FIG. 1A, a plurality of chip regions 3 a partitioned by a cutting line 2 are arranged on a substrate 11 of the wafer 1 of the present embodiment. Then, as shown in FIG. 1B, on the lower surface side of the substrate 11, a cavity 12 is provided over two adjacent chip regions 3a.
[0036]
When the wafer 1 is cut along the cutting line 2, a chip 3 having an outer shape as shown in FIG. 2 is obtained. As shown in FIG. 2, the substrate 11 of the chip 3 is divided into a concave portion 11a serving as the bottom of the cavity 12, and a side wall portion 11b surrounding three sides of the concave portion 11a.
[0037]
Next, a connection configuration of the wiring according to the present embodiment will be described with reference to FIGS. FIG. 3 is a cross-sectional view showing in detail the wiring and the like provided on or inside the surface of the chip substrate in the first embodiment. FIG. 4 is a perspective view showing a substrate of the chip shown in FIG.
[0038]
As shown in FIG. 3, the semiconductor device according to the present embodiment includes a substrate 11 having a concave portion 11a and a side wall portion 11b, a chip component 19 provided on the upper surface of the substrate 11, and a lower surface of the concave portion 11a of the substrate 11. , A semiconductor chip 17 provided on the lower surface of the concave portion 11a of the substrate 11 with the bump electrode 18 interposed therebetween, and a plurality of ceramic sheets 13 constituting the substrate 11 interposed therebetween. A wiring pattern 16, an inner via hole 15 provided through a single-layer ceramic sheet 13 for connecting the wiring patterns 16, and an input / output terminal 14 provided on the lower surface of the side wall 11b of the substrate 11. And an underfill 20 that fills a gap between the substrate 11 and the semiconductor chip 17 in the concave portion 11a. Here, although not shown in FIG. 3, the substrate 11 has an outer shape as shown in FIG.
[0039]
The concave portion 11 a is a bottom portion of the cavity 12 having a depth of 300 to 400 μm formed on the lower surface side of the substrate 11, and the side wall portion 11 b of the substrate 11 is a portion located on the side of the cavity 12. is there.
[0040]
The wiring pattern 16 may function as a passive element such as a filter, a balun, and a capacitor depending on material properties such as a dielectric constant. These passive elements are indispensable in high frequency radio circuits. By interposing the wiring pattern 16 between the plurality of ceramic sheets 13 and functioning as a passive element, it is possible to solve a problem that the passive element is difficult to be integrated on the surface of the substrate 11. Further, further miniaturization can be realized.
[0041]
The input / output terminals 14 are provided in a land grid array on the lower surface of the side wall 11 b of the substrate 11. The pitch of the input / output terminals 14 can be reduced to about 100 μm. This pitch depends on the patterning accuracy during manufacturing.
[0042]
The semiconductor chip 17 is flip-chip connected to the lower surface of the concave portion 11a by the bump electrode 18. The protruding electrode 18 is electrically connected to the wiring pattern 16 by the inner via hole 15, and is also electrically connected to the chip component 19 and the available terminal 14 by the inner via hole 15 and the wiring pattern 16.
[0043]
In the cavity 12, a resin called an underfill 20 fills a gap between the substrate 11 and the semiconductor chip 17. The underfill 20 reduces stress caused by a mismatch in the coefficient of thermal expansion between the material of the semiconductor chip 17 and the material of the substrate 11.
[0044]
As shown in FIG. 4, the substrate 11 has a structure in which a plurality of ceramic sheets 13 are stacked. Wiring patterns 16 are formed on the surfaces of these ceramic sheets 13, and the wiring patterns 16 located in different layers are electrically connected by inner via holes 15.
[0045]
The substrate 11 as shown in FIG. 4 is formed by the following method. First, the wiring pattern 16 is formed on the ceramic sheet 13 by a printing method. In this method, each of the line and the space can be processed with an accuracy of about 50 μm. Subsequently, after forming a through hole penetrating through the ceramic sheet 3, the inner via hole 15 is formed by filling the through hole with a conductor. The through hole at this time can be formed with a hole diameter of about 100 μm. The substrate 11 is formed by superposing a plurality of the ceramic sheets 13 provided with the wiring patterns 16 and the inner via holes 15 as described above. After that, the cavity 12 is formed on the lower surface side of the substrate 11.
[0046]
In the present embodiment, by forming the cavity 12 over the two chip regions 3a, the chip area can be reduced as compared with the related art. This will be described below.
[0047]
When filling the underfill 20 in the gap between the substrate 11 and the semiconductor chip 17, the resin is supplied by bringing the nozzle close to the cavity 21. Therefore, the cavity 21 needs a space for the nozzle to enter. Conventionally, since the cavity 21 is provided for each chip area, this space is also required for each chip area. On the other hand, in this embodiment, since the cavity 21 is provided for each of two or more chip regions, this space can be shared by a plurality of chip regions. In the present embodiment, the side wall 11b is not provided on one of the sides of the recess 11a. From the above, the chip area can be reduced.
[0048]
Further, in this embodiment, since the input / output terminal 14 and other members are electrically connected by the inner via hole 15 and the wiring pattern 16, it is not necessary to provide a through-hole electrode as in the related art. Therefore, the processing accuracy can be improved, and the chip area can be reduced. In addition, the number of input / output terminals 14 provided on the lower surface of the side wall 11b of the substrate 11 can be increased.
[0049]
Further, since a through-hole for providing a through-hole electrode is not required, the wiring pattern 16 can be formed with a higher degree of freedom. Further, when the substrate is sintered at a temperature of about 1000 degrees, the possibility that distortion occurs in the substrate or the like can be avoided. It is considered that the temperature distribution of the substrate during sintering is made uniform because there is no through hole. By avoiding the generation of the distortion as described above, it is possible to suppress the variation in the electrical characteristics of the passive elements provided on or inside the substrate. Further, the area of the margin set in preparation for the occurrence of distortion can be narrowed, so that the chip can be reduced in size.
[0050]
In the above embodiment, the external form of the substrate and the wiring connection form have been described. However, each form is independent, and only one of them may be implemented.
[0051]
In the above embodiment, the cavity 12 is shared by the two chip regions 3a, but the cavity 12 may be shared by three or more chip regions 3a.
[0052]
(Second embodiment)
In the second embodiment, a modified example of the wiring connection mode in the first embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment.
[0053]
As shown in FIG. 5, in the present embodiment, instead of providing the land grid array input / output terminals 14 (shown in FIG. 3) in the first embodiment, a ball grid array input / output terminal 24 is provided. Is provided. The pitch of the input / output terminals 24 is limited by the diameter of the ball, but can be reduced to about 100 μm. The other structure is the same as that of the first embodiment, and the description is omitted.
[0054]
In the present embodiment, the same effects as in the first embodiment can be obtained.
[0055]
(Third embodiment)
In the third embodiment, a modification of the wiring connection mode in the first embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment.
[0056]
As shown in FIG. 6, in the present embodiment, the electrical connection between the substrate 11 and the semiconductor chip 17 is realized by wire bonding instead of being realized by the bump electrode 18 (shown in FIG. 3) in the first embodiment. 38. The inside of the cavity 12 is filled with the resin 30. The other configuration is the same as that of the related art, and the description is omitted.
[0057]
In the present embodiment, the chip area can be reduced because the side wall 11b is not provided on one of the sides of the concave portion 11a in the present embodiment.
[0058]
Further, in this embodiment, since the input / output terminal 14 and other members are electrically connected by the inner via hole 15 and the wiring pattern 16, it is not necessary to provide a through-hole electrode as in the related art. Therefore, the processing accuracy can be improved, and the chip area can be reduced. In addition, the number of input / output terminals 14 provided on the lower surface of the side wall 11b of the substrate 11 can be increased.
[0059]
Further, since a through-hole for providing a through-hole electrode is not required, the wiring pattern 16 can be formed with a higher degree of freedom. Further, when the substrate is sintered at a temperature of about 1000 degrees, the possibility that distortion occurs in the substrate or the like can be avoided. It is considered that the temperature distribution of the substrate during sintering is made uniform because there is no through hole. By avoiding the generation of the distortion as described above, it is possible to suppress the variation in the electrical characteristics of the passive elements provided on or inside the substrate. Further, the area of the margin set in preparation for the occurrence of distortion can be narrowed, so that the chip can be reduced in size.
[0060]
【The invention's effect】
According to the present invention, the size of the semiconductor device can be reduced. Further, the degree of freedom in design can be improved, and variations in electrical characteristics can be reduced.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams showing an upper surface and a lower surface of a wafer in which a plurality of chip regions are arranged in the first embodiment.
FIGS. 2A to 2C are a plan view, a longitudinal sectional view, and a transverse sectional view showing a structure of a chip obtained by cutting a wafer in the first embodiment.
FIG. 3 is a cross-sectional view showing in detail a wiring and the like provided on or inside a surface of a chip substrate in the first embodiment.
FIG. 4 is a perspective view showing only a portion of the substrate of the chip shown in FIG. 3 closer to the main surface than the cavity.
FIG. 5 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment.
FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment.
FIG. 7 is a cross-sectional view showing a structure of a conventional semiconductor device proposed in Japanese Patent No. 2689956;
FIG. 8 is a diagram showing an upper surface of a conventional wafer in which a plurality of chip regions are arranged.
FIG. 9 is a perspective view showing a structure of a conventional chip obtained by cutting a wafer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Wafer 2 Cutting line 3 Chip 3a Chip area 11 Substrate 11a Depression 11b Side wall 12 Cavity 13 Ceramic sheet 14 Input / output electrode 15 Inner via hole 16 Wiring pattern 17 Semiconductor chip 18 Projection electrode 19 Chip component 20 Underfill 24 Input / output terminal 30 Resin 38 Wire Bond

Claims (15)

A substrate having a recess provided on the lower surface side and a side wall provided on the side of the recess,
A first conductor member provided on a lower surface of the side wall portion;
A second conductor member provided on an upper surface of the substrate, wherein a part of an outer edge of the substrate is the concave portion, and another of the outer edges is the side wall portion. A semiconductor device, characterized in that: The semiconductor device according to claim 1,
The substrate is formed by dividing a wafer having a plurality of chip regions for each of the chip regions,
The semiconductor device according to claim 1, wherein the concave portion of the substrate is formed over two chip regions adjacent to each other in the wafer. The semiconductor device according to claim 1, wherein
The semiconductor device according to claim 1, wherein the side wall has a U-shape or a U-shape in which one side of a square ring along the outer edge of the substrate is missing when viewed in plan. The semiconductor device according to any one of claims 1 to 3,
A semiconductor chip flip-chip mounted with the substrate is further provided in the recess.
A semiconductor device, wherein a gap between the substrate and the semiconductor chip is filled with a resin. The semiconductor device according to any one of claims 1 to 4,
The substrate is composed of a plurality of insulating layers,
At least one via hole penetrating the insulating layer and filled with a conductor;
A semiconductor device further comprising at least one wiring pattern interposed between the insulating layers. The semiconductor device according to claim 5,
The semiconductor device according to claim 1, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern. The semiconductor device according to any one of claims 1 to 5,
A semiconductor device, wherein the first conductor member and the second conductor member are electrically connected by a side electrode provided on a side surface of the substrate. A concave portion provided on the lower surface side, a substrate having a side wall portion provided on the side of the concave portion, and a plurality of insulating layers;
A first conductor member provided on a lower surface of the side wall portion;
A second conductor member provided on the upper surface of the substrate,
At least one via hole penetrating the insulating layer and filled with a conductor;
A semiconductor device comprising at least one wiring pattern interposed between the insulating layers,
The semiconductor device according to claim 1, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern. The semiconductor device according to claim 8,
A semiconductor device, wherein the recess is filled with a resin. The semiconductor device according to claim 8, wherein
A first element is provided in the recess,
The semiconductor device, wherein the first element is electrically connected to at least one of the via holes by flip-chip connection or wire bond connection. The semiconductor device according to claim 8, wherein
A first element is provided in the recess,
The semiconductor device according to claim 1, wherein the first element is formed in a land grid array shape or a ball grid array shape. (A) forming a concave portion for each of a plurality of chip regions on the lower surface side of the substrate;
(B) dividing the substrate into one of the chip regions;
Forming a first conductor member on the lower surface of the side wall portion of the recess and forming a second conductor member on the upper surface of the substrate. The method for manufacturing a semiconductor device according to claim 12,
In the step (a), a method of manufacturing a semiconductor device, characterized in that the concave portion is formed in a portion excluding outer peripheral portions of two chip regions. The method for manufacturing a semiconductor device according to claim 12, wherein
In the step (a), the recess is formed in the substrate by stacking a plurality of insulating layers;
Before the step (a), the method further includes a step (d) of forming a via hole penetrating the insulating layer, filling the via hole with a conductor, and forming a wiring pattern on the surface of the insulating layer,
The method of manufacturing a semiconductor device, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern. (A) forming a via hole penetrating through the insulating layer and filling with a conductor;
(B) forming a conductor pattern on the surface of the insulating layer;
(C) forming a substrate having a concave portion on the lower surface side by stacking a plurality of the insulating layers;
(D) dividing the substrate into chip regions;
Forming a first conductor member on the lower surface of the side wall of the concave portion and forming a second conductor member on the upper surface of the substrate;
A method of manufacturing a semiconductor device, wherein the first conductor member and the second conductor member are electrically connected by the via hole and the wiring pattern.

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