JP2004096083A

JP2004096083A - Semiconductor device and its manufacturing method

Info

Publication number: JP2004096083A
Application number: JP2003179200A
Authority: JP
Inventors: Hitoshi Sumida; 澄田　仁志
Original assignee: Fuji Electric Device Technology Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2002-07-08
Filing date: 2003-06-24
Publication date: 2004-03-25
Anticipated expiration: 2023-06-24
Also published as: JP4193604B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device on which a thick film gate HVPMOS having a punch-through voltage higher than an avalanche breakdown voltage is mounted. <P>SOLUTION: An n-type well region 70 is formed on the surface layer of an n-type substrate 3 of an SOI substrate 123. A p-type offset region 50 is formed apart from the n-type well region 70. A p-type source region 80 is formed on the surface layer of the n-type well region 70. A p-type drain region 6 is formed on the surface layer of the p-type offset region. A gate electrode 13 is formed on the n-type substrate 3 sandwiched between the p-type offset region 50 and the p-type source region, and on the n-type well region 70 via a thick film gate oxide film 11. A stable element withstand voltage can be obtained by making the punch-through voltage generated in a state that a depletion layer reaches the p-type source region 80 higher than the avalanche voltage generated in the p-type offset region 50 by making the amount of impurity in the n-type well region 70 to be high in a concentration of 3×10<SP>12</SP>cm<SP>-2</SP>-1×10<SP>13</SP>cm<SP>-2</SP>. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、貼り合わせ基板（以下、ＳＯＩ基板と略す）上に形成された高耐圧横型ＭＯＳＦＥＴなどの半導体装置に関する。
【０００２】
【従来の技術】
近年、ＳＯＩ基板とトレンチ分離を組み合わせた誘電体分離技術の進歩により、横型のダイオードや絶縁ゲート形バイポーラトランジスタ（以下、ＩＧＢＴと略す）、横型のＭＯＳＦＥＴなどの高耐圧デバイスとその駆動・制御・保護回路を一つのシリコン基板上に集積したパワー集積回路（以下、パワーＩＣと略す）の開発が盛んになっている。
ＳＯＩ基板を用いた誘電体分離基板上にパワーＩＣを作製することの大きなメリットは、バイポーラデバイスをハイサイドスイッチとして適用できること、しかもこれらを多出力化できる点にある。そのため、三相モータを駆動するインバターＩＣやフラットパネルディスプレイを駆動するドライバＩＣでは、ＩＧＢＴで構成されたトーテムポール回路を、出力回路として１チップ上に複数搭載したＩＣが開発されている。
【０００３】
ハイサイドスイッチを駆動する場合、レベルシフト回路が必要になる。このレベルシフト回路を高耐圧横形ｐチャネルＭＯＳＦＥＴ（以下ＨＶＰＭＯＳと略す）で構成することにより、別電源やコンデンサなどを必要としない単純な構成にすることができる。しかも、ＨＶＰＭＯＳのゲート酸化膜を厚くすることにより、ＨＶＰＭＯＳを出力側電源電圧によって直接駆動することが可能となり、ｎチャネル形ＭＯＳＦＥＴと組み合わせたＣＭＯＳ構成のレベルシフト回路を実現できる。その結果、レベルシフト回路の低消費電力化を達成することができる。
このような背景から、入力側電源電圧が印加される標準のゲート酸化膜とは異なり、出力側電源電圧の印加に耐えうる厚膜のゲート酸化膜を備えたＨＶＰＭＯＳの開発が重要になっている。尚、本明細書では標準膜厚のゲート酸化膜を備えたＨＶＰＭＯＳを標準ゲートＨＶＰＭＯＳと呼び、厚膜のゲート酸化膜を備えたＨＶＰＭＯＳを厚膜ゲートＨＶＰＭＯＳと呼ぶ。
【０００４】
図１２は、厚膜ゲートＨＶＰＭＯＳを適用したレベルシフト回路の一例を示す図である。
出力回路部Ａとして２つのＩＧＢＴ（Ｎ１、Ｎ２）からなるトーテムポール回路が搭載され、その前段に２つのＮチャネル形ＭＯＳＦＥＴ（Ｎ３、Ｎ４）と２つのＨＶＰＭＯＳ（Ｐ１、Ｐ２）で構成されたレベルシフト回路部Ｂが搭載されている。出力デバイスＮ１はＶｉｎ１によって制御され、Ｎ２はレベルシフト回路を駆動するＶｉｎ２、Ｖｉｎ３の信号によって制御される。なお、出力回路部Ａに内蔵されたＺＤはＮ２のゲートを保護するためのツェナーダイオードである。出力側電源電圧ＶＨには高電圧が印加されるため、本回路を構成するＺＤ以外のデバイスは全て高耐圧デバイスである。
【０００５】
本回路のレベルシフト回路Ｂは既知の回路であり、ここではその動作説明を省く。このレベルシフト回路の特徴はＰ１とＰ２のゲートを出力側電源電圧ＶＨで駆動できるところにある。このため、レベルシフト回路Ｂを通常のＣＭＯＳ回路で構成することが可能となり、レベルシフト回路Ｂの消費電力を大幅に低減させることができる。
図１３は、ＨＶＰＭＯＳをＳＯＩ基板に形成した場合の半導体装置の要部断面図である。各素子が形成される基板はｎ形基板３である。この導電形はパワーＩＣの出力回路を構成するｎチャネル形素子の形成を容易にする目的から選んでいる。以下、ＳＯＩ基板に形成したＨＶＰＭＯＳの高耐圧化について説明する。
【０００６】
ｎ形基板３にＨＶＰＭＯＳを形成するためには、ｐ形オフセット領域５０が不可欠になる。素子耐圧（素子のブレークダウン電圧のこと）はこのｐ形オフセット領域５０とｎ形ドリフト領域４の接合で発生するアバランシェブレークダウン電圧によって決まり、この電圧はｐ形オフセット領域５０の形成条件に依存する。したがって、素子の高耐化はこのｐ形オフセット領域５０の形成条件を最適化することで実施される。
厚膜ゲートＨＶＰＭＯＳと標準ゲートＨＶＰＭＯＳの構造上の相違点は、ゲート酸化膜厚と、ｐ形ソース領域の形成工程にある。厚膜のゲート酸化膜の厚さは、出力側電源電圧の大きさで決まり、その必要性については先に述べた通りである。
【０００７】
一方、ｐ形ソース領域の形成工程に関しては、標準ゲートＨＶＰＭＯＳでは、薄膜のゲート酸化膜を形成した後にゲート電極となるポリシリコンをパターン形成し、このポリシリコンをマスクとして用いてｐ形ソース領域８２がセルフアラインで形成される。
しかし、厚膜ゲートＨＶＰＭＯＳでは、ｐ形ソース領域８１を従来の標準ゲートＨＶＰＭＯＳの工程のように、ゲート電極となるポリシリコンをマスクとしてイオン注入と熱処理で形成する場合には、ゲート電極とｐ形ソース領域の間の耐圧を確保するために、図１４のように、ポリシリコンは厚膜のゲート酸化膜より小さくパターニングする必要があり、この厚膜のゲート酸化膜を通してイオン注入すると、ハの領域は不完全にイオン注入されて、正規のドーズ量が半導体基材に打ち込まれない。また、厚膜のゲート酸化膜では、その側面にポリシリコンのエッチング残りやポリシリコンの残渣が付着するために、ｐ形ソース領域８１のパターン形状が正規寸法からずれを生じてしまう。そのため、標準ゲートＨＶＰＭＯＳのｐ形ソース領域のようにセルフアライン（ゲート電極としてのポリシリコンをマスクとしてｐ形ソース領域を形成すること）でｐ形ソース領域８１を形成することができない。
【０００８】
これを、防止するために、標準ゲートＨＶＰＭＯＳのｐ形ソース領域を形成する前に、厚膜ゲートＨＶＰＭＯＳのｐ形ソース領域８１を予め形成する方法にすると、標準ゲートＨＶＰＭＯＳのｐ形ソース領域を形成する前に、６回程度高温の熱処理工程が行われることとなり、この高温の熱処理により、厚膜ゲートＨＶＰＭＯＳのｐ形ソース領域８１の拡散深さが、標準ゲートＨＶＰＭＯＳのｐ形ソース領域８２（図１３の点線）の拡散深さと比べて深くなる。その結果、ｎ形ウエル領域７０の拡散深さとｐ形ソース領域８１の拡散深さの差ｄが小さくなる。次に、ＳＯＩ基板に形成したＨＶＰＭＯＳの高電圧印加状態について考えてみる。
【０００９】
図１５は、ＳＯＩ基板上の標準ゲートＨＶＰＭＯＳのｐ形ドレイン層６に−２８０Ｖの電圧を印加した場合の電位分布を示す図である。これはデバイスシミュレーションによって求めた結果である。尚、ここでは半導体基板１の領域を省略している。また、図示しないが、厚膜ゲートＨＶＰＭＯＳにおいても、本結果と同様の電位分布となる。
本結果からわかるように、ＳＯＩ基板上のＨＶＰＭＯＳでは高耐圧印加時の素子内部の等電位線がｎ形ウエル領域７０直下のｎ形基板３（ｎ形ドリフト領域）に集中する。したがって、ｐ形オフセット領域５０ほどではないものの、この等電位線の集中によるｎ形ウエル領域７０の空乏化が進展する。
【００１０】
先に説明したように、厚膜ゲートＨＶＰＭＯＳはｐ形ソース領域８１の拡散深さが深い。そのため、ｎ形ウエル領域７０とｐ形ソース領域８１の深さ方向での拡散端距離（図１３のｄ）が短くなる。そして、図１５に示したように、ＳＯＩ基板上のＨＶＰＭＯＳに高電圧を印加した時はｎ形ウエル領域７０が空乏化しやすい。よって、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳの高電圧印加時はｎ形ウエル領域７０の深さ方向における空乏化によって、ｐ形オフセット領域５０とｐ形ソース領域８１間のパンチスルーが起こりやすくなる。
このパンチスルーが発生すると、ｐ形オフセット領域の形成条件による素子耐圧の制御が不可能となる。このため、素子の耐圧設計、すなわち素子の高耐圧化を図ることが困難になる。よって、このパンチスルーの発生を防止しなければならない。つぎに、パンチスルーを防止する方法について説明する。
【００１１】
図１６は、パンチスルーを防止する深い拡散層を用いた素子構造の要部断面図である。この素子はＳＯＩ基板の酸化膜２に到達するｎ形ウエル領域７３ならびにｐ形拡散領域５１によって構成されている。この素子ではｐ形ソース領域８１とｎ形ウエル領域７３の深さ方向における拡散端距離ｄが十分に長い。したがって、ｎ形ウエル領域７３の深さ方向における空乏化によって引き起こされる、ｐ形拡散領域５１とｐ形ソース領域８１間のパンチスルーは発生しない。
しかし、本素子構造ではｎ形拡散領域７３（ｎ形ウエル領域７０に相当する）とｐ形拡散領域５１（ｐ形オフセット領域５０に相当する）をＳＯＩ基板の酸化膜２まで拡散しなければならない。このため、長時間の拡散工程を必要とし、製造リードタイムの増加を招く。また、長時間の拡散工程は本デバイスを搭載したパワーＩＣの他デバイスへの影響もある。したがって、図１６に示した素子構造の採用はパワーＩＣを構成するデバイスの設計を根本から変えることになり、例えば同一基板上に形成する横形ＩＧＢＴの新規開発も要求される。従って、図１３に示した素子構造でのパンチスルー防止策を確立する必要がある。
【００１２】
また、高耐圧横型半導体装置において、ゲート電極をはみ出してゲート電極上とオフセット領域上へソース電極を形成し、このはみ出し長さを所定の長さとすることで、ｐオフセット領域の全電荷量を低下させることなく高耐圧化できる高耐圧ｐチャネルＭＯＳＦＥＴをＳＯＩ基板に形成することが報告されている（特許文献１参照）。
また、高耐圧横型半導体装置において、ゲート電極をオフセット領域上に延在して形成し、オフセット領域上に形成するゲート電極の長さを所定の長さとすることで、ｐオフセット領域の全電荷量を低下させることなく高耐圧化できる高耐圧ｐチャネルＭＯＳＦＥＴをＳＯＩ基板に形成することが報告されている（特許文献２参照）。
【００１３】
【特許文献１】
特開平１１−１４５４６２号
【特許文献２】
特開２０００−２５２４６７号
【００１４】
【発明が解決しようとする課題】
前記のように、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳではｐ形ソース領域の拡散深さが深くなる。そのため、チャネル領域を形成するｎ形ウエル領域と深さ方向における拡散端距離（図１３のｄ）が短い。また、ＳＯＩ基板上のＨＶＰＭＯＳに高電圧を印加した場合、素子内部の等電位線はｎ形ウエル領域直下のｎ形ドリフト領域に集中する。
このことから、ＳＯＩ基板上の厚膜ゲートＨＶＰＭＯＳでは高電圧印加時に、ｎ形ウエル領域７０の深さ方向での空乏化によるｐ形オフセット領域５０とｐ形ソース領域８１間のパンチスルーが、ｐ形オフセット領域５０とｎ形基板３のｐｎ接合でのアバランシェブレークダウンより起こり易い。
【００１５】
このパンチスルーが発生すると、ｐ形オフセット領域の形成条件による素子耐圧の制御が不可能となる。このため、通常、アバランシェブレークダウン電圧で設計する素子の耐圧の設計ができない。従って、ＳＯＩ基板上の厚膜ゲートＨＶＰＭＯＳではこのパンチスルーの発生を防止することが大きな課題となる。
この発明の目的は、前記の課題を解決し、アバランシェブレークダウン電圧より高いパンチスルー電圧を有した厚膜ゲートＨＶＰＭＯＳを搭載した半導体装置を提供することにある。
【００１６】
【課題を解決するための手段】
前記の目的を達成するために、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に形成された半導体装置において、前記第２半導体基材の表面に選択的に形成され、拡散深さが前記絶縁膜に到達しない第１導電形のウエル領域と、前記第２半導体基材の表面層に前記ウエル領域から離して選択的に形成された第２導電形のオフセット領域と、前記第１導電形のウエル領域の表面層に選択的に形成された第２導電形のソース領域と、前記オフセット領域の表面層に選択的に形成された第２導電形のドレイン領域と、前記ウエル領域の表面層に選択的に形成された第１導電形のコンタクト領域と、前記ソース領域と前記オフセット領域に挟まれた前記第２半導体基材上と前記ウエル領域上に、ゲート絶縁膜（このゲート絶縁膜は同一の貼り合わせ基板に形成されるＣＭＯＳ回路などのＭＯＳＦＥＴのゲート絶縁膜より膜厚が厚い）を介して形成されたゲート電極と、前記コンタクト領域上と前記ソース領域上とに形成されたソース電極と、前記ドレイン領域上に形成されたドレイン電極とを有する半導体装置であって、
前記ドレイン領域の拡散深さより拡散深さが深い前記ソース領域を有し、前記ウエル領域の不純物量を所定の値とし、前記ドレイン電極に対して前記ソース電極に正の電圧を印加したときの、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧が高い構成とする。
【００１７】
前記不純物量の所定の値が、３×１０^１２ｃｍ^−２以上で、１×１０^１３ｃｍ^−２以下であるとよい。
また、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に横型の第２導電形チャネルの第１ＭＯＳＦＥＴと、横型の第２導電形チャネルの第２ＭＯＳＦＥＴを有するＣＭＯＳ回路とが形成された半導体装置において、前記第２半導体基材の表面に選択的に形成され、拡散深さが前記絶縁膜に到達しない第１導電形の第１ウエル領域と、前記第２半導体基材の表面層に前記第１ウエル領域から離して選択的に形成された第２導電形のオフセット領域と、前記第１ウエル領域の表面層に選択的に形成された第２導電形のソース領域と、前記オフセット領域の表面層に選択的に形成された第２導電形のドレイン領域と、前記第１ウエル領域の表面層に形成された第１導電形のコンタクト領域と、前記ソース領域と前記オフセット領域に挟まれた前記第２半導体基材上と前記第１ウエル領域上に、第２ＭＯＳＦＥＴのゲート絶縁膜より厚膜のゲート絶縁膜を介して形成されたゲート電極と、前記コンタクト領域上と前記ソース領域上とに形成されたソース電極と、前記ドレイン領域上に形成されたドレイン電極とを有する横型の第１ＭＯＳＦＥＴを具備する半導体装置であって、
前記第１ウエル領域の不純物量が、前記第２ＭＯＳＦＥＴの第２ウエル領域の不純物量よりも大きくし、前記ドレイン電極に対して前記ソース電極に正の電圧を印加した場合に、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧が高い構成とする。
【００１８】
また、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に横型の第２導電形チャネルのＭＯＳＦＥＴと、第１導電形のバッファ領域を有する横型の第１導電形チャネルの絶縁ゲート形バイポーラトランジスタとが形成された半導体装置において、前記第２半導体基材の表面に選択的に形成され、拡散深さが前記絶縁膜に到達しない第１導電形のウエル領域と、前記第２半導体基材の表面層に前記ウエル領域から離して選択的に形成された第２導電形のオフセット領域と、前記ウエル領域の表面層に選択的に形成された第２導電形のソース領域と、前記オフセット領域の表面層に選択的に形成された第２導電形のドレイン領域と、前記ウエル領域の表面層に形成された第１導電形のコンタクト領域と、前記ソース領域と前記オフセット領域に挟まれた前記第２半導体基材上と前記ウエル領域上に、前記絶縁ゲートバイポーラトランジスタのゲート絶縁膜より厚膜のゲート絶縁膜を介して形成されたゲート電極と、前記コンタクト領域上と前記ソース領域上とに形成されたソース電極と、前記ドレイン領域上に形成されたドレイン電極とを有する横型のＭＯＳＦＥＴを具備する半導体装置であって、
前記ウエル領域の不純物量と、前記バッファ領域の不純物量とを同一とし、前記ドレイン電極に対して前記ソース電極に正の電圧を印加した場合に、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧が高い構成とする。
【００１９】
また、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に形成された半導体装置の製造方法において、前記第２半導体基材の表面に選択的に拡散深さが前記絶縁膜に到達しない第１導電形のウエル領域を形成する工程と、前記第２半導体基材の表面層に前記ウエル領域から離して選択的に第２導電形のオフセット領域を形成する工程と、前記第１導電形のウエル領域の表面層に選択的に第２導電形のソース領域を形成する工程と、前記オフセット領域の表面層に第２導電形のドレイン領域を形成する工程と、前記ウエル領域の表面層に第１導電形のコンタクト領域を形成する工程と、前記ソース領域と前記第２半導体基材に挟まれた前記ウエル領域上に、同時に形成されるＣＭＯＳ回路のＭＯＳＦＥＴのゲート絶縁膜より厚膜のゲート絶縁膜（このゲート絶縁膜は同一の貼り合わせ基板に形成されるＣＭＯＳ回路などのＭＯＳＦＥＴのゲート絶縁膜より膜厚が厚い）を介して形成されたゲート電極と、前記コンタクト領域上とを介してゲート電極を形成する工程と、前記コンタクト領域上と前記ソース領域上とにソース電極を、前記ドレイン領域上にドレイン電極とを形成する工程とを有する半導体装置の製造方法であって、
前記ドレイン領域の拡散深さより前記ソース領域の拡散深さを深くし、前記ドレイン電極に対して前記ソース電極に正の電圧を印加した場合に、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧の方が高くなる前記ウエル領域の不純物量とする製造方法とする。
【００２０】
また、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に横型の第２導電形チャネルの第１ＭＯＳＦＥＴと、横型の第２導電形チャネルの第２ＭＯＳＦＥＴを有するＣＭＯＳ回路とが形成された半導体装置の製造方法において、前記第２半導体基材の表面に選択的に、拡散深さが前記絶縁膜に到達しない第１導電形の第１ウエル領域を形成する工程と、前記第２半導体基材の表面層に前記第１ウエル領域から離して選択的に第２導電形のオフセット領域を形成する工程と、前記第１ウエル領域の表面層に選択的に第２導電形のソース領域を形成する工程と、該オフセット領域の表面層に第２導電形のドレイン領域を形成する工程と、前記第１ウエル領域の表面層に選択的に第１導電形のコンタクト領域を形成する工程と、前記ソース領域と前記オフセット領域に挟まれた前記第２半導体基材上と前記第１ウエル領域上に、前記第２ＭＯＳＦＥＴのゲート絶縁膜より厚膜のゲート絶縁膜を介してゲート電極を形成する工程と、前記コンタクト領域上と前記ソース領域上とにソース電極を、前記ドレイン領域上にドレイン電極とを形成する工程とを有する横型の第１ＭＯＳＦＥＴを具備する半導体装置の製造方法であって、
前記ドレイン電極に対して前記ソース電極に正の電圧を印加した場合に、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧を高くするように、前記１ウエル領域の不純物量を、前記第２ＭＯＳＦＥＴの第２ウエル領域の不純物量よりも大きくする製造方法とする。
【００２１】
また、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に横型の第２導電形チャネルのＭＯＳＦＥＴと、第１導電形のバッファ領域を有する横型の第１導電形チャネルの絶縁ゲート形バイポーラトランジスタとが形成された半導体装置の製造方法において、前記第２半導体基材の表面に選択的に拡散深さが前記絶縁膜に到達しない第１導電形のウエル領域を形成する工程と、前記第２半導体基材の表面層に前記ウエル領域から離して選択的に第２導電形のオフセット領域を形成する工程と、前記ウエル領域の表面層に選択的に第２導電形のソース領域を形成する工程と、該オフセット領域の表面層に第２導電形のドレイン領域を形成する工程と、前記ウエル領域の表面層に選択的に第１導電形のコンタクト領域を形成する工程と、前記ソース領域と前記オフセット領域に挟まれた前記第２半導体基材上と前記ウエル領域上に、前記絶縁ゲートバイポーラトランジスタのゲート絶縁膜より厚膜のゲート絶縁膜を介してゲート電極を形成する工程と、前記コンタクト領域上と前記ソース領域上とにソース電極と、前記ドレイン領域上にドレイン電極とを形成する工程とを有する横型のＭＯＳＦＥＴを具備する半導体装置の製造方法であって、
前記ウエル領域の不純物量と、前記バッファ領域の不純物量とを同一とし、前記ドレイン電極に対して前記ソース電極に正の電圧を印加した場合に、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧を高くするように、前記ウエル領域の不純物量と、前記バッファ領域の不純物量とを同一とする製造方法とする。
【００２２】
前記の内容をさらに説明する。ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳの高耐圧化を図るためには、ｐ形オフセット領域とｐ形ソース領域間のパンチスルーを防止し、ｐ形オフセット領域の形成条件によって素子耐圧を制御できるようにしなければならない。そのための手段として、ｐ形オフセット領域とｐ形ソース領域間のパンチスルー電圧を、ｐ形オフセット領域とｎ形ドリフト領域の接合で発生するアバランシェブレークダウン電圧よりも高くするとよい。これは、ｎ形ウエル領域の不純物量（電荷量）を調整することによって実現可能であり、所望とする耐圧値、すなわちｐ形オフセット領域の形成条件に応じてｎ形ウエル層の不純物量を調整すればよい。
【００２３】
また、ＣＭＯＳ回路を同一のＳＯＩ基板上に備えた場合では、厚膜ゲートＨＶＰＭＯＳのｎ形ウエル領域の不純物量を、ＣＭＯＳ回路を構成するｐチャネル形ＭＯＳＦＥＴのチャネル領域を形成するｎ形ウエル領域の不純物量よりも多くすればよい。
さらに、横形ＩＧＢＴを同一のＳＯＩ基板上に搭載する場合では、厚膜ゲートＨＶＰＭＯＳのｎ形ウエル領域に横形ＩＧＢＴのｎ形バッファ層を適用すればよい。
以上の手段により、ＳＯＩ基板上の厚膜ゲートＨＶＰＭＯＳで発生するｐ形オフセット領域とｐ形ソース領域間のパンチスルーを防止することが可能となる。その結果、素子の耐圧設計が容易となり、かつ素子の高耐圧化を実現することができる。
【００２４】
また、第１半導体基材と第２半導体基材が絶縁膜を介して貼り合わされ、該第２半導体基材が所定の厚さに研磨された貼り合わせ基板に形成された半導体装置において、
前記第２半導体基材の表面に選択的に形成され、拡散深さが前記絶縁膜に到達しない第１導電形のウエル領域と、前記第２半導体基材の表面層に前記ウエル領域から離して選択的に形成された第２導電形のオフセット領域と、前記第１導電形のウエル領域の表面層に選択的に形成された第２導電形のソース領域と、前記オフセット領域の表面層に選択的に形成された第２導電形のドレイン領域と、前記ウエル領域の表面層に選択的に形成された第１導電形のコンタクト領域と、前記ソース領域と前記コンタクト領域に挟まれ、前記ソース領域と接続して前記ウエル領域の表面層に形成される前記ソース領域より高濃度の第１導電形の補助ソース領域と、前記ソース領域と前記オフセット領域に挟まれた前記第２半導体基材上と前記ウエル領域上にゲート絶縁膜を介して形成されたゲート電極と、前記コンタクト領域上と前記補助ソース領域上とに形成されたソース電極と、前記ドレイン領域上に形成されたドレイン電極とを有する半導体装置であって、
前記ドレイン領域の拡散深さより拡散深さが深い前記ソース領域を有し、前記ウエル領域の不純物量を所定の値とし、前記ドレイン電極に対して前記ソース電極に正の電圧を印加したときの、前記オフセット領域と前記第２半導体基材で形成される接合のアバランシェブレークダウン電圧より、前記ソース領域に空乏層が達するパンチスルー電圧が高く、前記補助ソース領域の拡散深さを前記ソース領域の拡散深さより浅い構成とする。
【００２５】
また、前記ドレイン電極に対して前記ソース電極に正の電圧を印加し、前記ソース電極に対して前記ゲート電極に負の電圧を印加したとき（または、前記ゲート電極と前記ドレイン電極を同一電位としたとき）、前記ソース領域直下の前記ウエル領域を流れる電流で、前記ソース領域と該ソース領域直下の前記ウエル領域で形成されるｐｎ接合で発生する電圧で前記ソース領域から前記ウエル領域へのキャリアの注入がないような構成とする。
また、前記ソース領域と該ソース領域直下の前記ウエル領域で形成されるｐｎ接合で発生する電圧が０．６Ｖ以下であるとよい。
【００２６】
また、前記補助ソース領域が、島状に形成され、該島状に形成された前記補助ソース領域が、前記ソース領域と前記ソース電極とに接続すると構成とする。
また、前記補助ソース領域が、前記ドレイン領域と同一不純物濃度で同一拡散深さで形成されるとよい。
このようにすることで、ゲートにドレインと同等の電圧を印加した場合でも、ソースからウエルへのキャリアの注入が防止されて、素子が２次降伏することがなく、順方向安全動作領域を広くすることができる。
〔作用〕
上記で述べたように、ｎ形ウエル領域の不純物量を調整することによって、ｐ形オフセット領域とｐ形ソース領域間のパンチスルー電圧を、ｐ形オフセット領域とｎ形ドリフト領域の接合で発生するアバランシェブレークダウン電圧よりも高くするとよい。これにより、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳの高耐圧化を実現することができる。
【００２７】
また、ｐ形ソース領域を平面的に細く形成し、ソース電極とはｎ形ウエル領域内に形成された高濃度のｐ形拡散領域を介してコンタクトする。これにより、ｐ形ソース領域の拡散幅を短縮することが可能となり、ｐ形ソース領域とｎ形ウエル領域の接合部における抵抗を減少させることができる。
また、高濃度のｐ形拡散領域をｎ形ウエル領域内に島状に形成し、他の領域にはｎ形コンタクト領域を形成することにより、ｎ形コンタクト領域の形成領域を増加させることができる。その結果、２次降伏発生のトリガとなる基板電流をソース電極と接続するｎ形コンタクト領域で引き抜くことが容易となり、２次降伏の発生を抑えることができる。
【００２８】
上記二つの作用により、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳの２次降伏発生を防止することができる。
なお、高濃度のｐ形拡散領域をｐ形ドレイン領域と同一の拡散領域で形成することにより、本素子を形成するために必要なプロセス工程数の増加を抑えることが可能となる。
【００２９】
【発明の実施の形態】
図１は、この発明の第１実施例の半導体装置の要部断面図である。図１３と同一箇所には同一符号を記した。ｎ形またはｐ形の基板１とｎ形基板３とを酸化膜２で貼り合わせたＳＯＩ基板１２３のｎ形基板３の表面層にｎ形ウエル領域７０を形成し、このｎ形ウエル領域７０と離してｐ形オフセット領域５０を形成する。ｎ形ウエル領域７０、ｐ形オフセット領域５０が形成されないｎ形基板３がｎ形ドリフト領域４となる。
ｎ形ウエル領域７０の表面層にｐ形ソース領域８０を形成し、ｐ形オフセット領域の５０表面層に高濃度のｐ形ドレイン領域６を形成する。ｎ形ウエル領域７０の表面層にｐ形ソース領域８０と接して（接しない場合もある）高濃度のｎ形コンタクト領域９を形成する。ｐ形オフセット領域５０とｐ形ソース領域８０に挟まれたｎ形基板３上とｎ形ウエル領域７０上に厚膜のゲート酸化膜１１を介してポリシリコンのゲート電極１３を形成し、ｐ形ソース領域８０上とｎ形コンタクト領域９上にソース電極１４を形成し、ドレイン領域６上にドレイン電極１５を形成する。また、ｐ形オフセット領域５０上には絶縁膜が形成されその上にゲート電極１３が延在する。厚膜のゲート酸化膜１１の膜厚（４００ｎｍ程度）は、図示しない、同時に形成されるＣＭＯＳ回路のＭＯＳＦＥＴのゲート酸化膜や横型ＩＧＢＴのゲート酸化膜の膜厚（２０ｎｍ〜２５ｎｍ）よりも厚く形成する。前記のｎ形基板３の内で、前記のｎ形ウエル領域７０、ｐ形オフセット領域５０が形成されない箇所がｎ形ドリフト領域４となる。
【００３０】
ｐ形ソース領域８０の形成後、ｐ形ドレイン領域６が形成されるまでに、５回程度の熱処理工程を経るために、ｐ形ソース領域８０の拡散深さ（１μｍ程度）はｐドレイン領域６の深さ（０．５μｍ程度）より深い。また、ｎ形ウエル領域７０の不純物量を３×１０^１２ｃｍ^−２以上、１×１０^１３ｃｍ^−２以下とする。また、ｐ形オフセット領域の長さＬｐを６μｍから１２μｍ程度とする。尚、図中のＳはソース端子、Ｇはゲート端子、Ｄはドレイン端子である。
図２は、図１の素子構造におけるｐ形オフセット領域の長さＬｐと素子耐圧の関係を示す図である。この素子構造においては、ｐ形ソース領域８０の拡散深さとｎ形ウエル領域７０の拡散深さの差は約２μｍであり、ｐ形オフセット領域５０の不純物量は２×１０^１２ｃｍ^−２である。
【００３１】
ｎ形ウエル領域７０の不純物量が２×１０^１２ｃｍ^−２では耐圧値がＬｐに依存せず、約１００Ｖの一定値を示した。この値はｐ形オフセット領域５０とｐ形ソース領域７０間のパンチスルー電圧である。この結果は、ｎ形ウエル領域７０の不純物量が２×１０^１２ｃｍ^−２の素子では素子耐圧はパンチスルー電圧で決まってしまい、ｐ形オフセット領域５０の形成条件、つまり、Ｌｐを変化させて素子耐圧を変えるなどの制御することができないことを示している。
ｎ形ウエル領域７０の不純物量を増加すると、素子耐圧はＬｐに依存する。ｎ形ウエル領域７０の不純物量が５×１０^１２ｃｍ^−２の場合と７．５×１０^１２ｃｍ^−２の場合を比較すると、Ｌｐ＝６μｍではともに１４０Ｖ前後の素子耐圧を示している。Ｌｐを増加させると、５×１０^１２ｃｍ^−２の不純物量では１５０Ｖ程度で素子耐圧が飽和しているのに対し、７．５×１０^１２ｃｍ^−２の不純物量では約２２０Ｖ程度まで上昇した後に飽和した。素子耐圧が上昇している範囲では、アバランシェブレークダウンが起こっており、素子耐圧はアバランシェブレークダウン電圧となる。一方、飽和値を示す範囲では、パンチスルーが起こっており、素子耐圧はパンチスルー電圧となる。
【００３２】
ここで、例えばｎ形ウエル領域７０の不純物量を７．５×１０^１２ｃｍ^−２以上に設定しておくと、２２０Ｖのパンチスルー電圧まではｐ形オフセット領域５０の形成条件（Ｌｐを長くするなど）で素子耐圧を制御することができる。すなわち、ｎ形ウエル領域７０の不純物量を調整することによって、ｐ形オフセット領域５０とｎ形ドリフト領域４の接合でアバランシェブレークダウンを発生させ、安定した素子耐圧を得ることができる。また、ＳＯＩ基板上の厚膜ゲートＨＶＰＭＯＳの耐圧設計が容易になる。
ここで、ｎ形ウエル領域７０の不純物量にまとめると次のようになる。ｎ形ウエル領域７０の不純物量が、３×１０^１２ｃｍ^−２未満では、素子耐圧がパンチスルー発生電圧となり、素子耐圧を高くできない。一方、１×１０^１３ｃｍ^−２を超えるとｎ形ウエル領域７０のチャネル形成部の不純物濃度が高くなり、ゲートしきい値電圧が高くなり過ぎる。
【００３３】
そのため、本発明の半導体装置においては、ｎ形ウエル領域７０の不純物量を３×１０^１２ｃｍ^−２以上で、１×１０^１３ｃｍ^−２以下とする。好ましくは、４×１０^１２ｃｍ^−２以上で、７．５×１０^１２ｃｍ^−２以下とするとよい。また、ｐ形オフセット領域の長さＬｐは６μｍから１２μｍ程度がよい。
図３は、この発明の第２実施例の半導体装置の要部断面図である。この図は、図１の横型の厚膜ゲートＨＶＰＭＯＳとＣＭＯＳ回路のｎ形およびｐ形ＭＯＳＦＥＴをＳＯＩ基板に形成した場合を示す。
ＳＯＩ基板１２３とトレンチ誘電体分離１７によって構成された誘電体分離基板上にパワーＩＣを構成した場合の要部断面図で、ここでは、図１の横型の厚膜ゲートＨＶＰＭＯＳとＣＭＯＳ回路を構成する低耐圧のｎチャネルＭＯＳＦＥＴとｐチャネルＭＯＳＦＥＴを形成した図である。
【００３４】
このパワーＩＣでは、トレンチ誘電体分離１７よって形成された２つの半導体領域に厚膜ゲートＨＶＰＭＯＳ１９とＣＭＯＳ回路２０を構成する低耐圧のｐチャネル形ＭＯＳＦＥＴ２１とｎチャネル形ＭＯＳＦＥＴ２２が形成されている。ＣＭＯＳ回路２０のｐチャネル形ＭＯＳＦＥＴ２１は低耐圧であるために、ｎ形ウエル領域７１の不純物量は２×１０^１２ｃｍ^−２程度である。一方、厚膜ゲートＨＶＰＭＯＳ１９のｎ形ウエル領域７０の不純物量をｎ形ウエル領域７１の不純物量より多くして、図１で説明した範囲とすることで、図１と同様の効果が得られる。
【００３５】
図４は、この発明の第３実施例の半導体装置の要部断面図である。ＳＯＩ基板１２３とトレンチ分離１７によって構成された誘電体分離基板上にパワーＩＣを構成した場合を示す。このパワーＩＣではトレンチ誘電体分離１７よって形成された２つの半導体領域に横形ＩＧＢＴ１８と厚膜ゲートＨＶＰＭＯＳ１９が形成されている。
横形ＩＧＢＴ１８ではｎ形バッファ領域７２の形成が耐圧確保のために不可欠である。このｎ形バッファ領域７２の不純物量を３×１０^１２ｃｍ^−２以上することで、ＩＧＢＴの素子耐圧を確保することができる。そのため、このｎ形バッファ領域７２と同一条件で、厚膜ＨＶＰＭＯＳのｎ形ウエル領域７０を形成することで、図１と同様の効果が得られる。尚、図中のＥはエミッタ端子、Ｃはコレクタ端子である。
【００３６】
図５は、この発明の第４実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｄ）は工程順に示した要部製造工程断面図である。これは図１の半導体装置の製造方法である。
同図（ａ）において、ｎ形またはｐ形基板１とｎ形基板３を酸化膜２で貼り合わせたＳＯＩ基板１２３のｎ形基板３の表面層にｎ形ウエル領域７０とｐ形オフセット領域５０を形成する。ｎ形ウエル領域７０の不純物量を３×１０^１２ｃｍ^−２〜１×１０^１３ｃｍ^−２とする。また、不純物はＰ（リン）である。
同図（ｂ）において、ｎ形ウエル領域７０の表面層にｐ形ソース領域８０と、ｐ形オフセット領域５０上に絶縁膜１２を形成する。この絶縁膜１２はＬＯＣＯＳ酸化膜（選択酸化膜）である。
【００３７】
同図（ｃ）において、ｐ形ソース領域８０とｐ形オフセット領域５０に挟まれたｎ形基板３上とｎ形ウエル領域７０上に厚膜ゲート酸化膜１１を形成し、その４００ｎｍ程度の厚膜のゲート酸化膜１１上にポリシリコンのゲート電極１３を形成する。つぎに、ｎ形コンタクト領域９とｐ形ドレイン領域６を形成する。
同図（ｄ）において、ｐ形ソース領域８０上とｎ形コンタクト領域９上にソース電極１４を形成し、ｐ形ドレイン領域６上にドレイン電極１５を形成する。
図６は、この発明の第５実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｄ）は工程順に示した要部製造工程断面図である。これは図３の半導体装置の製造方法である。
【００３８】
同図（ａ）において、ＳＯＩ基板にトレンチ誘電体分離領域１７を形成し、分割されたｎ形基板３に、厚膜ゲートＨＶＰＭＯＳ１９のｎ形ウエル領域７０、ｐ形オフセット領域５０およびＣＭＯＳ回路２０のｐチャネルＭＯＳＦＥＴ２１のｎ形ウエル領域７１、ｎチャネルＭＯＳＦＥＴ２２のｐ形ウエル領域とをそれぞれ形成する。ｎ形ウエル領域７０の不純物量を３×１０^１２ｃｍ^−２〜１×１０^１３ｃｍ^−２とする。この不純物量はＣＭＯＳ回路２０のｐチャネルＭＯＳＦＥＴ２１のｎ形ウエル領域７１の不純物量（２×１０^１２ｃｍ^−２程度）より多い。また、不純物はＰ（リン）である。
【００３９】
同図（ｂ）において、ｎ形ウエル領域７０の表面層にｐ形ソース領域８０を形成し、ｐ形オフセット領域５０上とその他の表面に絶縁膜１２を選択的に形成する。この絶縁膜１２はＬＯＣＯＳ酸化膜（選択酸化膜）である。
同図（ｃ）において、ｐ形ソース領域８０とｐ形オフセット領域５０に挟まれたｎ形基板３上とｎ形ウエル領域７０上に４００ｎｍ程度の厚膜のゲート酸化膜１１を形成し、この厚膜のゲート酸化膜１１上にポリシリコンのゲート電極１３を形成する。つぎに、ｎ形コンタクト領域９とｐ形ドレイン領域６を形成する。また、ＣＭＯＳ回路２０を構成するｐチャネルＭＯＳＦＥＴ２１とｎチャネルＭＯＳＦＥＴ２２に２０ｎｍ程度の薄膜のゲート酸化膜３１、３２とポリシリコンでゲート電極３３、３４を形成し、ソース領域、ドレイン領域をそれぞれ形成する。
【００４０】
同図（ｄ）において、ｐ形ソース領域８０上とｎ形コンタクト領域９上にソース電極１４を形成し、ｐ形ドレイン領域６上にドレイン電極１５を形成する。また、ＣＭＯＳ回路２０のｐチャネルＭＯＳＦＥＴ２１のソース電極３５、ドレイン電極３８、ｎチャネルＭＯＳＦＥＴ２２のソース電極３６、ドレイン電極３７を形成する。
図７は、この発明の第６実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｄ）は工程順に示した要部製造工程断面図である。これは図４の半導体装置の製造方法である。
【００４１】
同図（ａ）において、ＳＯＩ基板にトレンチ誘電体分離領域１７を形成し、分割されたｎ形基板３に、厚膜ゲートＨＶＰＭＯＳ１９のｎ形ウエル領域７０、ｐ形オフセット領域５０および横型ＩＧＢＴ１８のｐ形ウエル領域、ｎ形バッファ領域７２を形成する。ｎ形ウエル領域７０とｎ形バッファ領域７２を同時に形成する。ｎ形ウエル領域７０およびｎ形バッファ領域の不純物量を３×１０^１２ｃｍ^−２〜１×１０^１３ｃｍ^−２とする。また、不純物はＰ（リン）である。
同図（ｂ）において、ｎ形ウエル領域７０の表面領域にｐ形ソース領域８０を形成し、ｐ形オフセット領域５０上とその他の表面に絶縁膜１２を選択的に形成する。この絶縁膜１２はＬＯＣＯＳ酸化膜（選択酸化膜）である。
【００４２】
同図（ｃ）において、ｐ形ソース領域８０とｐ形オフセット領域５０に挟まれたｎ形基板３上とｎ形ウエル領域７０上に４００ｎｍ程度の厚膜のゲート酸化膜１１を形成し、その厚膜ゲート酸化膜１１上にポリシリコンのゲート電極１３を形成する。つぎに、ｎ形コンタクト領域９とｐ形ドレイン領域６を形成する。また、横型ＩＧＢＴ１８の２０ｎｍ程度の薄膜ゲート酸化膜４１とポリシリコンでゲート電極４２を形成し、エミッタ領域、コンタクト領域、コレクタ領域をそれぞれ形成する。
同図（ｄ）において、ｐ形ソース領域８０上とｎ形コンタクト領域９上にソース電極１４を形成し、ｐ形ドレイン領域６上にドレイン電極１５を形成する。また、横型ＩＧＢＴ１８のエミッタ電極４３、コレクタ電極４４を形成する。
【００４３】
図５から図７の工程において、ｐ形ソース領域８０が形成された後、ｐ形ドレイン領域６が形成されるまでに８００℃から１１５０℃の高温の熱処理工程がある。そのため、ｐ形ソース領域８０の拡散深さは深くなるが、ｎ形ウエル領域７０の不純物量を前記の範囲とすることで、ｐ形オフセット領域５０とｎ形基板３とのｐｎ接合でのアバランシェブレークダウン電圧よりもパンチスルー電圧を高くしている。
ここで、前記の図１の半導体装置において、改善を要する事項についてつぎに説明する。
【００４４】
図８は図１の半導体装置の構成図であり、同図（ａ）は図１と同じ要部断面図、同図（ｂ）は、同図（ａ）のＷの領域の要部平面図である。図９は、図８の半導体装置の製造フローの概略説明図である。この半導体装置は前記したように厚膜ゲートＨＶＰＭＯＳである。
図８、図９において、ｐ形ソース領域にｐ形ドレイン領域を適用できる標準ゲートＨＶＰＭＯＳに対し、厚膜ゲートＨＶＰＭＯＳではゲート酸化膜形成工程前にｐ形ソース領域８０を形成しなければならない。これは厚膜ゲートのパターン形成を、ゲートポリシリコン１３を用いたセルフアラインで実施することが不可能であることによる。そのため、厚膜ゲートＨＶＰＭＯＳのｐ形ソース領域８０は図９で示す高温処理工程（フィールド酸化膜１２形成工程、ゲート酸化膜１１形成工程、ゲートポリシリコン１３形成工程など）を多く経験することになり、その拡散深さがｐ形ドレイン領域６をｐ形ソース領域８１に適用した標準ゲートＨＶＰＭＯＳに比べて深くなる。
【００４５】
また、ｐ形ソース領域８０はソース電極１４とコンタクトさせる必要がある。そのため、ｐ形ソース領域８０は図８のようにソース電極１４側に延在して形成しなければならない。つまり、ｐ形ソース領域８０の表面端はソース電極１４と少なくとも接するように、その横方向の拡散深さである拡散幅Ｌｐ１を長くしなければならない。（図８ではｎ形コンタクト領域１４にも接するように形成した図が描かれている）。このｐ形ソース領域８０とソース電極１４のコンタクトの様子を平面パターンで示したものが図８（ｂ）であり、この図８（ｂ）は図８（ａ）のソース・ゲート領域側（Ｗの領域）のみを表したものである。
【００４６】
ｐ形ソース領域８０は、前記したようにゲートポリシリコン１３のセルフアラインによって形成できないこと、また拡散深さが深いことからゲートポリシリコン１３との重なり幅（横方向の拡散深さ）が大きい。しかも、前記したように、このｐ形ソース領域８０は、ソース電極１４とコンタクトさせるためにソース電極１４側にも形成する必要がある。そのため、ｐ形ソース領域８０の平面的な拡散幅（図中のＬｐ１）は長くなる。
このように、厚膜ゲートＨＶＰＭＯＳはｐ形ソース層８０の拡散深さが深いため、ｎ形ウエル領域７０とｐ形ソース領域８０の深さ方向での拡散端距離ｄが小さくなる。そのため、ＳＯＩ基板１２３上のＨＶＰＭＯＳに高電圧を印加した時はｎ形ウエル領域７０中に延びる空乏層の先端とｎ形ウエル領域７０の拡散端との距離は小さくなる。そうすると、ｎ形ウエル領域７０の空乏化しない領域を通る電子の経路の断面積が小さくなり、それによって、ＳＯＩ基板１２３上に形成した厚膜ゲートＨＶＰＭＯＳの高電圧印加時には、ｐ形ソース領域８０直下におけるｎ形ウエル領域７０の抵抗Ｒｎが増加することになる。
【００４７】
この抵抗Ｒｎが増加すると、素子の高電圧印加時におけるホットキャリア（電離した電子）がｎ形ウエル領域８０を通してｎ形コンタクト領域９へ流れ、この電子流と抵抗Ｒｎの積で発生する電圧降下が増大する。この電圧降下が０．６Ｖを越えると、ｐ形ソース領域８０からｎ形ウエル領域８０へ正孔が注入され、電流が増大する。この電流の増大は２次降伏を引き起し、素子の耐圧特性が劣化することになる。特に、ゲートに電圧が印加されたオン時（例えば、ゲート電圧をドレイン電圧と同一にする時）の高電圧印加モードでは基板電流の発生量が増加するため、この２次降伏動作が促進されることになる。その結果、ゲートがオフ時の場合（例えば、ゲート電圧がソース電圧と同一の場合）に比べて耐圧特性の劣化が顕著になる。
【００４８】
このように、ＳＯＩ基板１２３上の厚膜ゲートＨＶＰＭＯＳでは、ｐ形ソース領域８０の拡散深さが深いこと、また高電圧印加時にｎ形ウエル領域７０の空乏化が進むことから２次降伏が起こりやい。特に、ゲートがオン状態では基板電流の増加により２次降伏の発生が促進され、素子の安全動作領域が狭くなるという問題が発生する。そのため、この２次降伏の発生を防止しなければならない。つぎに、これを、防止する方策について説明する。
図１０は、この発明の第７実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。
【００４９】
図８と異なるのは、ｐ形ソース領域８０がソース電極１４と直接コンタクトせず、高濃度のｐ形拡散領域８３（補助ｐ形ソース領域）を通して間接的にコンタクトされている点である。直接コンタクトさせる必要がないために、ｐ形ソース領域８０の拡散幅Ｌｐ１を図８より小さくすることができる。その結果、Ｒｎが小さくなり、高電圧印加時で、ゲート電極１３に負の電圧を印加してオン状態とした時にも、Ｒｎによる電圧降下が小さくなり、ｐ形ソース領域７０からｎ形ウエル領域８０への正孔の注入が抑制されて、２時降伏の発生が抑制され、安全動作領域を広げることができる。
【００５０】
また、高濃度のｐ形拡散領域８３をｐ形ドレイン領域６と同一の拡散領域を形成することにより、この拡散領域８３の拡散深さを浅くすることができる。その結果、ｎ形ウエル領域７０のｐ形拡散領域８３との接合部付近における抵抗（図１０（ｂ）中のＲｎ１）は小さくなり、Ｒｎに対して無視することができる。したがって、ｐ形ソース領域８０の拡散幅Ｌｐ１を小さくすることは、２次降伏防止に大きな効果を発揮する。
図１０では、拡散幅Ｌｐ１を図８の３．０μｍから１．０μｍ程度まで短縮することができる。また、高濃度のｐ形拡散領域８３をｐ形ドレイン領域６と同一の拡散領域で形成することにより、プロセス工程数の増加を招くことなく、本発明を適用することができる。
【００５１】
図１１は、この発明の第８実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ１−Ｘ１線で切断した要部断面図である。
ｐ形ソース領域８０をソース電極１４とコンタクトする高濃度のｐ形拡散領域８３がｎ形ウエル領域７０内に島状に形成されている。すなわち、ｐ形ソース領域８０がソース電極１４とコンタクトする領域は図中のＡ、Ｂ領域だけである。その他のｎ形ウエル領域７０内にはｎ形コンタクト領域９を形成することにより、ｎ形コンタクト領域９の形成領域を増加させている。ｎ形コンタクト領域９の形成領域をドレイン領域側に接近して形成できるので、２次降伏発生のトリガとなる基板電流のｎ形コンタクト領域からの引抜きが容易になる。その結果、２次降伏発生を図１０の場合より抑えることができる。
【００５２】
図１１の半導体装置においても図１０の半導体装置と同様に、高濃度のｐ形拡散領域８３をｐ形ドレイン領域６と同一の拡散領域で形成することにより、プロセス工程数の増加を招くことなく、本発明を適用することができる。
【００５３】
【発明の効果】
本発明によれば、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳにおいて、ｎ形ウエル領域の不純物量を調整することによって、ｐ形オフセット領域とｐ形ソース領域間のパンチスルー電圧を、ｐ形オフセット領域とｎ形基板のｐｎ接合のアバランシェブレークダウン電圧よりも高くする。また、ＣＭＯＳ回路を同一のＳＯＩ基板上に備えた場合では、厚膜ゲートＨＶＰＭＯＳのｎ形ウエル領域の不純物量を、ＣＭＯＳ回路を構成するｐチャネル形ＭＯＳＦＥＴのチャネル領域を形成するｎ形ウエル領域の不純物量よりも多くする。さらに、横形ＩＧＢＴを同一のＳＯＩ基板上に搭載する場合では、厚膜ゲートＨＶＰＭＯＳのｎ形ウエル領域に横形ＩＧＢＴのｎ形バッファ領域を適用する。
【００５４】
以上により、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳの耐圧設計が容易となり、素子の高耐圧化を実現することができる。
また、本発明によれば、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳのｐ形ソース領域を平面的に細く形成し、ソース電極とはｎ形ウエル領域内に形成された高濃度のｐ形拡散領域（補助ｐ形ソース領域）を介してコンタクトすることにより、ｐ形ソース領域の拡散幅を短縮することができて、ｐ形ソース領域直下のｎ形ウエル領域の抵抗を減少させることができる。
また、高濃度のｐ形拡散領域をｎ形ウエル領域内に島状に形成し、他の領域にはｎ形コンタクト領域を形成することにより、ｎ形コンタクト領域の形成領域を増加させることができる。その結果、２次降伏発生のトリガとなる基板電流の引き抜きが容易となり、２次降伏の発生を抑えることができる。
【００５５】
このようにすることにより、ＳＯＩ基板上に形成した厚膜ゲートＨＶＰＭＯＳの２次降伏の発生を防止することができて、素子の安全動作領域を向上させることができる。
また、高濃度のｐ形拡散領域をｐ形ドレイン領域と同一の拡散領域で形成することにより、プロセス工程数の増加を抑えることができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置の要部断面図
【図２】図１の素子構造におけるｐ形オフセット領域の長さＬｐと素子耐圧の関係を示す図
【図３】この発明の第２実施例の半導体装置の要部断面図
【図４】この発明の第３実施例の半導体装置の要部断面図
【図５】この発明の第４実施例の半導体装置の製造方法であり、（ａ）から（ｄ）は工程順に示した要部製造工程断面図
【図６】この発明の第５実施例の半導体装置の製造方法であり、（ａ）から（ｄ）は工程順に示した要部製造工程断面図
【図７】この発明の第６実施例の半導体装置の製造方法であり、（ａ）から（ｄ）は工程順に示した要部製造工程断面図
【図８】図１の半導体装置の構成図であり、（ａ）は図１と同じ要部断面図、（ｂ）は、（ａ）のＷの領域の要部平面図
【図９】図８の半導体装置の製造フローの概略説明図
【図１０】この発明の第７実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図
【図１１】この発明の第８実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ１−Ｘ１線で切断した要部断面図
【図１２】厚膜ゲートＨＶＰＭＯＳを適用したレベルシフト回路の一例を示す図
【図１３】ＨＶＰＭＯＳをＳＯＩ基板に形成した場合の半導体装置の要部断面図
【図１４】厚膜ゲート酸化膜と薄膜ゲート酸化膜でのイオン注入の様子を示す図
【図１５】ＳＯＩ基板上の標準ゲートＨＶＰＭＯＳのｐ形ドレイン領域６に−２８０Ｖの電圧を印加した場合の電位分布を示す図
【図１６】パンチスルーを防止する深い拡散領域を用いた素子構造の要部断面図
【符号の説明】
１　　　ｎ形あるいはｐ形半導体基板
２　　酸化膜
３　　　ｎ形半導体基板
４　　ｎ形ドリフト領域
６　　ｐ形ドレイン領域
９　　ｎ形コンタクト領域
１０　　チャネル形成領域
１１　　厚膜のゲート酸化膜
１２　　フィールド酸化膜
１３　　ゲート電極
１４　　ソース電極
１５　　ドレイン電極
１６　　等電位線
１７　　トレンチ分離領域
１８　　横形ＩＧＢＴ
１９　　厚膜ゲートＨＶＰＭＯＳ
２０　　ＣＭＯＳ回路
２１　　ｐチャネル形ＭＯＳＦＥＴ
２２　　ｎチャネル形ＭＯＳＦＥＴ
３１、３２　薄膜ゲート酸化膜
３３、３４　ゲート電極
３５、３６　ソース電極
３７、３８　ドレイン電極
４１　　薄膜のゲート酸化膜
４２　　ゲート電極
４３　　エミッタ電極
４４　　コレクタ電極
５０　　ｐ形オフセット領域
５１　　ｐ形拡散領域
７０、７１　ｎ形ウエル領域
７２　　ｎ形バッファ領域
７３　　ｎ形拡散領域
８０、８１、８２　ｐ形ソース領域
８３　　ｐ形拡散領域（補助ｐ形ソース領域）
１２３　　ＳＯＩ基板
Ａ　　出力回路部
Ｂ　　レベルシフト回路部
Ｎ１、Ｎ２　ＩＧＢＴ
Ｎ３、Ｎ４　ｎチャネル形ＭＯＳＦＥＴ
Ｐ１、Ｐ２　ｐチャネル形ＭＯＳＦＥＴ
ＺＤ　　ツェナーダイオード
ＶＨ　　出力側電源電圧
ＧＮＤ　　グランド電圧
Ｖｉｎ１、Ｖｉｎ２、Ｖｉｎ３　　入力信号
Ｖｏｕｔ　　出力信号
Ｌｐ　　ｐ形オフセット領域の長さ
ｄ　　ｎ形ウエル領域とｐ形ソース領域の深さ方向における拡散深さ
の差（拡散端の距離）
Ｌｐ１　拡散幅
Ｒｎ　　抵抗（ｐ形ソース領域直下）
Ｒｎ１　抵抗（補助ｐ形ソース領域直下）[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device such as a high-withstand-voltage lateral MOSFET formed on a bonded substrate (hereinafter abbreviated as an SOI substrate).
[0002]
[Prior art]
In recent years, with the progress of dielectric isolation technology combining an SOI substrate and trench isolation, high breakdown voltage devices such as lateral diodes, insulated gate bipolar transistors (hereinafter abbreviated as IGBTs), and lateral MOSFETs, and their drive, control, and protection. Power integrated circuits (hereinafter, abbreviated as power ICs) in which circuits are integrated on one silicon substrate have been actively developed.
A great advantage of manufacturing a power IC on a dielectric isolation substrate using an SOI substrate is that a bipolar device can be applied as a high-side switch, and that these devices can have multiple outputs. For this reason, as an inverter circuit for driving a three-phase motor or a driver IC for driving a flat panel display, an IC in which a plurality of totem pole circuits constituted by IGBTs are mounted on one chip as output circuits has been developed.
[0003]
When driving the high-side switch, a level shift circuit is required. By configuring this level shift circuit with a high-withstand-voltage horizontal p-channel MOSFET (hereinafter abbreviated as HVPMOS), it is possible to achieve a simple configuration that does not require a separate power supply or a capacitor. Moreover, by increasing the thickness of the gate oxide film of the HVPMOS, the HVPMOS can be directly driven by the output-side power supply voltage, and a CMOS level shift circuit combined with an n-channel MOSFET can be realized. As a result, low power consumption of the level shift circuit can be achieved.
Against this background, it is important to develop an HVPMOS having a thick gate oxide film that can withstand the application of the output-side power supply voltage, unlike the standard gate oxide film to which the input-side power supply voltage is applied. . In this specification, an HVPMOS provided with a gate oxide film having a standard thickness is referred to as a standard gate HVPMOS, and an HVPMOS provided with a thick gate oxide film is referred to as a thick gate HVPMOS.
[0004]
FIG. 12 is a diagram showing an example of a level shift circuit to which a thick gate HVPMOS is applied.
A totem pole circuit composed of two IGBTs (N1, N2) is mounted as the output circuit section A, and a level composed of two N-channel MOSFETs (N3, N4) and two HVPMOSs (P1, P2) at the preceding stage. The shift circuit section B is mounted. The output device N1 is controlled by Vin1, and N2 is controlled by signals of Vin2 and Vin3 for driving the level shift circuit. Note that ZD built in the output circuit section A is a Zener diode for protecting the gate of N2. Since a high voltage is applied to the output side power supply voltage VH, all devices other than the ZD constituting this circuit are high breakdown voltage devices.
[0005]
The level shift circuit B of this circuit is a known circuit, and the description of its operation is omitted here. The feature of this level shift circuit is that the gates of P1 and P2 can be driven by the output side power supply voltage VH. For this reason, the level shift circuit B can be configured by a normal CMOS circuit, and the power consumption of the level shift circuit B can be significantly reduced.
FIG. 13 is a cross-sectional view of a main part of a semiconductor device when HVPMOS is formed on an SOI substrate. The substrate on which each element is formed is an n-type substrate 3. This conductivity type is selected for the purpose of facilitating the formation of the n-channel type element constituting the output circuit of the power IC. Hereinafter, a description will be given of how to increase the breakdown voltage of the HVPMOS formed on the SOI substrate.
[0006]
In order to form the HVPMOS on the n-type substrate 3, the p-type offset region 50 is indispensable. The element breakdown voltage (element breakdown voltage) is determined by the avalanche breakdown voltage generated at the junction between the p-type offset region 50 and the n-type drift region 4, and this voltage depends on the formation conditions of the p-type offset region 50. . Therefore, the improvement of the resistance of the element is performed by optimizing the conditions for forming the p-type offset region 50.
The structural difference between the thick gate HVPMOS and the standard gate HVPMOS lies in the gate oxide film thickness and the step of forming the p-type source region. The thickness of the thick gate oxide film is determined by the magnitude of the output side power supply voltage, and its necessity is as described above.
[0007]
On the other hand, with respect to the step of forming the p-type source region, in the standard gate HVPMOS, after forming a thin gate oxide film, polysilicon serving as a gate electrode is patterned and the p-type source region 82 is formed using this polysilicon as a mask. Are formed in a self-aligned manner.
However, in the case of the thick-film gate HVPMOS, when the p-type source region 81 is formed by ion implantation and heat treatment using polysilicon serving as a gate electrode as a mask as in the conventional standard gate HVPMOS process, the gate electrode and the p-type As shown in FIG. 14, polysilicon must be patterned to be smaller than a thick gate oxide film in order to secure a withstand voltage between source regions. Is incompletely implanted, and a regular dose is not implanted in the semiconductor substrate. In addition, in the case of a thick gate oxide film, the pattern shape of the p-type source region 81 is deviated from the normal size because the etching residue of polysilicon and the residue of polysilicon adhere to the side surface. Therefore, the p-type source region 81 cannot be formed by self-alignment (forming the p-type source region using polysilicon as a gate electrode as a mask) like the p-type source region of the standard gate HVPMOS.
[0008]
In order to prevent this, if the p-type source region 81 of the thick gate HVPMOS is formed in advance before the p-type source region of the standard gate HVPMOS is formed, the p-type source region of the standard gate HVPMOS is formed. Before the heat treatment, a high-temperature heat treatment process is performed about six times, and the high-temperature heat treatment reduces the diffusion depth of the p-type source region 81 of the thick gate HVPMOS to the p-type source region 82 of the standard gate HVPMOS (see FIG. 13 (dotted line). As a result, the difference d between the diffusion depth of the n-type well region 70 and the diffusion depth of the p-type source region 81 decreases. Next, consider a high voltage application state of the HVPMOS formed on the SOI substrate.
[0009]
FIG. 15 is a diagram showing a potential distribution when a voltage of -280 V is applied to the p-type drain layer 6 of the standard gate HVPMOS on the SOI substrate. This is a result obtained by device simulation. Here, the region of the semiconductor substrate 1 is omitted. Although not shown, the potential distribution of the thick gate HVPMOS is similar to that of the present result.
As can be seen from this result, in the HVPMOS on the SOI substrate, equipotential lines inside the element when a high withstand voltage is applied concentrate on the n-type substrate 3 (n-type drift region) immediately below the n-type well region 70. Therefore, although not as large as the p-type offset region 50, the depletion of the n-type well region 70 due to the concentration of the equipotential lines progresses.
[0010]
As described above, in the thick-film gate HVPMOS, the diffusion depth of the p-type source region 81 is large. Therefore, the diffusion edge distance (d in FIG. 13) in the depth direction between the n-type well region 70 and the p-type source region 81 is reduced. Then, as shown in FIG. 15, when a high voltage is applied to the HVPMOS on the SOI substrate, the n-type well region 70 is easily depleted. Therefore, when a high voltage is applied to the thick gate HVPMOS formed on the SOI substrate, punch-through easily occurs between the p-type offset region 50 and the p-type source region 81 due to depletion of the n-type well region 70 in the depth direction. Become.
When this punch-through occurs, it becomes impossible to control the withstand voltage of the element by the conditions for forming the p-type offset region. For this reason, it becomes difficult to design the breakdown voltage of the element, that is, to increase the breakdown voltage of the element. Therefore, it is necessary to prevent this punch-through from occurring. Next, a method for preventing punch-through will be described.
[0011]
FIG. 16 is a sectional view of a main part of an element structure using a deep diffusion layer for preventing punch-through. This element includes an n-type well region 73 reaching the oxide film 2 of the SOI substrate and a p-type diffusion region 51. In this element, the diffusion end distance d in the depth direction between the p-type source region 81 and the n-type well region 73 is sufficiently long. Therefore, punch-through between the p-type diffusion region 51 and the p-type source region 81 caused by depletion in the depth direction of the n-type well region 73 does not occur.
However, in this element structure, the n-type diffusion region 73 (corresponding to the n-type well region 70) and the p-type diffusion region 51 (corresponding to the p-type offset region 50) must be diffused to the oxide film 2 of the SOI substrate. . For this reason, a long diffusion step is required, which leads to an increase in manufacturing lead time. Further, the long-time diffusion process has an effect on other devices of the power IC equipped with the present device. Therefore, the adoption of the element structure shown in FIG. 16 fundamentally changes the design of the device constituting the power IC. For example, a new development of a horizontal IGBT formed on the same substrate is also required. Therefore, it is necessary to establish a measure for preventing punch-through in the element structure shown in FIG.
[0012]
Further, in the high breakdown voltage lateral semiconductor device, the source electrode is formed on the gate electrode and the offset region by protruding the gate electrode, and by setting the protruding length to a predetermined length, the total charge amount in the p offset region is reduced. It has been reported that a high-breakdown-voltage p-channel MOSFET capable of increasing the breakdown voltage without causing the formation is formed on an SOI substrate (see Patent Document 1).
Further, in the high breakdown voltage lateral semiconductor device, the gate electrode is formed so as to extend on the offset region, and the length of the gate electrode formed on the offset region is set to a predetermined length. It has been reported that a high-breakdown-voltage p-channel MOSFET capable of increasing the breakdown voltage without lowering the power dissipation is formed on an SOI substrate (see Patent Document 2).
[0013]
[Patent Document 1]
JP-A-11-145462
[Patent Document 2]
JP-A-2000-252467
[0014]
[Problems to be solved by the invention]
As described above, in the thick gate HVPMOS formed on the SOI substrate, the diffusion depth of the p-type source region is large. Therefore, the distance between the n-type well region forming the channel region and the diffusion edge in the depth direction (FIG. 13D) is short. Further, when a high voltage is applied to the HVPMOS on the SOI substrate, equipotential lines inside the device concentrate on the n-type drift region immediately below the n-type well region.
Thus, in the thick gate HVPMOS on the SOI substrate, when a high voltage is applied, punch-through between the p-type offset region 50 and the p-type source region 81 due to depletion in the depth direction of the n-type well region 70 causes It is more likely to occur than avalanche breakdown at the pn junction between the n-type offset region 50 and the n-type substrate 3.
[0015]
When this punch-through occurs, it becomes impossible to control the withstand voltage of the element by the conditions for forming the p-type offset region. For this reason, it is not usually possible to design the withstand voltage of the element designed with the avalanche breakdown voltage. Therefore, prevention of the occurrence of the punch-through in the thick gate HVPMOS on the SOI substrate is a major problem.
An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device having a thick gate HVPMOS having a punch-through voltage higher than an avalanche breakdown voltage.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a first semiconductor substrate and a second semiconductor substrate are bonded via an insulating film, and the second semiconductor substrate is formed on a bonded substrate polished to a predetermined thickness. In the semiconductor device, a well region of the first conductivity type which is selectively formed on the surface of the second semiconductor base material and whose diffusion depth does not reach the insulating film, and a surface layer of the second semiconductor base material, A second conductivity type offset region selectively formed away from the well region; a second conductivity type source region selectively formed on a surface layer of the first conductivity type well region; and the offset region. A drain region of the second conductivity type selectively formed on the surface layer of the first region, a contact region of the first conductivity type selectively formed on the surface layer of the well region, and the source region and the offset region. On the second semiconductor substrate A gate electrode formed on the well region via a gate insulating film (this gate insulating film is thicker than a gate insulating film of a MOSFET such as a CMOS circuit formed on the same bonded substrate); A semiconductor device having a source electrode formed on a contact region and on the source region, and a drain electrode formed on the drain region,
When the source region has a deeper diffusion depth than the diffusion depth of the drain region, the impurity amount of the well region is a predetermined value, and a positive voltage is applied to the source electrode with respect to the drain electrode, A punch-through voltage reaching a depletion layer to the source region is higher than an avalanche breakdown voltage of a junction formed by the offset region and the second semiconductor substrate.
[0017]
The predetermined value of the impurity amount is 3 × 10 ¹² cm ^-2 With the above, 1 × 10 ^Thirteen cm ^-2 It is good to be the following.
In addition, the first semiconductor substrate and the second semiconductor substrate are bonded together via an insulating film, and the second semiconductor substrate is polished to a predetermined thickness on a bonded substrate. In a semiconductor device in which one MOSFET and a CMOS circuit having a lateral second conductive type second MOSFET are formed, the semiconductor device is selectively formed on a surface of the second semiconductor base material, and a diffusion depth reaches the insulating film. A first well region of a first conductivity type not to be formed, an offset region of a second conductivity type selectively formed on a surface layer of the second semiconductor base away from the first well region, and the first well region A source region of the second conductivity type selectively formed on the surface layer of the first region, a drain region of the second conductivity type selectively formed on the surface layer of the offset region, and a surface layer of the first well region. First conductive formed Formed on the second semiconductor base material and the first well region sandwiched between the contact region, the source region and the offset region via a gate insulating film thicker than the gate insulating film of the second MOSFET. A semiconductor device comprising a horizontal first MOSFET having a gate electrode, a source electrode formed on the contact region and the source region, and a drain electrode formed on the drain region.
When the amount of impurities in the first well region is larger than the amount of impurities in the second well region of the second MOSFET and a positive voltage is applied to the source electrode with respect to the drain electrode, the offset region and the The punch-through voltage at which the depletion layer reaches the source region is higher than the avalanche breakdown voltage of the junction formed by the second semiconductor substrate.
[0018]
The first semiconductor substrate and the second semiconductor substrate are bonded via an insulating film, and the second semiconductor substrate is polished to a predetermined thickness on a bonded substrate. And a lateral type insulated gate bipolar transistor having a first conductivity type channel having a buffer region of the first conductivity type, wherein the diffusion depth is formed selectively on the surface of the second semiconductor base material. A well region of the first conductivity type that does not reach the insulating film; an offset region of the second conductivity type selectively formed on the surface layer of the second semiconductor base away from the well region; A source region of the second conductivity type selectively formed on the surface layer of the region, a drain region of the second conductivity type selectively formed on the surface layer of the offset region, and a surface layer of the well region Is A gate insulating film thicker than a gate insulating film of the insulated gate bipolar transistor, on a contact region of the first conductivity type, and on the second semiconductor substrate and the well region sandwiched between the source region and the offset region; A semiconductor device comprising a lateral MOSFET having a gate electrode formed through the gate electrode, a source electrode formed on the contact region and the source region, and a drain electrode formed on the drain region. So,
When the amount of impurities in the well region is the same as the amount of impurities in the buffer region, and a positive voltage is applied to the source electrode with respect to the drain electrode, the offset region and the second semiconductor base are formed. The punch-through voltage at which the depletion layer reaches the source region is higher than the avalanche breakdown voltage of the junction to be formed.
[0019]
Further, in a method of manufacturing a semiconductor device in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is formed on a bonded substrate polished to a predetermined thickness. Forming a first conductivity type well region in which the diffusion depth does not reach the insulating film selectively on the surface of the second semiconductor substrate; and forming a well region on the surface layer of the second semiconductor substrate from the well region. Selectively forming a second conductivity type offset region apart from each other; selectively forming a second conductivity type source region in a surface layer of the first conductivity type well region; Forming a drain region of a second conductivity type in a surface layer; forming a contact region of a first conductivity type in a surface layer of the well region; and sandwiching the source region and the second semiconductor substrate. Form simultaneously on the well area Through a gate insulating film thicker than the gate insulating film of the MOSFET of the CMOS circuit to be formed (the gate insulating film is thicker than the gate insulating film of the MOSFET such as the CMOS circuit formed on the same bonded substrate). Forming a gate electrode via the formed gate electrode and the contact region, forming a source electrode on the contact region and the source region, and forming a drain electrode on the drain region And a method for manufacturing a semiconductor device having
When the diffusion depth of the source region is made deeper than the diffusion depth of the drain region and a positive voltage is applied to the source electrode with respect to the drain electrode, the drain region is formed by the offset region and the second semiconductor base material. And an impurity amount in the well region where a punch-through voltage at which a depletion layer reaches the source region is higher than an avalanche breakdown voltage of the junction.
[0020]
In addition, the first semiconductor substrate and the second semiconductor substrate are bonded together via an insulating film, and the second semiconductor substrate is polished to a predetermined thickness on a bonded substrate. In a method for manufacturing a semiconductor device in which one MOSFET and a CMOS circuit having a second MOSFET of a lateral second conductivity type channel are formed, a diffusion depth is selectively formed on a surface of the second semiconductor base material. Forming a first well region of the first conductivity type that does not reach; and selectively forming an offset region of the second conductivity type in the surface layer of the second semiconductor base away from the first well region. Selectively forming a source region of a second conductivity type in a surface layer of the first well region, forming a drain region of a second conductivity type in a surface layer of the offset region, On the surface layer of the area Forming a contact region of a first conductivity type; and forming a gate insulating film of the second MOSFET on the second semiconductor substrate and the first well region sandwiched between the source region and the offset region. Forming a gate electrode via a thicker gate insulating film; forming a source electrode on the contact region and the source region; and forming a drain electrode on the drain region. A method for manufacturing a semiconductor device including a first MOSFET, comprising:
When a positive voltage is applied to the source electrode with respect to the drain electrode, a punch in which a depletion layer reaches the source region is obtained from an avalanche breakdown voltage of a junction formed between the offset region and the second semiconductor substrate. The manufacturing method is such that the amount of impurities in the one well region is larger than the amount of impurities in the second well region of the second MOSFET so as to increase the through voltage.
[0021]
Further, the first semiconductor substrate and the second semiconductor substrate are bonded together via an insulating film, and the second semiconductor substrate is polished to a predetermined thickness on a bonded substrate. And a lateral type insulated gate bipolar transistor having a first conductivity type channel having a buffer region of the first conductivity type, wherein a diffusion depth is selectively formed on the surface of the second semiconductor substrate. Forming a well region of the first conductivity type that does not reach the insulating film, and selectively forming an offset region of the second conductivity type in the surface layer of the second semiconductor base away from the well region. Forming a source region of the second conductivity type selectively on the surface layer of the well region; forming a drain region of the second conductivity type on the surface layer of the offset region; Selectively forming a contact region of the first conductivity type in a surface layer; and forming the insulated gate bipolar transistor on the second semiconductor base and the well region sandwiched between the source region and the offset region. Forming a gate electrode through a gate insulating film thicker than the gate insulating film; forming a source electrode on the contact region and the source region; and forming a drain electrode on the drain region. A method for manufacturing a semiconductor device having a lateral MOSFET having
When the amount of impurities in the well region is the same as the amount of impurities in the buffer region, and a positive voltage is applied to the source electrode with respect to the drain electrode, the offset region and the second semiconductor base are formed. The impurity amount of the well region is made equal to the impurity amount of the buffer region so that the punch-through voltage at which the depletion layer reaches the source region is higher than the avalanche breakdown voltage of the junction to be formed. .
[0022]
The above contents will be further described. In order to increase the breakdown voltage of the thick-film gate HVPMOS formed on the SOI substrate, punch-through between the p-type offset region and the p-type source region can be prevented, and the device breakdown voltage can be controlled by the conditions for forming the p-type offset region. I have to do it. For this purpose, the punch-through voltage between the p-type offset region and the p-type source region may be higher than the avalanche breakdown voltage generated at the junction between the p-type offset region and the n-type drift region. This can be realized by adjusting the impurity amount (charge amount) of the n-type well region, and adjusting the impurity amount of the n-type well layer according to a desired breakdown voltage value, that is, the formation condition of the p-type offset region. do it.
[0023]
In the case where the CMOS circuit is provided on the same SOI substrate, the impurity amount of the n-type well region of the thick gate HVPMOS is reduced by the amount of impurities of the n-type well region forming the channel region of the p-channel MOSFET constituting the CMOS circuit. What is necessary is just to make it larger than the amount of impurities.
Furthermore, when the horizontal IGBT is mounted on the same SOI substrate, the n-type buffer layer of the horizontal IGBT may be applied to the n-type well region of the thick gate HVPMOS.
By the above means, it is possible to prevent punch-through between the p-type offset region and the p-type source region generated in the thick gate HVPMOS on the SOI substrate. As a result, the withstand voltage design of the element becomes easy, and the high withstand voltage of the element can be realized.
[0024]
Further, in a semiconductor device in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is formed on a bonded substrate polished to a predetermined thickness,
A first conductivity type well region selectively formed on the surface of the second semiconductor substrate and having a diffusion depth that does not reach the insulating film; and a surface layer of the second semiconductor substrate separated from the well region. An offset region of the second conductivity type selectively formed, a source region of the second conductivity type selectively formed on the surface layer of the well region of the first conductivity type, and a surface layer of the offset region. A drain region of the second conductivity type formed selectively; a contact region of the first conductivity type selectively formed on the surface layer of the well region; and the source region sandwiched between the source region and the contact region. An auxiliary source region of a first conductivity type having a higher concentration than the source region formed in the surface layer of the well region in connection with the second semiconductor substrate interposed between the source region and the offset region; The well region A gate electrode formed through a gate insulating film, a source electrode formed on the contact region and the auxiliary source region, and a drain electrode formed on the drain region. hand,
When the source region has a deeper diffusion depth than the diffusion depth of the drain region, the impurity amount of the well region is a predetermined value, and a positive voltage is applied to the source electrode with respect to the drain electrode, The punch-through voltage at which the depletion layer reaches the source region is higher than the avalanche breakdown voltage of the junction formed by the offset region and the second semiconductor substrate, and the diffusion depth of the auxiliary source region is increased by the diffusion depth of the source region. It shall be shallower than the depth.
[0025]
Further, when a positive voltage is applied to the source electrode with respect to the drain electrode and a negative voltage is applied to the gate electrode with respect to the source electrode (or when the gate electrode and the drain electrode are set to the same potential). The carrier flowing from the source region to the well region by a current flowing through the well region immediately below the source region and a voltage generated at a pn junction formed between the source region and the well region immediately below the source region. Is configured so as not to be injected.
Further, a voltage generated at a pn junction formed by the source region and the well region immediately below the source region is preferably 0.6 V or less.
[0026]
Further, the auxiliary source region is formed in an island shape, and the auxiliary source region formed in the island shape is connected to the source region and the source electrode.
Further, the auxiliary source region may be formed with the same impurity concentration and the same diffusion depth as the drain region.
In this way, even when a voltage equivalent to that of the drain is applied to the gate, injection of carriers from the source to the well is prevented, the element does not undergo secondary breakdown, and the forward safe operation area is widened. can do.
[Action]
As described above, a punch-through voltage between the p-type offset region and the p-type source region is generated at the junction between the p-type offset region and the n-type drift region by adjusting the impurity amount of the n-type well region. It may be higher than the avalanche breakdown voltage. Thereby, it is possible to realize a high breakdown voltage of the thick gate HVPMOS formed on the SOI substrate.
[0027]
Further, the p-type source region is formed thin in a plane, and is in contact with the source electrode via a high-concentration p-type diffusion region formed in the n-type well region. Thus, the diffusion width of the p-type source region can be reduced, and the resistance at the junction between the p-type source region and the n-type well region can be reduced.
Further, by forming a high-concentration p-type diffusion region in an n-type well region in an island shape and forming an n-type contact region in other regions, the formation region of the n-type contact region can be increased. . As a result, the substrate current that triggers the occurrence of secondary breakdown can be easily extracted at the n-type contact region connected to the source electrode, and the occurrence of secondary breakdown can be suppressed.
[0028]
By the above two actions, it is possible to prevent the secondary breakdown of the thick gate HVPMOS formed on the SOI substrate.
By forming the high-concentration p-type diffusion region with the same diffusion region as the p-type drain region, it is possible to suppress an increase in the number of process steps required for forming the present element.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. The same parts as those in FIG. 13 are denoted by the same reference numerals. An n-type well region 70 is formed in the surface layer of the n-type substrate 3 of the SOI substrate 123 in which the n-type or p-type substrate 1 and the n-type substrate 3 are bonded with the oxide film 2. A p-type offset region 50 is formed apart. The n-type substrate 3 where the n-type well region 70 and the p-type offset region 50 are not formed becomes the n-type drift region 4.
A p-type source region 80 is formed in a surface layer of the n-type well region 70, and a high-concentration p-type drain region 6 is formed in a surface layer of the p-type offset region 50. A high-concentration n-type contact region 9 is formed on the surface layer of the n-type well region 70 in contact with (or not in contact with) the p-type source region 80. A polysilicon gate electrode 13 is formed on the n-type substrate 3 and the n-type well region 70 between the p-type offset region 50 and the p-type source region 80 via the thick gate oxide film 11 to form a p-type gate electrode 13. The source electrode 14 is formed on the source region 80 and the n-type contact region 9, and the drain electrode 15 is formed on the drain region 6. An insulating film is formed on the p-type offset region 50, and the gate electrode 13 extends thereon. The thickness (about 400 nm) of the thick gate oxide film 11 is formed to be larger than the thickness (20 nm to 25 nm) of a gate oxide film of a MOSFET and a lateral IGBT of a CMOS circuit formed at the same time, not shown. I do. A portion of the n-type substrate 3 where the n-type well region 70 and the p-type offset region 50 are not formed becomes the n-type drift region 4.
[0030]
After the formation of the p-type source region 80, the heat treatment process is performed about five times until the p-type drain region 6 is formed. Therefore, the diffusion depth (about 1 μm) of the p-type source region 80 is (About 0.5 μm). Further, the impurity amount of the n-type well region 70 is set to 3 × 10 ¹² cm ^-2 Above 1 × 10 ^Thirteen cm ^-2 The following is assumed. Further, the length Lp of the p-type offset region is set to about 6 μm to 12 μm. In the figure, S is a source terminal, G is a gate terminal, and D is a drain terminal.
FIG. 2 is a diagram showing the relationship between the length Lp of the p-type offset region and the withstand voltage of the device in the device structure of FIG. In this element structure, the difference between the diffusion depth of the p-type source region 80 and the diffusion depth of the n-type well region 70 is about 2 μm, and the impurity amount of the p-type offset region 50 is 2 × 10 ¹² cm ^-2 It is.
[0031]
The impurity amount of the n-type well region 70 is 2 × 10 ¹² cm ^-2 In this case, the breakdown voltage did not depend on Lp, and showed a constant value of about 100 V. This value is a punch-through voltage between the p-type offset region 50 and the p-type source region 70. This result indicates that the impurity amount of the n-type well region 70 is 2 × 10 ¹² cm ^-2 With the device (1), the device withstand voltage is determined by the punch-through voltage, which indicates that it is not possible to control the formation condition of the p-type offset region 50, that is, changing the device withstand voltage by changing Lp.
When the amount of impurities in the n-type well region 70 is increased, the element breakdown voltage depends on Lp. The impurity amount of the n-type well region 70 is 5 × 10 ¹² cm ^-2 And 7.5 × 10 ¹² cm ^-2 Comparing the cases (1) and (2), Lp = 6 μm shows an element withstand voltage of about 140 V. When Lp is increased, 5 × 10 ¹² cm ^-2 The element withstand voltage is saturated at about 150 V, whereas 7.5 × 10 ¹² cm ^-2 With the impurity amount of, the voltage was increased to about 220 V and then saturated. In the range where the element withstand voltage is increasing, avalanche breakdown occurs, and the element withstand voltage becomes an avalanche breakdown voltage. On the other hand, in the range showing the saturation value, punch-through occurs, and the element withstand voltage becomes the punch-through voltage.
[0032]
Here, for example, the impurity amount of the n-type well region 70 is set to 7.5 × 10 ¹² cm ^-2 With the above setting, the element breakdown voltage can be controlled under the conditions for forming the p-type offset region 50 (such as increasing Lp) up to a punch-through voltage of 220 V. That is, by adjusting the impurity amount of the n-type well region 70, avalanche breakdown occurs at the junction between the p-type offset region 50 and the n-type drift region 4, and a stable element withstand voltage can be obtained. Further, the withstand voltage design of the thick gate HVPMOS on the SOI substrate is facilitated.
Here, the amount of impurities in the n-type well region 70 can be summarized as follows. The impurity amount of the n-type well region 70 is 3 × 10 ¹² cm ^-2 If the value is less than 1, the element withstand voltage becomes a punch-through generation voltage, and the element withstand voltage cannot be increased. On the other hand, 1 × 10 ^Thirteen cm ^-2 Is exceeded, the impurity concentration in the channel formation portion of the n-type well region 70 becomes high, and the gate threshold voltage becomes too high.
[0033]
Therefore, in the semiconductor device of the present invention, the impurity amount of the n-type ¹² cm ^-2 With the above, 1 × 10 ^Thirteen cm ^-2 The following is assumed. Preferably, 4 × 10 ¹² cm ^-2 With the above, 7.5 × 10 ¹² cm ^-2 The following is recommended. The length Lp of the p-type offset region is preferably about 6 μm to 12 μm.
FIG. 3 is a sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention. This figure shows a case where the horizontal thick film gate HVPMOS of FIG. 1 and the n-type and p-type MOSFETs of the CMOS circuit are formed on an SOI substrate.
FIG. 2 is a cross-sectional view of a main part when a power IC is formed on a dielectric isolation substrate formed by an SOI substrate 123 and a trench dielectric isolation 17, and here, a horizontal thick film gate HVPMOS and a CMOS circuit of FIG. 1 are configured. FIG. 3 is a diagram in which an n-channel MOSFET and a p-channel MOSFET with low breakdown voltage are formed.
[0034]
In this power IC, a thick-film gate HVPMOS 19 and a low-breakdown-voltage p-channel MOSFET 21 and an n-channel MOSFET 22 constituting a CMOS circuit 20 are formed in two semiconductor regions formed by the trench dielectric isolation 17. Since the p-channel MOSFET 21 of the CMOS circuit 20 has a low withstand voltage, the impurity amount of the n-type well region 71 is 2 × 10 ¹² cm ^-2 It is about. On the other hand, by making the impurity amount of the n-type well region 70 of the thick film gate HVPMOS 19 larger than the impurity amount of the n-type well region 71 and in the range described with reference to FIG.
[0035]
FIG. 4 is a sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention. The case where a power IC is formed on a dielectric isolation substrate constituted by an SOI substrate 123 and a trench isolation 17 is shown. In this power IC, a lateral IGBT 18 and a thick gate HVPMOS 19 are formed in two semiconductor regions formed by a trench dielectric isolation 17.
In the horizontal IGBT 18, the formation of the n-type buffer region 72 is indispensable for ensuring the withstand voltage. The impurity amount of this n-type buffer region 72 is set to 3 × 10 ¹² cm ^-2 As described above, the element breakdown voltage of the IGBT can be ensured. Therefore, by forming the n-type well region 70 of the thick film HVPMOS under the same conditions as the n-type buffer region 72, the same effect as in FIG. 1 can be obtained. In the figure, E is an emitter terminal, and C is a collector terminal.
[0036]
FIGS. 5A to 5D show a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIGS. This is a method for manufacturing the semiconductor device of FIG.
In FIG. 1A, an n-type well region 70 and a p-type offset region 50 are provided on a surface layer of an n-type substrate 3 of an SOI substrate 123 in which an n-type or p-type substrate 1 and an n-type substrate 3 are bonded with an oxide film 2. To form The impurity amount of the n-type well region 70 is set to 3 × 10 ¹² cm ^-2 ~ 1 × 10 ^Thirteen cm ^-2 And The impurity is P (phosphorus).
In FIG. 2B, a p-type source region 80 is formed on the surface layer of the n-type well region 70, and an insulating film 12 is formed on the p-type offset region 50. This insulating film 12 is a LOCOS oxide film (selective oxide film).
[0037]
In FIG. 3C, a thick gate oxide film 11 is formed on the n-type substrate 3 and the n-type well region 70 sandwiched between the p-type source region 80 and the p-type offset region 50, and has a thickness of about 400 nm. A polysilicon gate electrode 13 is formed on the gate oxide film 11. Next, an n-type contact region 9 and a p-type drain region 6 are formed.
In FIG. 4D, the source electrode 14 is formed on the p-type source region 80 and the n-type contact region 9, and the drain electrode 15 is formed on the p-type drain region 6.
FIGS. 6A to 6D show a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. FIGS. This is a method for manufacturing the semiconductor device of FIG.
[0038]
3A, a trench dielectric isolation region 17 is formed in an SOI substrate, and an n-type well region 70, a p-type offset region 50 and a CMOS circuit 20 of a thick gate HVPMOS 19 are formed in the divided n-type substrate 3. An n-type well region 71 of the p-channel MOSFET 21 and a p-type well region of the n-channel MOSFET 22 are formed. The impurity amount of the n-type well region 70 is set to 3 × 10 ¹² cm ^-2 ~ 1 × 10 ^Thirteen cm ^-2 And This impurity amount is the impurity amount (2 × 10 4) of the n-type well region 71 of the p-channel MOSFET 21 of the CMOS circuit 20. ¹² cm ^-2 Degree) more. The impurity is P (phosphorus).
[0039]
In FIG. 3B, a p-type source region 80 is formed in a surface layer of the n-type well region 70, and an insulating film 12 is selectively formed on the p-type offset region 50 and other surfaces. This insulating film 12 is a LOCOS oxide film (selective oxide film).
4C, a thick gate oxide film 11 of about 400 nm is formed on the n-type substrate 3 and the n-type well region 70 sandwiched between the p-type source region 80 and the p-type offset region 50. A polysilicon gate electrode 13 is formed on the thick gate oxide film 11. Next, an n-type contact region 9 and a p-type drain region 6 are formed. Further, gate electrodes 33 and 34 of thin gate oxide films 31 and 32 of about 20 nm and polysilicon are formed on the p-channel MOSFET 21 and the n-channel MOSFET 22 constituting the CMOS circuit 20, and a source region and a drain region are formed respectively.
[0040]
In FIG. 4D, the source electrode 14 is formed on the p-type source region 80 and the n-type contact region 9, and the drain electrode 15 is formed on the p-type drain region 6. Further, a source electrode 35 and a drain electrode 38 of the p-channel MOSFET 21 of the CMOS circuit 20 and a source electrode 36 and a drain electrode 37 of the n-channel MOSFET 22 are formed.
FIGS. 7A to 7D show a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIGS. This is a method for manufacturing the semiconductor device of FIG.
[0041]
In FIG. 2A, a trench dielectric isolation region 17 is formed in an SOI substrate, and an n-type well region 70 of a thick gate HVPMOS 19, a p-type offset region 50, and a p-type of a lateral IGBT 18 are formed in the divided n-type substrate 3. A well region and an n-type buffer region 72 are formed. The n-type well region 70 and the n-type buffer region 72 are formed simultaneously. The impurity amount of the n-type well region 70 and the n-type buffer region is 3 × 10 ¹² cm ^-2 ~ 1 × 10 ^Thirteen cm ^-2 And The impurity is P (phosphorus).
In FIG. 3B, a p-type source region 80 is formed in the surface region of the n-type well region 70, and the insulating film 12 is selectively formed on the p-type offset region 50 and other surfaces. This insulating film 12 is a LOCOS oxide film (selective oxide film).
[0042]
4C, a thick gate oxide film 11 of about 400 nm is formed on the n-type substrate 3 and the n-type well region 70 sandwiched between the p-type source region 80 and the p-type offset region 50. A polysilicon gate electrode 13 is formed on the thick gate oxide film 11. Next, an n-type contact region 9 and a p-type drain region 6 are formed. Further, a gate electrode 42 is formed of a thin gate oxide film 41 of about 20 nm of the lateral IGBT 18 and polysilicon, and an emitter region, a contact region, and a collector region are respectively formed.
In FIG. 4D, the source electrode 14 is formed on the p-type source region 80 and the n-type contact region 9, and the drain electrode 15 is formed on the p-type drain region 6. Further, the emitter electrode 43 and the collector electrode 44 of the horizontal IGBT 18 are formed.
[0043]
In the steps of FIGS. 5 to 7, there is a high-temperature heat treatment step of 800 ° C. to 1150 ° C. after the p-type source region 80 is formed and before the p-type drain region 6 is formed. Therefore, the diffusion depth of the p-type source region 80 is increased, but by setting the impurity amount of the n-type well region 70 within the above range, the avalanche at the pn junction between the p-type offset region 50 and the n-type substrate 3 is obtained. The punch-through voltage is higher than the breakdown voltage.
Here, items requiring improvement in the semiconductor device of FIG. 1 will be described below.
[0044]
8A and 8B are configuration diagrams of the semiconductor device of FIG. 1, wherein FIG. 8A is a cross-sectional view of a main part same as FIG. 1, and FIG. 8B is a plan view of a main part of a region W in FIG. It is. FIG. 9 is a schematic explanatory diagram of the manufacturing flow of the semiconductor device of FIG. This semiconductor device is a thick gate HVPMOS as described above.
8 and 9, the p-type source region 80 must be formed before the gate oxide film forming step in the thick gate HVPMOS, as opposed to the standard gate HVPMOS in which the p-type drain region can be applied to the p-type source region. This is because it is impossible to form the pattern of the thick film gate by self-alignment using the gate polysilicon 13. Therefore, the p-type source region 80 of the thick gate HVPMOS experiences many high-temperature processing steps (the step of forming the field oxide film 12, the step of forming the gate oxide film 11, and the step of forming the gate polysilicon 13) shown in FIG. The diffusion depth is larger than that of the standard gate HVPMOS in which the p-type drain region 6 is applied to the p-type source region 81.
[0045]
Further, the p-type source region 80 needs to be in contact with the source electrode 14. Therefore, the p-type source region 80 must be formed to extend toward the source electrode 14 as shown in FIG. That is, the diffusion width Lp1, which is the lateral diffusion depth, must be increased so that the surface end of the p-type source region 80 is at least in contact with the source electrode 14. (FIG. 8 illustrates a diagram formed so as to be in contact with the n-type contact region 14 as well). FIG. 8B shows the state of the contact between the p-type source region 80 and the source electrode 14 in a plane pattern, and FIG. 8B shows the source / gate region side (W Area).
[0046]
As described above, the p-type source region 80 cannot be formed by the self-alignment of the gate polysilicon 13 and has a large diffusion depth, so that an overlap width (lateral diffusion depth) with the gate polysilicon 13 is large. Moreover, as described above, the p-type source region 80 needs to be formed also on the source electrode 14 side in order to make contact with the source electrode 14. Therefore, the planar diffusion width (Lp1 in the figure) of the p-type source region 80 becomes longer.
As described above, in the thick-film gate HVPMOS, since the diffusion depth of the p-type source layer 80 is large, the diffusion end distance d in the depth direction between the n-type well region 70 and the p-type source region 80 decreases. Therefore, when a high voltage is applied to the HVPMOS on the SOI substrate 123, the distance between the tip of the depletion layer extending into the n-type well region 70 and the diffusion end of the n-type well region 70 decreases. Then, the cross-sectional area of the path of electrons passing through the non-depleted region of n-type well region 70 is reduced, so that when a high voltage is applied to thick-film gate HVPMOS formed on SOI substrate 123, it is directly below p-type source region 80. In this case, the resistance Rn of the n-type well region 70 increases.
[0047]
When the resistance Rn increases, hot carriers (ionized electrons) at the time of applying a high voltage to the element flow through the n-type well region 80 to the n-type contact region 9, and a voltage drop generated by the product of this electron flow and the resistance Rn is reduced. Increase. When this voltage drop exceeds 0.6 V, holes are injected from p-type source region 80 into n-type well region 80, and the current increases. This increase in current causes secondary breakdown, which degrades the breakdown voltage characteristics of the device. In particular, in a high-voltage application mode when a voltage is applied to the gate (for example, when the gate voltage is made equal to the drain voltage), the amount of generation of the substrate current increases, and this secondary breakdown operation is promoted. Will be. As a result, the deterioration of the breakdown voltage characteristics becomes more remarkable as compared with the case where the gate is off (for example, the case where the gate voltage is the same as the source voltage).
[0048]
As described above, in the thick gate HVPMOS on the SOI substrate 123, the secondary breakdown occurs because the diffusion depth of the p-type source region 80 is deep and the depletion of the n-type well region 70 proceeds when a high voltage is applied. Yeah. In particular, when the gate is in the ON state, the occurrence of the secondary breakdown is promoted by the increase in the substrate current, which causes a problem that the safe operation area of the element is narrowed. Therefore, it is necessary to prevent the secondary breakdown from occurring. Next, measures to prevent this will be described.
10A and 10B are configuration diagrams of a semiconductor device according to a seventh embodiment of the present invention. FIG. 10A is a plan view of a main part, and FIG. 10B is a cross-sectional view taken along line XX of FIG. It is principal part sectional drawing.
[0049]
The difference from FIG. 8 is that the p-type source region 80 is not in direct contact with the source electrode 14 but is indirectly contacted through the high-concentration p-type diffusion region 83 (auxiliary p-type source region). Since there is no need to make direct contact, the diffusion width Lp1 of the p-type source region 80 can be made smaller than that in FIG. As a result, Rn is reduced, and when a high voltage is applied and a negative voltage is applied to the gate electrode 13 to turn on the gate electrode 13, the voltage drop due to Rn is reduced, and the p-type source region 70 to the n-type well region Injection of holes into 80 is suppressed, occurrence of 2 o'clock breakdown is suppressed, and a safe operation area can be expanded.
[0050]
Further, by forming the high-concentration p-type diffusion region 83 in the same diffusion region as the p-type drain region 6, the diffusion depth of the diffusion region 83 can be reduced. As a result, the resistance (Rn1 in FIG. 10B) near the junction of the n-type well region 70 with the p-type diffusion region 83 becomes small and can be ignored with respect to Rn. Therefore, reducing the diffusion width Lp1 of the p-type source region 80 has a significant effect on preventing secondary breakdown.
In FIG. 10, the diffusion width Lp1 can be reduced from 3.0 μm in FIG. 8 to about 1.0 μm. Further, by forming the high-concentration p-type diffusion region 83 with the same diffusion region as the p-type drain region 6, the present invention can be applied without increasing the number of process steps.
[0051]
11A and 11B are configuration diagrams of a semiconductor device according to an eighth embodiment of the present invention. FIG. 11A is a plan view of a main part, and FIG. 11B is a sectional view taken along line X1-X1 of FIG. It is principal part sectional drawing.
A high-concentration p-type diffusion region 83 that contacts the p-type source region 80 with the source electrode 14 is formed in the n-type well region 70 in an island shape. That is, the regions where the p-type source region 80 contacts the source electrode 14 are only the A and B regions in the figure. The formation region of the n-type contact region 9 is increased by forming the n-type contact region 9 in the other n-type well region 70. Since the formation region of the n-type contact region 9 can be formed close to the drain region side, it is easy to extract the substrate current that triggers the secondary breakdown from the n-type contact region. As a result, the occurrence of secondary breakdown can be suppressed as compared with the case of FIG.
[0052]
In the semiconductor device of FIG. 11, similarly to the semiconductor device of FIG. 10, the high-concentration p-type diffusion region 83 is formed of the same diffusion region as the p-type drain region 6 without increasing the number of process steps. The present invention can be applied.
[0053]
【The invention's effect】
According to the present invention, the punch-through voltage between the p-type offset region and the p-type source region can be reduced by adjusting the impurity amount of the n-type well region in the thick-film gate HVPMOS formed on the SOI substrate. It is set higher than the avalanche breakdown voltage of the pn junction between the region and the n-type substrate. In the case where the CMOS circuit is provided on the same SOI substrate, the impurity amount of the n-type well region of the thick gate HVPMOS is reduced by the amount of impurities of the n-type well region forming the channel region of the p-channel MOSFET constituting the CMOS circuit. More than the amount of impurities. Further, when the horizontal IGBT is mounted on the same SOI substrate, the n-type buffer region of the horizontal IGBT is applied to the n-type well region of the thick gate HVPMOS.
[0054]
As described above, the withstand voltage design of the thick-film gate HVPMOS formed on the SOI substrate is facilitated, and the withstand voltage of the element can be increased.
Further, according to the present invention, the p-type source region of the thick gate HVPMOS formed on the SOI substrate is formed to be thin in a plane, and the source electrode is defined by the high concentration p-type diffusion formed in the n-type well region. By making contact via the region (auxiliary p-type source region), the diffusion width of the p-type source region can be reduced, and the resistance of the n-type well region immediately below the p-type source region can be reduced.
Further, by forming a high-concentration p-type diffusion region in an n-type well region in an island shape and forming an n-type contact region in other regions, the formation region of the n-type contact region can be increased. . As a result, the substrate current that triggers the occurrence of secondary breakdown can be easily extracted, and the occurrence of secondary breakdown can be suppressed.
[0055]
By doing so, it is possible to prevent the secondary breakdown of the thick gate HVPMOS formed on the SOI substrate, and to improve the safe operation area of the device.
Further, by forming the high-concentration p-type diffusion region with the same diffusion region as the p-type drain region, an increase in the number of process steps can be suppressed.
[Brief description of the drawings]
FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a diagram showing the relationship between the length Lp of a p-type offset region and the withstand voltage of the device in the device structure of FIG.
FIG. 3 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;
FIG. 4 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention;
FIGS. 5A to 5D are cross-sectional views of a main part manufacturing process shown in the order of processes, showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention; FIGS.
6 (a) to 6 (d) are cross-sectional views of a main part manufacturing process shown in the order of processes, showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.
7A to 7D are cross-sectional views of a main part manufacturing process shown in a process order, showing a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention;
FIGS. 8A and 8B are configuration diagrams of the semiconductor device of FIG. 1, in which FIG. 8A is a cross-sectional view of the same main part as that of FIG. 1, and FIG.
FIG. 9 is a schematic explanatory view of a manufacturing flow of the semiconductor device of FIG. 8;
FIGS. 10A and 10B are configuration diagrams of a semiconductor device according to a seventh embodiment of the present invention, wherein FIG. 10A is a plan view of a main part, and FIG. 10B is a cross-sectional view of the main part taken along line XX of FIG.
11A and 11B are configuration diagrams of a semiconductor device according to an eighth embodiment of the present invention, wherein FIG. 11A is a plan view of a main part, and FIG. 11B is a cross-sectional view of the main part cut along line X1-X1 in FIG.
FIG. 12 is a diagram illustrating an example of a level shift circuit to which a thick gate HVPMOS is applied;
FIG. 13 is a cross-sectional view of a main part of a semiconductor device when an HVPMOS is formed on an SOI substrate.
FIG. 14 is a diagram showing a state of ion implantation in a thick gate oxide film and a thin gate oxide film.
FIG. 15 is a diagram showing a potential distribution when a voltage of −280 V is applied to the p-type drain region 6 of the standard gate HVPMOS on the SOI substrate;
FIG. 16 is a sectional view of an essential part of an element structure using a deep diffusion region for preventing punch-through;
[Explanation of symbols]
1 n-type or p-type semiconductor substrate
2 oxide film
3 n-type semiconductor substrate
4 N-type drift region
6 p-type drain region
9 N-type contact area
10 Channel formation area
11 Thick gate oxide film
12 Field oxide film
13 Gate electrode
14 Source electrode
15 Drain electrode
16 equipotential lines
17 Trench isolation region
18 Horizontal IGBT
19 Thick film HVPMOS
20 CMOS circuit
21 p-channel MOSFET
22 n-channel MOSFET
31, 32 Thin gate oxide film
33, 34 Gate electrode
35, 36 Source electrode
37, 38 Drain electrode
41 Thin gate oxide film
42 Gate electrode
43 Emitter electrode
44 Collector electrode
50 p-type offset area
51 p-type diffusion region
70, 71 n-type well region
72 n-type buffer area
73 n-type diffusion region
80, 81, 82 p-type source region
83 p-type diffusion region (auxiliary p-type source region)
123 SOI substrate
A Output circuit
B level shift circuit
N1, N2 IGBT
N3, N4 n-channel MOSFET
P1, P2 p-channel MOSFET
ZD Zener diode
VH Output side power supply voltage
GND ground voltage
Vin1, Vin2, Vin3 input signal
Vout output signal
Lp Length of p-type offset area
Diffusion depth in the depth direction of n-type well region and p-type source region
Difference (distance of diffusion edge)
Lp1 Diffusion width
Rn resistance (directly below the p-type source region)
Rn1 resistor (directly below the auxiliary p-type source region)

Claims

In a semiconductor device in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is formed on a bonded substrate polished to a predetermined thickness,
A first conductivity type well region selectively formed on the surface of the second semiconductor substrate and having a diffusion depth that does not reach the insulating film; and a surface layer of the second semiconductor substrate separated from the well region. An offset region of the second conductivity type selectively formed, a source region of the second conductivity type selectively formed on the surface layer of the well region of the first conductivity type, and a surface layer of the offset region. A second conductivity type drain region formed selectively, a first conductivity type contact region selectively formed on a surface layer of the well region, and the second conductivity type sandwiched between the source region and the offset region. A gate electrode formed on the semiconductor substrate and the well region via a gate insulating film; a source electrode formed on the contact region and the source region; and a drain formed on the drain region. Electrodes and A semiconductor device having,
When the source region has a deeper diffusion depth than the diffusion depth of the drain region, the impurity amount of the well region is a predetermined value, and a positive voltage is applied to the source electrode with respect to the drain electrode, A semiconductor device, wherein a punch-through voltage at which a depletion layer reaches the source region is higher than an avalanche breakdown voltage of a junction formed by the offset region and the second semiconductor substrate.

The semiconductor device according to claim 1, wherein the predetermined value of the impurity amount is 3 × 10 ¹² cm ⁻² or more and 1 × 10 ¹³ cm ⁻² or less.

The first semiconductor substrate and the second semiconductor substrate are bonded via an insulating film, and the second semiconductor substrate is polished to a predetermined thickness on a bonded substrate. , A CMOS circuit having a lateral second conductivity type channel second MOSFET, wherein:
A first well region of a first conductivity type which is selectively formed on the surface of the second semiconductor substrate and whose diffusion depth does not reach the insulating film; and a first well region on a surface layer of the second semiconductor substrate. An offset region of the second conductivity type selectively formed away from the region, a source region of the second conductivity type selectively formed on the surface layer of the first well region, and a surface layer of the offset region. A drain region of the second conductivity type selectively formed, a contact region of the first conductivity type selectively formed on the surface layer of the first well region, and the source region and the offset region; A gate electrode formed on the second semiconductor base material and the first well region via a gate insulating film thicker than a gate insulating film of the second MOSFET; and formed on the contact region and the source region. Source A semiconductor device having a first 1MOSFET lateral with the pole, and a drain electrode formed on said drain region,
When the amount of impurities in the first well region is larger than the amount of impurities in the second well region of the second MOSFET and a positive voltage is applied to the source electrode with respect to the drain electrode, the offset region and the A semiconductor device, wherein a punch-through voltage reaching a depletion layer to the source region is higher than an avalanche breakdown voltage of a junction formed by a second semiconductor substrate.

A horizontal second conductivity type MOSFET on a bonded substrate in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is polished to a predetermined thickness; In a semiconductor device in which a horizontal first conductivity type channel insulated gate bipolar transistor having a first conductivity type buffer region is formed,
A first conductivity type well region selectively formed on the surface of the second semiconductor substrate and having a diffusion depth that does not reach the insulating film; and a surface layer of the second semiconductor substrate separated from the well region. An offset region of the second conductivity type selectively formed, a source region of the second conductivity type selectively formed on the surface layer of the well region, and selectively formed on the surface layer of the offset region. A drain region of a second conductivity type, a contact region of a first conductivity type selectively formed in a surface layer of the well region, and a portion on the second semiconductor substrate sandwiched between the source region and the offset region. A gate electrode formed on the well region via a gate insulating film thicker than a gate insulating film of the insulated gate bipolar transistor; and a source electrode formed on the contact region and the source region. , A semiconductor device having a lateral MOSFET having a drain electrode formed on said drain region,
When the amount of impurities in the well region is the same as the amount of impurities in the buffer region, and a positive voltage is applied to the source electrode with respect to the drain electrode, the offset region and the second semiconductor base are formed. A punch-through voltage at which a depletion layer reaches the source region is higher than an avalanche breakdown voltage of a junction to be formed.

In a method of manufacturing a semiconductor device in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is formed on a bonded substrate polished to a predetermined thickness,
Forming a well region of the first conductivity type in which the diffusion depth does not reach the insulating film selectively on the surface of the second semiconductor substrate; and separating the well region from the well region on the surface layer of the second semiconductor substrate. Selectively forming a second conductivity type offset region, selectively forming a second conductivity type source region on a surface layer of the first conductivity type well region, and forming a surface of the offset region. Forming a drain region of the second conductivity type in the layer; forming a contact region of the first conductivity type in the surface layer of the well region; and forming the contact region between the source region and the second semiconductor substrate. A semiconductor device comprising: forming a gate electrode on a well region via a gate insulating film; and forming a source electrode on the contact region and the source region and a drain electrode on the drain region. A manufacturing method,
When the diffusion depth of the source region is made deeper than the diffusion depth of the drain region and a positive voltage is applied to the source electrode with respect to the drain electrode, the drain region is formed by the offset region and the second semiconductor base material. Wherein the amount of impurities in the well region is such that the punch-through voltage at which the depletion layer reaches the source region is higher than the avalanche breakdown voltage of the junction.

The first semiconductor substrate and the second semiconductor substrate are bonded via an insulating film, and the second semiconductor substrate is polished to a predetermined thickness on a bonded substrate. And a CMOS circuit having a horizontal second conductivity type channel and a second MOSFET formed therein.
Selectively forming a first well region of a first conductivity type whose diffusion depth does not reach the insulating film on the surface of the second semiconductor substrate; and forming the first well region on the surface layer of the second semiconductor substrate. Selectively forming a second conductivity type offset region away from the one well region; selectively forming a second conductivity type source region in a surface layer of the first well region; Forming a second conductivity type drain region on the surface layer of the first well region; selectively forming a first conductivity type contact region on the surface layer of the first well region; Forming a gate electrode on the sandwiched second semiconductor substrate and the first well region via a gate insulating film thicker than a gate insulating film of the second MOSFET; and forming a gate electrode on the contact region and the source region. On and on The over scan electrode, a manufacturing method of a semiconductor device having a first 1MOSFET lateral and a step of forming a drain electrode on said drain region,
When a positive voltage is applied to the source electrode with respect to the drain electrode, a punch in which a depletion layer reaches the source region is obtained from an avalanche breakdown voltage of a junction formed between the offset region and the second semiconductor substrate. A method of manufacturing a semiconductor device, wherein an amount of impurities in the one well region is made larger than an amount of impurities in a second well region of the second MOSFET so as to increase a through voltage.

A horizontal second conductivity type MOSFET on a bonded substrate in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is polished to a predetermined thickness; A method of manufacturing a semiconductor device in which a lateral first conductivity type channel insulated gate bipolar transistor having a first conductivity type buffer region is formed.
Forming a well region of the first conductivity type in which the diffusion depth does not reach the insulating film selectively on the surface of the second semiconductor substrate; and separating the well region from the well region on the surface layer of the second semiconductor substrate. Selectively forming a second conductivity type offset region in the second region, selectively forming a second conductivity type source region in a surface layer of the well region, and forming a second conductivity type in the surface region of the offset region. Forming a drain region of a first conductivity type, selectively forming a contact region of a first conductivity type in a surface layer of the well region, and forming the second semiconductor substrate sandwiched between the source region and the offset region Forming a gate electrode on the well and the well region via a gate insulating film thicker than the gate insulating film of the insulated gate bipolar transistor; and forming a source on the contact region and on the source region. A method of manufacturing a semiconductor device including the electrode, and forming a drain electrode on said drain region, a lateral MOSFET having a
When the amount of impurities in the well region is the same as the amount of impurities in the buffer region, and a positive voltage is applied to the source electrode with respect to the drain electrode, the offset region and the second semiconductor base are formed. The amount of impurities in the well region and the amount of impurities in the buffer region are made equal to each other so that a punch-through voltage at which a depletion layer reaches the source region is higher than the avalanche breakdown voltage of the junction to be formed. Semiconductor device manufacturing method.

In a semiconductor device in which a first semiconductor base and a second semiconductor base are bonded via an insulating film, and the second semiconductor base is formed on a bonded substrate polished to a predetermined thickness,
A first conductivity type well region selectively formed on the surface of the second semiconductor substrate and having a diffusion depth that does not reach the insulating film; and a surface layer of the second semiconductor substrate separated from the well region. An offset region of the second conductivity type selectively formed, a source region of the second conductivity type selectively formed on the surface layer of the well region of the first conductivity type, and a surface layer of the offset region. A drain region of the second conductivity type formed selectively; a contact region of the first conductivity type selectively formed on the surface layer of the well region; and the source region sandwiched between the source region and the contact region. An auxiliary source region of a first conductivity type having a higher concentration than the source region formed in the surface layer of the well region in connection with the second semiconductor substrate interposed between the source region and the offset region; The well region A gate electrode formed through a gate insulating film, a source electrode formed on the contact region and the auxiliary source region, and a drain electrode formed on the drain region. hand,
When the source region has a deeper diffusion depth than the diffusion depth of the drain region, the impurity amount of the well region is a predetermined value, and a positive voltage is applied to the source electrode with respect to the drain electrode, A punch-through voltage reaching a depletion layer to the source region is higher than an avalanche breakdown voltage of a junction formed by the offset region and the second semiconductor substrate, and a diffusion depth of the auxiliary source region is larger than a diffusion depth of the source region. A semiconductor device characterized by being shallower than that.

When a positive voltage is applied to the source electrode with respect to the drain electrode, and a negative voltage is applied to the gate electrode with respect to the source electrode, a current flowing through the well region immediately below the source region causes the source to flow. 9. The method according to claim 8, wherein carriers are not injected from the source region into the well region by a voltage generated at a pn junction formed between the region and the well region immediately below the source region. Semiconductor device.

10. The semiconductor device according to claim 9, wherein a voltage generated at a pn junction formed between the source region and the well region immediately below the source region is 0.6 V or less.

11. The device according to claim 8, wherein the auxiliary source region is formed in an island shape, and the auxiliary source region formed in the island shape is connected to the source region and the source electrode. 13. The semiconductor device according to item 9.

The semiconductor device according to claim 8, wherein the auxiliary source region has the same impurity concentration and the same diffusion depth as the drain region.