JP2004095761A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device configured by dividing the main face of a semiconductor substrate into mesh patterns, and arranging the same MOS transistor in respective cells configuring the mesh pattern wherein the MOS transistor whose ESD surge resistance and breakdown voltage is optimized is formed in the respective cells. <P>SOLUTION: The semiconductor device 200 is configured by arranging the same MOS transistor 101 in the respective cells of a mesh pattern, when the area of the cell is set as Sc[cm<SP>2</SP>]. The dose of the first conductive impurity of an intermediate concentration area 6 is set as Dd[/cm<SP>2</SP>], the outer peripheral length of a contact 40 of a drain area 5 and a drain electrode 14 is set as Ld[cm], the saturating speed of electrons is set as Vs[cm/s], and the elementary charge of the electrons is set as Qe[C]. At the above essential terms, the following formula; (Ld/Sc)×Vs×Dd×Qe>2×10<SP>4</SP>[A/cm<SP>2</SP>] is fulfilled. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a main surface of a semiconductor substrate is divided into a mesh pattern, and the same MOS transistor is arranged in each cell constituting the mesh pattern.
[0002]
[Prior art]
[0003]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2001-352070 One of the semiconductor power devices is, for example, a lateral MOSFET (LDMOS) disclosed in Japanese Patent Application Laid-Open No. 2001-352070.
[0004]
An LDMOS power device generally has a configuration in which tens of thousands to hundreds of thousands of small LDMOSs are connected in parallel, and the power device obtains an output by operating these LDMOSs simultaneously. When a large number of these LDMOSs are formed on a semiconductor substrate, it is common to divide the main surface of the semiconductor substrate into a mesh pattern and arrange LDMOSs of the same size in each cell forming the mesh pattern. is there. Therefore, all the LDMOSs constituting the power element have the same size, and in principle, the same current flows in all the LDMOSs.
[0005]
However, when a large current is to flow instantaneously like an ESD (ElectroStatic Discharge) surge, the same amount of current cannot flow in all LDMOS due to a difference in wiring length and the like. In addition, a large current locally flows through some LDMOSs to cause element destruction, and the wiring connected to the LDMOSs to be blown. For this reason, a power element using an LDMOS is required to have improved ESD surge immunity, and particularly in an application field for automobiles, a high ESD surge immunity of about 10 kV / mm ² is demanded. In recent years, even higher ESD surge tolerance of about 15 kV / mm ² has been demanded.
[0006]
FIG. 5 shows the relationship between the ESD surge resistance and the maximum current per unit area. With an ESD surge resistance of 10 kV / mm ² , it is necessary to allow a current of 1.3 × 10 ⁴ A / cm ² to flow. Also, with an ESD surge withstand capability of 15 kV / mm ² , it is necessary to allow a current of 1.8 × 10 ⁴ A / cm ² to flow.
[0007]
As a method of improving the ESD surge withstand capability of the LDMOS, the structure of the LDMOS 100 shown in FIG. 6 is disclosed in JP-A-2001-352070. This LDMOS 100 is formed on an SOI substrate including a p-type silicon substrate 2, an insulating layer 3, and an n-type layer 1. In the LDMOS 100, an n-type region 6 is formed so as to surround the n + -type drain region 5 and to have a higher concentration than the n-type layer 1 and to have a higher concentration as approaching the n + -type drain region 5. Further, ap + -type contact region 9 disposed adjacent to the n + -type source region 8 is formed so as to enter the lower portion of the n + -type source region 8. In FIG. 6, reference numeral 4 denotes a LOCOS oxide film, reference numeral 10 denotes a gate insulating film, reference numeral 11 denotes a gate electrode, reference numeral 12 denotes an interlayer insulating film, reference numeral 13 denotes a source electrode, and reference numeral 14 denotes a drain electrode.
[0008]
[Problems to be solved by the invention]
In the power element having the LDMOS 100 shown in FIG. 6 as one cell, an n-type region 6 surrounding the n + -type drain region 5 and ap + -type contact region 9 penetrating below the n + -type source region 8 are arranged. , The LDMOS 100 has an improved ESD surge resistance.
[0009]
On the other hand, since the drain region substantially approaches the source region due to the arrangement of the n-type region 6, the breakdown voltage of the LDMOS 100 decreases. Then, if the other conditions of each diffusion region are the same and the cell pitch is simply widened to separate the drain region and the source region in order to secure the withstand voltage of the LDMOS 100, the ESD surge withstand capability decreases again and some The drain was destroyed due to current concentration in the cell. This is considered to be because the current applied to one LDMOS 100 increased because the cell pitch was increased and the LDMOS 100 was increased.
[0010]
As described above, it has been found that the ESD surge withstand voltage and the withstand voltage are contradictory characteristics. Therefore, in applying the LDMOS 100 shown in FIG. 6, it is necessary to make the ESD surge withstand voltage and the withstand voltage compatible and optimize them.
[0011]
Therefore, an object of the present invention is to optimize the ESD surge withstand voltage and withstand voltage for each cell in a semiconductor device in which the main surface of a semiconductor substrate is divided into mesh patterns and the same MOS transistor is arranged in each cell constituting the mesh pattern. It is an object of the present invention to provide a semiconductor device in which a MOS transistor is formed.
[0012]
[Means for Solving the Problems]
The invention according to claim 1 is a semiconductor device in which a main surface of a semiconductor substrate is divided into a mesh pattern, and the same MOS transistor is arranged in each cell constituting the mesh pattern, wherein the MOS transistor has a first conductivity type. A second conductive type base region formed in a surface portion of the semiconductor layer; a first conductive type source region formed in a surface portion of the base region; A first conductive type drain region disposed so as to be separated from the base region; and a base region located between the source region and the drain region as a channel region. A gate insulating film, a gate electrode formed on the gate insulating film, a source electrode connected to the source region, and the drain A first conductivity type disposed between the drain region and the base region at a surface layer portion of the semiconductor layer and having a higher concentration than the semiconductor layer and a lower concentration than the drain region; Wherein the area of the cell is Sc [cm ² ], the dose of the first conductivity type impurity in the intermediate concentration region is Dd [/ cm ² ], and the drain region and the drain electrode When the outer peripheral length of the contact is Ld [cm], the saturation speed of electrons is Vs [cm / s], and the elementary charge of electrons is Qe [C], (Ld / Sc) × Vs × Dd × Qe> 2 × It is characterized by being 10 ⁴ [A / cm ² ].
[0013]
In a semiconductor device used for an automobile, an ESD surge immunity test of 15 kV / mm ² is required in an ESD surge immunity test, and a surge current of about 2 × 10 ⁴ A / cm ² flows at the maximum in this ESD surge immunity test.
[0014]
According to the present invention, the surge current per unit area is 2 × 10 ⁴ A in the semiconductor device in combination of the area Sc [cm ² ] of the cell capable of ensuring the withstand voltage and the dose Dd [/ cm ² ] of the intermediate concentration region. Even if / cm ² is applied, the traveling speed of electrons does not saturate near the drain of the MOS transistor. Therefore, the semiconductor device of the present invention can be a semiconductor device in which a MOS transistor having an optimized ESD surge resistance and breakdown voltage is formed in each of the cells. Further, the semiconductor device of the present invention can be a semiconductor device having a required ESD surge resistance even when used for an automobile.
[0015]
According to a second aspect of the present invention, the cell is configured by connecting a source cell in which a source region is formed and a drain cell in which a drain region is formed, and the source cell and the drain cell are squares having the same size. When one side of the square is Wc [cm], {Ld / 2 × (Wc × Wc)} × Vs × Dd × Qe> 2 × 10 ⁴ [A / cm ² ].
[0016]
According to this, as described above, the ESD surge withstand voltage and the withstand voltage of the MOS transistor formed in each cell are optimized, and the source cells and the drain cells having the same size in the square are arranged in a lattice pattern, thereby reducing waste. Space can be eliminated. Thus, the size of the semiconductor device can be reduced.
[0017]
According to a third aspect of the present invention, when the contact between the drain region and the drain electrode is a square and one side of the square is Wd [cm], {2 × Wd / (Wc × Wc)} × Vs × Dd × Qe> 2 × 10 ⁴ [A / cm ² ].
[0018]
According to this, the ESD surge withstand voltage and the withstand voltage of the MOS transistor formed in each cell are optimized as described above, and the current is supplied perpendicularly to each side of the square from the square contact between the drain region and the drain electrode. Can flow evenly. Thereby, the four sides of the square contact of the drain can be used evenly.
[0019]
The invention according to claim 4 is characterized in that one side Wc [cm] of the square of the source cell and the drain cell satisfies 9 × 10 ⁻⁴ ≦ Wc ≦ 14 × 10 ⁻⁴ .
[0020]
Within this range, it is possible to select a MOS transistor having a square source cell and a drain cell and having an ESD surge withstand voltage and a withstand voltage required for an automobile. A semiconductor device having a withstand voltage can be obtained.
[0021]
The invention according to claim 5 is characterized in that the dose amount Dd [/ cm ² ] of the first conductivity type impurity in the intermediate concentration region is 2 × 10 ¹³ ≦ Dd ≦ 1 × 10 ¹⁴ . Thereby, the concentration of the first conductivity type impurity in the intermediate concentration region can be appropriately set between the semiconductor layer and the drain region.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
FIG. 1A is a schematic plan view showing a structure of a semiconductor device 200 of the present invention, and FIG. 1B is a schematic sectional view taken along line AA ′ in FIG. 1A.
[0024]
As shown in FIG. 1A, in the semiconductor device 200, the main surface of the semiconductor substrate 1 is divided into meshes and divided into square cells each having a side length of Wc [cm]. The divided square cells are composed of source cells 20 and 21 in which source regions of MOS transistors are formed, and drain cells 30 and 31 in which drain regions are formed. These are arranged in a lattice pattern as shown in the figure. I have. A MOS transistor 101 is constituted by, for example, the source cell 20 and the drain cell 30 as a set of adjacent cells of the source cells 20 and 21 and the drain cells 30 and 31 arranged in a lattice pattern. By arranging the source cells 20 and 21 and the drain cells 30 and 31 having the same size in a square pattern in a lattice pattern, it is possible to eliminate useless space. In addition, the size of the semiconductor device 200 can be reduced.
[0025]
The MOS transistor 101 formed in the semiconductor device 200 of the present embodiment is an LDMOS as shown in FIG. The structure of the LDMOS 101 in FIG. 1B is the same as that of the LDMOS 100 shown in FIG. 6, and the same parts as those in the LDMOS 100 in FIG. In FIG. 1B, for simplification, the illustration of the gate insulating film 10 in FIG. 6 is omitted. Reference numeral 9a in FIGS. 1A and 1B denotes a high-concentration p + type region. The contact 50 of the source electrode 13 is square and larger than the area of the high-concentration p + -type region 9a, and connects the high-concentration p + -type region 9a and the n + -type source region 8 in common.
[0026]
In the LDMOS 101 of the present embodiment, the contact 40 between the n + -type drain region 5 and the drain electrode 14 is a square having one side of Wd [cm]. As a result, the current can be caused to flow uniformly from the contact 40 vertically to each side of the square. Therefore, the four sides of the square contact 40 can be used evenly.
[0027]
In the semiconductor device 200 of the present embodiment, for a required surge allowable current of 2 × 10 ⁴ A / cm ² , one cell area of the LDMOS 101 is Sc [cm ² ], and the dose amount Dd of the intermediate concentration region 6 is [/ Cm ² ], the outer peripheral length Ld [cm] of the contact 40 between the n + type drain region 5 and the drain electrode 14 is defined as follows.
[0028]
(Ld / Sc) × Vs × Dd × Qe> 2 × 10 ⁴ [A / cm ² ]
Here, Vs [cm / s] is the saturation speed of the electron, and Qe [C] is the elementary charge of the electron.
[0029]
In the case of the LDMOS 101 of the present embodiment, two square cells each having a side of Wc [cm] are connected to form one LDMOS 101. Therefore, one cell area of the LDMOS 101 is Sc = 2 × ( Wc × Wc) [cm ² ]. Therefore, Equation 6 is as follows.
[0030]
{Ld / 2 × (Wc × Wc)} × Vs × Dd × Qe> 2 × 10 ⁴ [A / cm ² ]
Further, in the case of the LDMOS 101 of the present embodiment, the contact 40 between the n + -type drain region 5 and the drain electrode 14 is a square having one side of Wd [cm], so the outer peripheral length Ld of the contact 40 is Ld = 4 × Wd [ cm]. Therefore, Equation 7 is as follows.
[0031]
## EQU8 ## {2 × Wd / (Wc × Wc)} × Vs × Dd × Qe> 2 × 10 ⁴ [A / cm ² ]
Equations 6 to 8 above are derived in consideration of the fact that the drain is not destroyed by the surge current Is per unit area applied to the semiconductor device 200.
[0032]
It is presumed that the current concentration at the drain, which occurs when the cell size is increased to secure the withstand voltage described in the conventional problem, is a result of the velocity saturation of the impurity electrons in the intermediate concentration region 6. When the surge current Is increases, the velocity saturation of the impurity electrons in the intermediate concentration region 6 occurs in some cells, and the impurity electrons cannot carry any more current. If an attempt is made to pass a larger current, more electrons are generated than electrons that can be supplied by the impurity, and the charge balance is disrupted, so that a negative space charge is generated. When a negative space charge is generated, the voltage between the drain and the source decreases, and this cell exhibits a negative resistance. When the LDMOS enters the region of negative resistance, positive feedback is applied and current concentration occurs, leading to destruction.
[0033]
Therefore, in the present invention, the electrons given from the impurities in the intermediate concentration region 6 can flow under the velocity saturation on the left side of Equations 6 to 8 so that the electron velocity saturation does not occur at the drain contact end where the current is most concentrated. An amount corresponding to the maximum electron current per unit area was defined. Therefore, the conditions of Expressions 6 to 8 mean that the maximum electron current defined as described above does not exceed the surge current Is per unit area.
[0034]
As a result, in the intermediate current region 6, the speed saturation of the electron current does not occur in the surge current Is in the range where the mathematical expressions 6 to 8 hold. For this reason, it was considered that the impurity electrons in the intermediate concentration region 6 could not carry the surge current Is and did not break the charge balance, and the current was not concentrated in some cells and the drain was not destroyed.
[0035]
Next, the present embodiment will be described using specific numerical values. Consider a case where the semiconductor device 200 having a surge allowable current of 2 × 10 ⁴ A / cm ² is realized. The electron elementary charge Qe is 1.60 × 10 ⁻¹⁹ C, and the electron saturation velocity Vs can be generally set to 1.07 × 107 cm / s. Further, the dose amount Dd of the intermediate concentration region 6 is set to 5 × 10 ¹³ / cm ² .
[0036]
In FIG. 1A, when one side Wc of the square of the source cell 20 and the drain cell 30 is 11 μm and one side Wd of the square of the drain contact 31 is 2.4 μm, the left side of Expression 8 is 3.39 × 10 ⁴ A. / Cm ² , which satisfies Equation 8 in these combinations.
[0037]
In FIG. 1A, when one side Wc of the square of the source cell 20 and the drain cell 30 is 13 μm and one side Wd of the square of the drain contact 31 is 3.4 μm, the left side of Expression 8 is 3.44 × 10 ⁴ A. / Cm ² . When Wd is 2.4 μm, the left side of Expression 8 is 2.43 × 10 ⁴ A / cm ² . Therefore, Equation 8 is satisfied also in these combinations. On the other hand, when Wc is 13 μm and Wd is reduced to 1.4 μm, the left side of Expression 8 is 1.42 × 10 ⁴ A / cm ² . Therefore, Equation 8 is not satisfied in this combination.
[0038]
FIG. 2 shows the measurement results of the ESD surge resistance when Wc is 13 μm and Wd is 1.4 μm, 2.4 μm, and 3.4 μm. As shown in the figure, when Wd that satisfies Equation 8 is 2.4 μm and 3.4 μm, the ESD surge resistance is 15 kV / mm ² , which satisfies the standard required for a semiconductor device mounted on a vehicle.
[0039]
FIGS. 3A and 3B are simulation results of the current-voltage characteristics Id-Vd in the drain region when Wc is 13 μm and Wd is 1.4 μm and 3.4 μm.
[0040]
In order to prevent the LDMOS from being destroyed, it is desirable that the current Id that becomes the negative resistance region be as large as possible. 3 (a) and 3 (b), although the breakdown voltage is about 60 V and both are almost equal, when Wd is 1.4 μm, the negative resistance occurs when Id is 0.18 or more. , Wd is 3.4 μm, negative resistance occurs when Id is 0.58 or more. Therefore, when Wd is 3.4 μm, the current capability is three times or more higher than when Wd is 1.4 μm.
[0041]
FIG. 4 shows the results of measuring the relationship between the ESD surge withstand voltage and the withstand voltage of the LDMOS that satisfies Equation 8 when Wc is 9, 11, 13, and 14 μm and that has different Wd and Dd and satisfies Equation 8. All of them have an ESD surge resistance of 15 kV / mm ² or more, and those having 9 × 10 ⁻⁴ ≦ Wc ≦ 14 × 10 ⁻⁴ [cm] can satisfy the standards required for semiconductor devices mounted on automobiles.
[0042]
In the above embodiment, the case where the dose amount Dd of the first conductivity type impurity in the intermediate concentration region is 5 × 10 ¹³ / cm ² has been described, but it goes without saying that Dd is not limited to this value. Dd of the intermediate concentration region 6 is in a range of 2 × 10 ¹³ / cm ² or more and 1 × 10 ¹⁴ / cm ² or less, which allows the concentration of the first conductivity type impurity to be set appropriately between the semiconductor layer 1 and the drain region 5. Is desirable.
[0043]
In this embodiment, the case where the source cell 20 and the drain cell 30 are squares each having a side length of Wc and the drain contact 40 is a square whose side length is Wd is specifically described. However, this is exemplary. According to the present invention, the area Sc [cm ² ] of the cell in which the MOS transistor is formed, the dose Dd [/ cm ² ] of the first conductivity type impurity in the intermediate concentration region, and the outer peripheral length Ld [cm] of the drain contact Is defined as in Expression 6, the same effect as described above can be obtained.
[Brief description of the drawings]
FIG. 1A is a plan view showing a structure of a semiconductor device of the present invention, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG.
FIG. 2 is a measurement result of an ESD surge resistance when Wc is 13 μm.
3A and 3B are simulation results of current-voltage characteristics in a drain region when Wc is 13 μm. FIG. 3A shows a case where Wd is 1.4 μm, and FIG. 3B shows a case where Wd is 3.4 μm.
FIG. 4 shows the results of measuring the relationship between the ESD surge withstand voltage and the withstand voltage for each of Wc and LDMOS having different Wd and Dd satisfying Expression 8.
FIG. 5 is a diagram showing a relationship between an ESD surge withstand capacity and a maximum current per unit area.
FIG. 6 is a sectional view showing the structure of a conventional LDMOS 100.
[Explanation of symbols]
100,101 MOS transistor (LDMOS)
200 semiconductor device 20, 21 drain cell 30, 31 source cell 1 semiconductor substrate (n-type layer)
Reference Signs List 4 LOCOS oxide film 5 n + type drain region 6 n type region 7 p type base region 8 n + type source region 9 p + type contact region 9a high concentration p + type region 10 gate insulating film 11 gate electrode 12 interlayer insulating film 13 source electrode 14 drain Electrodes 40, 50 contacts

Claims (5)

In a semiconductor device in which a main surface of a semiconductor substrate is divided into a mesh pattern and the same MOS transistor is arranged in each cell constituting the mesh pattern,
The MOS transistor includes a substrate having a semiconductor layer of a first conductivity type, a base region of a second conductivity type formed on a surface portion of the semiconductor layer, and a first conductive layer formed on a surface portion of the base region. Source region, a first conductivity type drain region disposed at a distance from the base region in a surface layer portion of the semiconductor layer, and the base region located between the source region and the drain region. A channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, a source electrode connected to the source region, and a drain connected to the drain region. An electrode disposed between the drain region and the base region at a surface portion of the semiconductor layer, and having a higher concentration than the semiconductor layer and a lower concentration than the drain region; It and a conductivity type of the intermediate concentration region,
The area of the cell is Sc [cm ² ], the dose of the first conductivity type impurity in the intermediate concentration region is Dd [/ cm ² ], and the outer peripheral length of the contact between the drain region and the drain electrode is Ld [cm]. When the saturation speed of electrons is Vs [cm / s] and the elementary charge of electrons is Qe [C],

A semiconductor device, characterized in that: The cell is configured by connecting a source cell in which the source region is formed and a drain cell in which the drain region is formed,
The source cell and the drain cell are formed of the same size square,
When one side of the square is Wc [cm],

The semiconductor device according to claim 1, wherein The contact between the drain region and the drain electrode is square,
When one side of the square is Wd [cm],

The semiconductor device according to claim 2, wherein One side Wc [cm] of the square of the source cell and the drain cell is

The semiconductor device according to claim 2, wherein The dose Dd [/ cm ² ] of the first conductivity type impurity in the intermediate concentration region is:

The semiconductor device according to claim 1, wherein:

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