JP2004088886A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of turning off a switching device at a high speed without being affected by the parasitic inductance of gate wiring. <P>SOLUTION: An insulated gate type switching device for controlling continuity/discontinuity between first and second current terminals by a gate terminal is installed on a package. The package includes an external control terminal connected with the gate terminal, and first and second external current terminals connected with the first and second current terminals, respectively. The package is also mounted with a turn-off buffer which discharges a gate load to either of the first and second external current terminals when the switching device is turned off. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to an insulated gate power switching element.
[0002]
[Prior art]
As an insulated gate type (MOS type) power switching element, an insulated gate type bipolar transistor (Insulated Gate Bipolar Transistor, hereinafter referred to as IGBT) and a MOS transistor are known. In these switching elements, it is necessary to increase the chip size in order to increase power, but the input capacitance (gate capacitance) increases accordingly. In order to drive a switching element having a large input capacitance at high speed, it is necessary to reduce a gate resistance as much as possible so that a large gate current flows during switching. On the other hand, when a steep gate current flows, the gate voltage easily oscillates due to the parasitic inductance of the gate wiring and the gate capacitance, and this oscillation causes a switching malfunction.
[0003]
FIG. 9 shows a configuration example of a gate drive circuit section of a conventional MOS power switching element. The switching element 1 is an IGBT in which a reverse conducting diode 2 is integrally formed. The reverse conducting diode 2 conducts when a reverse bias voltage exceeding a certain value is applied between the collector and the emitter, and serves to prevent the switching element 1 from being destroyed. The switching element 1 is mounted on a package 3 shown by a broken line, and has three external terminals of a gate terminal G, a collector terminal C, and an emitter terminal E.
[0004]
The gate drive circuit of the switching element 1 has a photocoupler 10 and a driver stage 20 driven by the photocoupler. The driver stage 20 has an npn transistor Q1 for supplying a gate current when turned on, and a pnp transistor Q2 for discharging a gate charge when turned off. A resistor R12 for limiting a turn-on current is inserted between the emitters of the transistors Q1 and Q2. A connection node between the resistor R12 and the emitter of the transistor Q2 is connected to the gate terminal G of the switching element 1 via the input resistor R13.
[0005]
The bases of the transistors Q1 and Q2 are commonly connected, and the output of the photocoupler 10 drives this common base terminal. The photocoupler 10 is used to couple the gate control circuit (not shown) and the circuit section including the driver stage 20 and the switching element 1 in an electrically separated state.
[0006]
When the switching element 1 is turned on, the transistor Q2 of the driver stage 20 is turned off and the transistor Q1 is turned on. As a result, a gate current is supplied from the power supply VDD via the transistor Q1 and the resistors R12 and R13. When the gate voltage exceeds the threshold, the switching element 1 turns on. When the switching element 1 is turned off, the transistor Q2 of the driver stage 20 is turned on and the transistor Q1 is turned off. As a result, the gate charge of the switching element 1 is discharged via the resistor R13 and the transistor Q2. When the gate voltage drops below the threshold, the switching element 1 is turned off.
[0007]
The switching element drive circuit in FIG. 9 assumes a 0 V switching circuit (soft switching circuit) that turns on the switching element 1 at Vce = 0 V. In this case, since the resistor can be driven at a low speed at the time of turn-on, for example, a resistor R12 having a resistance of about 150Ω is used to suppress a sharp change in gate current at the time of turn-on. Thereby, the influence of the parasitic inductance of the gate wiring at the time of turn-on is suppressed, and the oscillation of the gate voltage is prevented.
[0008]
[Problems to be solved by the invention]
However, the circuit configuration of FIG. 9 does not solve the problem of the gate voltage oscillation when the switching element 1 is to be turned off at high speed. In order to turn off the switching element 1 at a high speed, it is necessary to discharge the gate voltage at a high speed, and the resistor R13 must be as small as about 10Ω. Then, a sharp gate discharge current flows at the time of turn-off. Therefore, when the parasitic inductance of the gate wiring is large, a switching malfunction due to the oscillation of the gate voltage occurs. In particular, the problem becomes serious when the input capacitance increases due to the increase in power of the switching element.
[0009]
An object of the present invention is to provide a semiconductor device that enables a high-speed turn-off of a switching element.
[0010]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes an insulated gate switching element in which conduction and non-conduction between first and second current terminals are controlled by a gate terminal, and a connection to the gate terminal on which the switching element is mounted. A package having an external control terminal to be connected, first and second external current terminals to which the first and second current terminals are respectively connected, and a gate mounted on the package when the switching element is turned off. A turn-off buffer for discharging a charge to one of the first and second external current terminals.
[0011]
According to the present invention, the turn-off buffer for discharging the gate charge without passing through the external control terminal when the switching element is turned off is mounted on the package together with the switching element, so that the switching element can be operated at high speed without being affected by the parasitic inductance of the gate wiring. Turn off is possible.
[0012]
In the present invention, for example, the turn-off buffer is interposed between the gate terminal of the switching element and the first current terminal, and the control terminal is connected to the external control terminal and is turned on when the switching element is turned off to transfer the electric charge of the gate terminal. A discharge transistor that escapes to the first current terminal; and a discharge transistor that is inserted between the external control terminal and the gate terminal to keep the discharge transistor off when the switching element is turned on, and to forward bias the discharge transistor when the switching element is turned off. And a bias element for providing As a result, the turn-off buffer can be mounted while the package remains at three terminals.
[0013]
In the present invention, in order to suppress the discharge speed at the time of turn-off, a resistor for limiting the discharge current may be inserted in the current path of the discharge transistor.
[0014]
In the present invention, the switching element is one of an n-channel MOS transistor and an n-channel IGBT. As the discharging transistor, a pnp transistor having an emitter connected to the gate terminal and a collector connected to the first current terminal can be used. Alternatively, a p-channel MOS transistor having a source connected to the gate terminal and a drain connected to the first current terminal can be used as the discharging transistor.
[0015]
As the bias element of the turn-off buffer, a diode having the external control terminal side as an anode can be used. Specifically, the diode can be constituted by a bipolar transistor having a base and a collector commonly connected, or a MOS transistor having a gate and a drain commonly connected.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a semiconductor device according to an embodiment of the present invention, together with a gate drive circuit. The power switching element 1 may be either an n-channel IBGT or an n-channel MOS transistor, but an example of an IGBT is shown here. The same applies to the following embodiments.
[0017]
The switching element 1 has an emitter terminal E as a first current terminal, a collector terminal C as a second current terminal, and a MOS gate terminal G for controlling conduction and non-conduction between these terminals. When the switching element 1 is a MOS transistor, the source terminal and the drain terminal correspond to the emitter terminal E and the collector terminal C, respectively.
[0018]
The switching element 1 has a reverse conducting diode 2 formed integrally therewith. The switching element 1 is mounted on a package 3 indicated by a broken line. The package 3 has the same three terminals as the switching element 1. The first and first external current terminals 4 and 5 to which the emitter terminal E and the collector terminal C are respectively connected, and the external control to which the gate terminal G is to be connected. It has a terminal 6.
[0019]
In this embodiment, a turn-off buffer 7 for discharging a gate charge at high speed when the switching element 1 is turned off is mounted on the package 3 together with the switching element 1. It is important that the turn-off buffer 7 is configured without providing any special terminal in addition to the three external terminals 4, 5, 6 described above on the package 3.
[0020]
Specifically, in the example of FIG. 1, the turn-off buffer 7 includes a pnp transistor T for discharging a charge at the gate terminal G and a diode Di. The discharge transistor T has an emitter connected to the gate terminal G, a collector connected to the emitter terminal E, that is, the first external current terminal 4, and a base connected to the external control terminal 6. The diode Di is a bias element for forward-biasing the discharge transistor T at the time of turn-off. The diode Di has an anode connected to the external control terminal 6, a cathode connected to the gate terminal G, and a connection between the external terminal 6 and the gate terminal G. Inserted between them.
[0021]
The photocoupler 10 is used as a gate drive circuit of the switching element 1. The photocoupler 10 includes an LED 11 driven by a control signal and a photodiode 12 that receives output light from the LED 11. The output current of the photodiode 12 is converted into a voltage by a current-voltage conversion circuit 13, and the output voltage is supplied to a drive circuit 14. The drive circuit 14 drives the npn transistor 15 and the pnp transistor 16 of the output stage, whose emitters are commonly connected, so that they are turned on at the time of turn-on and at the time of turn-off, respectively. The collector of the transistor 15 is connected to the power supply VDD, and the collector of the transistor 16 is connected to the first external current terminal 4.
[0022]
The commonly connected emitters of the transistors 15 and 16 are the output terminals of the photocoupler 10 and are connected to the external control terminal 6 via the resistor R1. The resistor R1 limits the rising speed of the gate current supplied by the transistor 15 at the time of turn-on, and corresponds to the resistor R12 in FIG. Therefore, for example, a resistor of about 150Ω is used as the resistor R1. In this embodiment, the driver stage 20 as in the prior art shown in FIG. 9 is not necessary. This is because the gate current when the switching element 1 is turned on is suppressed by the resistor R1, and when the switching element 1 is turned off, the gate is discharged by the turn-off buffer 7.
[0023]
The switching operation of the switching element 1 in this embodiment is as follows. At the time of turn-on, the transistor 15 of the output stage transistors 15 and 16 of the photocoupler 10 is turned on. As a result, a gate current is supplied from the power supply VDD to the gate terminal G through the path of the transistor 15, the resistor R1, the external control terminal 6, and the diode Di. When the gate voltage exceeds the threshold, the switching element 1 turns on.
[0024]
While the switching element 1 is on, the base of the discharging transistor T is kept higher than the emitter by the diode Di and kept off by the diode Di. In the case of this embodiment, the switching element 1 assumes 0 V switching. Therefore, the rise rate of the gate current at the time of turn-on is limited by the resistor R1, and the gate voltage oscillation due to the influence of the inductance attached to the external control terminal 6 is suppressed.
[0025]
When the switching element 1 is turned off, the transistor 16 of the output stage transistors 15 and 16 of the photocoupler 10 is turned on. As a result, the external control terminal 6 goes low, and the diode Di enters a reverse bias state. The discharge transistor T is forward-biased by the voltage between the anode and the cathode of the diode Di and is turned on, and the positive charge of the gate terminal G is discharged to the first current terminal 4 via the discharge transistor T. That is, the gate current at the time of turn-off flows to the first current terminal 4 through the discharge transistor T without passing through the resistor R1, so that high-speed turn-off by high-speed discharge can be performed.
[0026]
In addition, the transistor T is housed in the same package 3 as the switching element 1, and the connection between the emitter of the transistor T and the gate terminal G of the switching element 1 can be made with a very short wiring. The effect of the parasitic inductance associated with is greatly reduced. As a result, a situation in which the gate voltage oscillates even when a high-speed gate discharge is performed is prevented.
[0027]
Further, according to this embodiment, even a switching element having a large input capacitance can be turned off at a high speed. Therefore, it is possible to suppress the turn-off loss and increase the power of the switching element. Further, since it is not necessary to consider the influence of the parasitic inductance of the gate wiring, the degree of freedom of the gate wiring is improved. In this embodiment, the turn-off buffer is packaged together with the switching element. However, the turn-off buffer employs a configuration that does not require a special external terminal, and the package remains at three terminals as in the conventional case. That is, the existing three-terminal package can be used as it is, and the compatibility with the existing switching element is good.
[0028]
2 to 8 show a semiconductor device according to another embodiment only with respect to an internal configuration of a package. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. However, according to these embodiments, it is possible to obtain the same effects as those of the previous embodiments.
[0029]
FIG. 2 shows an example in which a resistor R2 is inserted in the current path (specifically, the emitter) of the discharge transistor T of the turn-off buffer 7. To slightly suppress the turn-off speed, the resistor R2 may be inserted in the discharge path as described above. When the switching element 1 is switched at a high speed, radiation noise due to electromagnetic induction may cause a problem for surrounding circuits and the like. Therefore, when it is necessary to adjust the turn-off speed, the configuration as shown in FIG. 2 is effective.
[0030]
FIG. 3 shows an example in which a resistor R3 is used instead of the diode Di as a bias element for turning on the transistor T when the switching element 1 is turned off. In this case, if the value of the resistor R3 is appropriately selected, the transistor T can be turned on by the voltage across the resistor R3 at the time of turning off. At this time, the discharging path of the gate charge of the switching element 1 includes a path discharging through the transistor T, a path discharging through the resistor R3, the external control terminal R6, and further through the transistor 16 shown in FIG. Will be. However, if a larger discharge current is caused to flow through the transistor T, the influence of the inductance of the gate wiring can be suppressed.
[0031]
FIG. 4 shows an example in which an npn transistor having a base and a collector connected in common is used as an equivalent element of the diode Di.
FIG. 5 shows an example in which a p-channel MOS transistor Q is used instead of the pnp transistor T as the discharging transistor. The MOS transistor Q has a source connected to the gate G of the switching element 1, a gate connected to the external control terminal 6, and a drain connected to the first current terminal 4. Thus, as in the case of the pnp transistor T, the switching element 1 is turned on when it is turned off, and the gate charge can be discharged.
[0032]
FIG. 6 shows an example in which a resistor R2 is inserted into the source of the MOS transistor Q as in FIG. 2 in order to adjust the turn-off speed in the configuration of FIG.
FIG. 7 shows an example in which a resistor R3 is used instead of the diode Di in the configuration of FIG.
FIG. 8 shows an example in which an n-channel MOS transistor having a gate and a drain connected together is used as an equivalent element of the diode Di in the configuration of FIG.
[0033]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor device capable of turning off a switching element at high speed.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 3 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 4 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 5 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 6 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 7 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 8 is a diagram showing a configuration of a semiconductor device according to another embodiment.
FIG. 9 is a diagram showing a configuration of a conventional semiconductor device.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 switching element (IGBT, MOS transistor), 2 reverse conducting diode, 3 package, 4 first external current terminal, 5 second external current terminal, 6 external control terminal, 7 turn-off buffer, T: discharge transistor (pnp transistor), Di: diode (bias element), R2, R3: resistor, Q: discharge transistor (p-channel MOS transistor).

Claims (7)

An insulated gate switching element in which conduction and non-conduction between the first and second current terminals are controlled by the gate terminal;
A package having the switching element, an external control terminal to be connected to the gate terminal, and first and second external current terminals to which the first and second current terminals are respectively connected;
A turn-off buffer mounted on the package and discharging a gate charge to one of the first and second external current terminals when the switching element is turned off;
A semiconductor device comprising: The turn-off buffer,
A control terminal is interposed between the gate terminal and the first current terminal of the switching element, and a control terminal is connected to the external control terminal and is turned on when the switching element is turned off to charge the gate terminal with the first current. A discharge transistor to escape to the terminal,
A bias element inserted between the external control terminal and the gate terminal to keep the discharging transistor off when the switching element is on, and to apply a forward bias to the discharging transistor when the switching element is turned off; ,
2. The semiconductor device according to claim 1, comprising: 3. The semiconductor device according to claim 2, wherein a resistor for limiting a discharge current is inserted in a current path of the discharge transistor. The switching element is one of an n-channel MOS transistor and an n-channel IGBT,
The discharge transistor is a pnp transistor having an emitter connected to the gate terminal and a collector connected to the first current terminal, respectively.
3. The semiconductor device according to claim 2, wherein the bias element is a diode having the external control terminal side as an anode. The switching element is one of an n-channel MOS transistor and an n-channel IGBT,
The discharge transistor is a p-channel MOS transistor having a source connected to the gate terminal and a drain connected to the first current terminal, respectively.
3. The semiconductor device according to claim 2, wherein the bias element is a diode having the external control terminal side as an anode. 6. The semiconductor device according to claim 4, wherein said diode is constituted by a bipolar transistor having a base and a collector connected in common. 6. The semiconductor device according to claim 4, wherein said diode is constituted by a MOS transistor having a gate and a drain connected together.

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