JP2004087589A - Printed board having reduced emi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To analyze the generation mechanism of radiation noises and to reduce the radiation noises 30 even when a via part (2) is made on the end part of a printed board as shown in Fig.(a). <P>SOLUTION: The EMI reduced printed board is constituted by arranging a 3rd insulating layer 6 whose dielectric constant (or electric conductivity) is larger than that of 1st and 2nd insulating layers 2, 4 in a prescribed range surrounding a via part 7 connecting a 2nd power supply electrode 5 to a 1st power suppLy electrode 1 on a multilayer printed board 10 on which the 1st power supply electrode 1, the 1st insulating layer 2, a ground electrode 3, the 2nd insulating layer 4, and the 2nd power supply electrode 5 are successively laminated. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an EMI reduction printed board used for reducing unnecessary radiation from electronic circuit components mounted on a printed board.
[0002]
[Prior art]
High-density mounting of electronic circuit components on printed circuit boards is a requirement of the times. In order to achieve this requirement, electronic circuit components have been integrated into integrated circuits (ICs), and printed circuit boards have been multilayered. Under such circumstances, reduction of unnecessary radiation radiated from the printed circuit board has become an important technical problem. In particular, in a multilayer substrate, EMI (electromagnetic interference) of noise radiating from an edge of the substrate due to cavity intrusion into the substrate through a via wiring, cavity resonance between a power supply electrode and a ground electrode of the substrate, and a problem has occurred. . Here, the via wiring is a wiring for connecting a power supply line between stacked substrates in a multilayer substrate.
[0003]
With reference to the drawings, a description will be given of the technical contents that have been known in the past regarding noise that enters the substrate through the via wiring.
FIG. 5 is a configuration diagram of a conventional printed circuit board.
(A) is a plan view, and (b) is an enlarged view of a cross section (BB) of a via portion.
As shown in (a), when the via portion (1) is arranged at the center of the printed circuit board, the radiation noise 30 is relatively small, and is arranged at the end of the printed circuit board like other via portions (2). It has been empirically found that the radiation noise 30 increases when the power is turned on.
[0004]
On the other hand, in order to reduce the radiation noise 30, a decoupling capacitor is inserted between the power supply electrode 29 and the ground electrode 28 to bypass the high frequency current, or a magnetic loss element such as ferrite is inserted to insert the high frequency current. And other measures were taken.
[0005]
[Problems to be solved by the invention]
As described in the above related art, inserting a magnetic loss element such as a decoupling capacitor or ferrite into a printed circuit board hinders high-density mounting. Further, the inductance of the wiring of the magnetic loss element such as a decoupling capacitor or ferrite cannot be ignored, and the effect is reduced. Further, when the via portion is disposed at the end of the printed circuit board, if the radiated noise 30 becomes large, it is necessary to restrict the mounting position of the components and the like, which is an obstacle to high-density mounting.
[0006]
Therefore, the mechanism of the generation of the radiation noise is clarified, and the radiation noise 30 is reduced even when the via portion is disposed at the end of the printed circuit board as in the via portion (2) shown in (a). It is an object of the present invention.
[0007]
[Means for Solving the Problems]
The present invention employs the following configuration to solve the above points.
<Configuration 1>
A first power electrode, a first insulating layer, a ground electrode, a second insulating layer, and a second power electrode are stacked, and the second power electrode and the first power electrode are connected to each other. In a multilayer printed circuit board having a via portion to be connected, a high dielectric portion having a higher dielectric constant than the first insulating layer and the second insulating layer is provided in a predetermined range surrounding the via portion. Reduced printed circuit boards.
[0008]
<Configuration 2>
A first power electrode, a first insulating layer, a ground electrode, a second insulating layer, and a second power electrode are stacked, and the second power electrode and the first power electrode are connected to each other. In a multilayer printed circuit board having a via portion to be connected, a high-conductivity portion having a higher conductivity than the first insulating layer and the second insulating layer is provided in a predetermined range surrounding the via portion. Reduced printed circuit boards.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described using specific examples.
<Configuration of specific example>
An insulating layer having a dielectric constant higher than the dielectric constant of the other part of the insulating layer is arranged between the power supply electrode and the ground electrode near the via portion of the printed circuit board. Alternatively, an insulating layer having a higher conductivity than the other portions of the insulating layer is disposed between the power electrode and the ground electrode near the via portion of the printed circuit board. By doing so, the electric field intensity near the via portion is reduced, and the amount of radiation noise generated between the power supply electrode and the ground electrode is reduced. In order to achieve the above object, an EMI reduction printed circuit board according to the present invention is configured as follows.
[0010]
FIG. 1 is a configuration diagram of a printed circuit board according to the present invention.
(A) is a plan view of a printed circuit board according to the present invention, and (b) is an enlarged cross-sectional view (AA) of a via portion.
As shown in FIG. 1, a printed circuit board 10 according to the present invention includes a power supply electrode 1, a first insulating layer 2, a ground electrode 3, a second insulating layer 4, a power supply line 5, and a third insulating layer 6. , Via portion 7.
[0011]
The power electrode 1 is an electrode for supplying DC power to electronic circuit components and the like mounted on the printed circuit board 10, and is a copper foil having a thickness of about 0.02 mm to 0.2 mm adhered to the first insulating layer 2. Consists of The power electrode 1 is usually adhered so as to cover most of the area of the first insulating layer 2 in order to reduce the plane resistance. The power supply electrode 1 corresponds to a first power supply electrode in the claims.
[0012]
The first insulating layer 2 is formed of a 0.3 mm to 0.5 mm thick insulator that supports electronic circuit components and the like mounted on the printed circuit board 10. The first insulating layer 2 is usually made of a highly insulating material such as a glass-containing epoxy polymer material. The power electrode 1 and the ground electrode 3 are bonded to both surfaces of the first insulating layer 2.
[0013]
The ground electrode 3 is an electrode that supplies a ground potential to electronic circuit components and the like mounted on the printed circuit board 10, and is laminated and bonded between the first insulating layer 2 and the second insulating layer 4. It is made of copper foil having a thickness of about 0.2 mm to 0.3 mm. The ground electrode 3 is usually bonded so as to cover most of the area of the first insulating layer 2 or the second insulating layer 4 in order to reduce the plane resistance.
[0014]
The second insulating layer 4 is formed of a 0.3 mm to 1.0 mm thick insulator that supports electronic circuit components and the like mounted on the printed circuit board 10 in the same manner as the first insulating layer 2. The second insulating layer 4 is usually made of a highly insulating material such as a glass-containing epoxy polymer material. The power supply line 5 is a wiring for supplying DC power to electronic circuit components and the like mounted on the printed circuit board 10. A via portion 7 is provided to connect the power supply line 5 to the power supply electrode 1. This power supply line 5 corresponds to the second power supply electrode in the claims.
[0015]
The third insulating layer 6 is disposed in a predetermined range surrounding the via portion 7, and has a dielectric constant ε3 larger than the dielectric constant ε1 of the first insulating layer 2 and the dielectric constant ε2 of the second insulating layer 4. (Corresponding to the high dielectric portion in claim 1). Alternatively, the insulating layer has a conductivity ρ1 larger than the conductivity ρ1 of the first insulating layer 2 and the conductivity ρ2 of the second insulating layer 4 arranged in a predetermined range surrounding the via portion 7. (Corresponding to the high conductive portion in claim 2).
The via portion 7 is a wiring for connecting a power supply line between stacked substrates in a printed board (multilayer board).
Here, the mechanism of radiation noise generation by the via portion 7 will be elucidated, and the process leading to the idea of the via portion of the present invention surrounded by the third insulating layer 6 will be described in detail with reference to other drawings.
[0016]
FIG. 2 is a high-frequency equivalent circuit diagram of a printed circuit board according to the present invention.
(A) is an enlarged cross-sectional view of a via portion, and (b) is an equivalent circuit diagram showing a propagation path of a noise signal on a printed circuit board according to the present invention.
[0017]
In FIG. 2, a noise source Vn is an equivalent power supply in which a noise (in particular, digital noise) generated by an IC or the like mounted on a printed circuit board is represented as a high-frequency power supply. The noise signal Sn is output from the noise source Vn, passes through the propagation path 11 of the power supply line, the propagation path 12 of the via portion, and the propagation path 13 of the power supply / ground, from the end of the printed circuit board 10 (FIG. 1) to the air. Is radiated as radiation noise 30.
[0018]
The propagation path 11 of the power supply line is a distributed constant line that can be approximated to a strip line including the power supply line 5, the second insulating layer 4, and the ground electrode 3. The noise source Vn is connected to the tip, and the end is connected to the propagation path 12 of the via portion. The characteristic impedance Z1 of the propagation path 11 of the power supply line viewed from the propagation path 12 side of the via portion is approximately represented by a route of (L1 / C1). Usually, Z1 indicates a value of several tens Ω. Here, L1 is the inductance per unit length of the power supply line 5, and here, the electrode width of the power supply line 5 is as thin as about 1 mm and cannot be ignored. C1 is the capacitance per unit length of the approximated strip line.
[0019]
The power supply / ground propagation path 13 is a distributed constant line obtained by approximating a cavity resonator including the power supply electrode 1, the first insulating layer 2, and the ground electrode 3 by a transmission line. Here, the power electrode 1 is usually bonded so as to cover most of the area of the first insulating layer 2 in order to reduce the plane resistance as described above. Therefore, the inductance per unit length for approximating a distributed constant line is extremely small as compared with the propagation path 11 of the power supply line, and the capacitance between the power supply electrode 1 and the ground electrode 3 is extremely large. That is, the characteristic impedance Z4 of the power supply / ground propagation path 13 viewed from the propagation path 12 side of the via portion is Z1≫Z4 as compared with the characteristic impedance Z1 of the power supply line propagation path 11.
[0020]
As a result, the characteristic impedance Z1 of the power supply line propagation path 11 and the power supply / ground propagation path even if the via path propagation path 12 described later is not arranged as in the conventional configuration (FIG. 5). 13 is largely mismatched, the noise signal Sn output from the noise source Vn is largely reflected, and the component absorbed in the power supply / ground propagation path 13 should be negligible. .
[0021]
However, as described in the prior art, when the via portion is disposed at the center of the printed circuit board as in the via portion (1) shown in FIG. It has been empirically understood that the radiation noise 30 increases when the via portion is disposed at the end of the printed circuit board as in (2). In order to elucidate this phenomenon, the inventor made a simulation Micro-StripesV. The following simulation was performed using 5.6.
[0022]
FIG. 3 is a diagram illustrating the principle of noise emission.
(A) is a figure showing the position of the via | veer part on each printed circuit board of board | substrate outer diameter 150mmx230mm which performed simulation. In the model A, the power supply line extends in the X-axis direction, and the via portion is disposed substantially at the center in both the X-axis direction and the Y-axis direction of the substrate. In the model B, the power supply line extends in the X-axis direction, and the via portions are arranged at the center of the substrate in the Y-axis direction and at the ends in the X-axis direction. In the model C, the power supply line extends in the X-axis direction, and the via portions are arranged at the Y-axis end and the X-axis central portion of the substrate.
[0023]
In the model D, the power supply line extends in the X-axis direction, and the via portions are arranged at the Y-axis end and the X-axis end of the substrate. In the model E, the power supply line extends in the Y-axis direction, and the via portion is disposed substantially at the center in both the X-axis direction and the Y-axis direction of the substrate. In the model F, the power supply line extends in the Y-axis direction, and the via portions are arranged at the Y-axis end and the X-axis center of the substrate.
[0024]
(B) is a figure showing the above-mentioned analysis model and a simulation result of radiation power.
The horizontal direction represents the fundamental mode resonance frequency (320 MHz) in the X-axis direction, the fundamental mode resonance frequency (490 MHz) in the Y-axis direction, and the fundamental mode resonance frequency (580 MHz) in the diagonal direction. Represents a model.
[0025]
(B), the radiation power at the fundamental mode resonance frequency is large when the via portion is arranged at the end of the printed circuit board, and small when the via portion is arranged at the center of the printed circuit board. You can see that. This result proves the facts empirically grasped in the prior art.
However, this simulation revealed that the direction in which the feed line extended did not significantly affect the radiated power. Then, the power supply electrode and the ground electrode acting as the cavity resonator can be estimated to be excited only by the almost electric field component between the power supply electrode and the ground electrode in the via portion, and to excite the radiation noise 30.
[0026]
From this fact, the inventor estimated the generation mechanism of the radiation noise 30 as follows.
(1) When a predetermined condition is satisfied, a parallel plate cavity resonator is equivalently constituted by the power supply electrode and the ground electrode. The cavity resonator resonates when the frequency of a high-frequency component (noise component) supplied from the via portion matches its own resonance frequency, and radiates a radiation noise 30 by an antenna function.
(2) A portion of the antinode of the amplitude at the time of resonance of the cavity resonator, that is, an end of the printed circuit board, corresponds to the position angle j (π / 2) of the distributed line at the receiving end and has a maximum impedance (theoretical). To infinity) position. Therefore, when the via portion is disposed at this position, the characteristic impedance Z1 of the power supply line propagation path 11 and the characteristic impedance Z4 of the power supply / ground propagation path 13 become closer to matching, and the power supply / ground propagation path 11 The supply amount of the noise signal Sn to the propagation path 13 increases. As a result, the radiation noise 30 increases.
[0027]
From the above estimation results, it was decided to reduce the radiation noise 30 by providing the via portion propagation path according to the present invention.
Returning to FIG. 2, description of the high-frequency equivalent circuit of the printed circuit board according to the present invention will be continued.
[0028]
The propagation path 12 of the via portion is a four-terminal network line including the via portion 7, the third insulating layer 6, and the ground electrode 3. When a material having a high dielectric constant ε3 is used as the third insulating layer 6 or a material having a high electrical conductivity ρ3 is used as the third insulating layer 6, the image impedance Z2 of the four-terminal network line is Z1≫Z2 as compared with the characteristic impedance Z1 of the power supply line, and prevents the characteristic impedance Z1 of the power supply line propagation path 11 and the characteristic impedance Z4 of the power supply / ground propagation path 13 from approaching matching. Can be. Furthermore, the electric field strength between the power supply electrode 1 and the ground electrode 3 which are excitation sources of the radiation noise 30 can be significantly reduced. The following experiment was performed based on the above estimation.
[0029]
<Experiment of specific example>
・ Experimental sample 1 (Comparison substrate)
In FIG. 1, FR-4 (ε1 of the first insulating layer and ε2 of the second insulating layer are 4.7) is used as a printed circuit board, and ε3 = 4.7 is used as a third insulating layer. An IC (74ALVC) was mounted on this substrate to supply a DC voltage.
[0030]
Document 2 (substrate according to the present invention)
In FIG. 1, FR-4 (ε1 of the first insulating layer and ε2 of the second insulating layer are 4.7) is used as the printed circuit board, and ε3 = 10 is used as the third insulating layer. An IC (74ALVC) was mounted on the substrate, and a DC voltage of 3.3 V was supplied.
[0031]
Measurement method A pulse train of level 0 to 2.5 V, 20 MHz was input to the IC (74ALVC) using a pulse generator (HP81100), and measurement was performed with a spectrum analyzer using a 3 m method in an anechoic chamber.
[0032]
Measurement results FIG. 4 shows a frequency spectrum of a specific example.
(A) is the measurement result of sample 1 (substrate of the comparative example), and (b) is the measurement result of sample 2 (substrate according to the present invention).
Comparing (a) and (b), the maximum value of the noise level is 64.3 dB for document 1 (substrate of the comparative example), and 62.0 dB for document 2 (substrate according to the present invention). It is improved by about 2.3 dB. Further, the number of spectrums of 40 dB or more is considerably smaller in the material 2 (the substrate according to the present invention) than in the material 1 (the substrate of the comparative example).
[0033]
Discussion of the results As described above, both ε1 of the first insulating layer and ε2 of the second insulating layer are 4.7, ε3 of the third insulating layer is 10, and the ratio of ε1 and ε2 to ε3 is about Although a large effect has not been obtained because it is twice as small, the measurement results clearly have an advantage. Therefore, it can be seen that the estimation of the emission noise generation mechanism was correct.
[0034]
Here, only the case where a material having a high dielectric constant is used for the third insulating layer 6 is shown, and no experimental result is shown for the case where a material having a high conductivity is used. However, by using a material larger than the conductivity ρ1 of the first insulation layer and the conductivity ρ2 of the second insulation layer, the conductivity ρ3 of the third insulation layer The electric field strength can be significantly reduced. As a result, it is clear that the same results as those obtained when the above-mentioned material having a high dielectric constant is used are obtained.
[0035]
In the above description, an example in which the third insulating layer 6 is disposed between the ground electrode 3 and the power electrode 1 as shown in FIG. 1 has been described, but the present invention is limited to this example. Not something. That is, a further effect can be obtained by arranging the third insulating layer 6 between the ground electrode 3 and the power supply electrode 1 and also between the power supply line 5 and the ground electrode 3. .
[0036]
Further, although the size of the third insulating layer 6 is not particularly limited, the size is not limited by the effect of the present invention and the power loss generated when a material having high conductivity is used as the third insulating layer 6. This is because the size should be determined in relation to the allowable amount, and the size should not be uniformly limited.
[0037]
【The invention's effect】
As described above, by arranging an insulating layer having a dielectric constant higher than that of the insulating layer in other parts between the power supply electrode and the ground electrode near the via portion of the printed board, The following effects can be obtained by disposing an insulating layer having a higher conductivity than the insulating layer in the other portion between the power electrode and the ground electrode near the portion.
(1) The electric field in the vicinity of the via portion can be suppressed, and the amount of radiation noise generated between the power supply electrode and the ground electrode can be reduced.
(2) As a result, there is no need to mount a magnetic loss element such as a decoupling capacitor or a ferrite on a printed circuit board, which hinders high-density mounting.
(3) Further, since there is no limit on the position of component mounting on the printed circuit board, high-density mounting is facilitated.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a printed circuit board according to the present invention.
FIG. 2 is a high-frequency equivalent circuit diagram of a printed circuit board according to the present invention.
FIG. 3 is a diagram illustrating the principle of noise emission.
FIG. 4 is a frequency spectrum of a specific example.
FIG. 5 is a configuration diagram of a conventional printed circuit board.
[Explanation of symbols]
1 power electrode (first power electrode)
2 First insulating layer 3 Ground electrode 4 Second insulating layer 5 Power supply line (second power electrode)
6 Third insulating layer 7 Via section 10 Printed circuit board

Claims (2)

A first power electrode, a first insulating layer, a ground electrode, a second insulating layer, and a second power electrode are stacked, and the second power electrode and the first power electrode are connected to each other. In a multilayer printed circuit board having a via portion to be connected,
An EMI reduction printed circuit board, comprising: a high dielectric portion having a higher dielectric constant than the first insulating layer and the second insulating layer in a predetermined range surrounding the via portion. A first power electrode, a first insulating layer, a ground electrode, a second insulating layer, and a second power electrode are stacked, and the second power electrode and the first power electrode are connected to each other. In a multilayer printed circuit board having a via portion to be connected,
An EMI reduction printed circuit board, comprising: a high conductive portion having a higher conductivity than the first insulating layer and the second insulating layer in a predetermined range surrounding the via portion.

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