JP2004079705A5

JP2004079705A5 -

Info

Publication number: JP2004079705A5
Application number: JP2002236535A
Authority: JP
Filing date: 2002-08-14
Publication date: 2005-11-04

Claims

A first circuit portion and a second circuit portion are provided on the same substrate, a first MIS transistor having a gate electrode and a source / drain semiconductor region is formed in the first circuit portion, and a gate electrode is formed in the second circuit portion. And a semiconductor integrated circuit device for forming a second MIS transistor having a semiconductor region for source / drain,
The gate electrode of the first MIS transistor is formed of a conductive film having a conductivity type opposite to the conductivity type of the semiconductor region for source / drain, and the gate electrode of the second MIS transistor is conductive of the semiconductor region for source / drain. A semiconductor integrated circuit device comprising a conductive film of the same conductivity type as the mold.

A first circuit portion and a second circuit portion are provided on the same substrate, a first MIS transistor having a gate electrode and a source / drain semiconductor region is formed in the first circuit portion, and a gate electrode is formed in the second circuit portion. And a semiconductor integrated circuit device for forming a second MIS transistor having a semiconductor region for source / drain,
The gate electrode of the first MIS transistor is formed of a silicon film into which an impurity having a conductivity type opposite to that of the semiconductor region for the source / drain is introduced, and the gate electrode of the second MIS transistor is used for the source / drain A semiconductor integrated circuit device comprising a silicon film into which an impurity having the same conductivity type as that of the semiconductor region is introduced.

3. The semiconductor integrated circuit device according to claim 1, wherein the first circuit unit includes an input / output circuit of an SRAM memory cell, and the second circuit unit includes a sense amplifier circuit or a word driver circuit. Semiconductor integrated circuit device.

A first circuit portion and a second circuit portion are provided on the same substrate, a first MIS transistor having a gate electrode and a source / drain semiconductor region is formed in the first circuit portion, and a gate electrode is formed in the second circuit portion. And a method of manufacturing a semiconductor integrated circuit device for forming a second MIS transistor provided with a semiconductor region for source / drain,
The gate electrode of the first MIS transistor is formed of a silicon film doped with an impurity having a conductivity type opposite to that of the semiconductor region for the source / drain, and the gate electrode of the second MIS transistor is used for the source / drain. Formed of a silicon film doped with impurities of the same conductivity type as that of the semiconductor region,
An n-type extension region formed by introducing an n-type impurity into the substrate on both sides of the gate electrode and an n-type diffusion region formed by introducing an n-type impurity into the substrate on both sides of the sidewall provided on the sidewall of the gate electrode, A p-type diffusion region is formed by forming a semiconductor region for the source / drain of the n-channel type first MIS transistor and introducing p-type impurities into the substrate on both sides of the side wall provided on the side wall of the gate electrode. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a semiconductor region for a source / drain of the channel-type first MIS transistor.

A first circuit portion and a second circuit portion are provided on the same substrate, a first MIS transistor having a gate electrode and a source / drain semiconductor region is formed in the first circuit portion, and a gate electrode is formed in the second circuit portion. And a method of manufacturing a semiconductor integrated circuit device for forming a second MIS transistor provided with a semiconductor region for source / drain,
The gate electrode of the first MIS transistor is formed of a silicon film doped with an impurity having a conductivity type opposite to that of the semiconductor region for the source / drain, and the gate electrode of the second MIS transistor is used for the source / drain. Formed of a silicon film doped with impurities of the same conductivity type as that of the semiconductor region,
An n-type extension region formed by introducing an n-type impurity into the substrate on both sides of the gate electrode and an n-type diffusion region formed by introducing an n-type impurity into the substrate on both sides of the sidewall provided on the sidewall of the gate electrode, A p-type extension region formed by forming a semiconductor region for the source / drain of the n-channel type first MIS transistor and introducing p-type impurities into the substrate on both sides of the gate electrode, and a sidewall provided on the side wall of the gate electrode The semiconductor region for the source / drain of the p-channel type first MIS transistor is formed by p-type diffusion regions formed by introducing p-type impurities into the substrates on both sides of the semiconductor integrated circuit device. Method.

A semiconductor integrated circuit device having an n-channel MIS transistor and a p-channel MIS transistor in a first region of a semiconductor substrate, and an n-channel MIS transistor and a p-channel MIS transistor in a second region of the semiconductor substrate. ,
The n-channel MIS transistor in the first region includes a gate electrode including an impurity exhibiting p-type conductivity, and a source / drain region including an impurity exhibiting n-type conductivity,
The p-channel MIS transistor in the first region has a gate electrode containing an impurity exhibiting n-type conductivity, and a source / drain region containing an impurity exhibiting p-type conductivity,
The n-channel MIS transistor in the second region has a gate electrode containing an impurity exhibiting n-type conductivity, and a source / drain region containing an impurity exhibiting n-type conductivity,
The p-channel MIS transistor in the second region includes a gate electrode including an impurity exhibiting p-type conductivity, and a source / drain region including an impurity exhibiting p-type conductivity. Integrated circuit device.

The semiconductor integrated circuit device according to claim 6.
The threshold voltage when the n-channel MIS transistor and the p-channel MIS transistor in the first region operate is the threshold voltage when the n-channel MIS transistor and the p-channel MIS transistor in the second region operate. A semiconductor integrated circuit device characterized in that each of the threshold voltages is larger than the threshold voltage.

The semiconductor integrated circuit device according to claim 6 or 7,
A semiconductor integrated circuit device, wherein silicide layers are formed on the source / drain regions of the n-channel MIS transistor and the p-channel MIS transistor in the first region and the second region, respectively. .

The semiconductor integrated circuit device according to claim 8.
The silicide layer is also formed on the gate electrodes of the n-channel MIS transistor and the p-channel MIS transistor in the first region and the second region, respectively. .