JP2004079578A5 - - Google Patents

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JP2004079578A5
JP2004079578A5 JP2002233756A JP2002233756A JP2004079578A5 JP 2004079578 A5 JP2004079578 A5 JP 2004079578A5 JP 2002233756 A JP2002233756 A JP 2002233756A JP 2002233756 A JP2002233756 A JP 2002233756A JP 2004079578 A5 JP2004079578 A5 JP 2004079578A5
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semiconductor chip
region
solid
semiconductor device
state imaging
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JP2004079578A (en
JP4352664B2 (en
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複数の光電変換素子により被写体の撮像を行う固体撮像素子形成領域と、周辺回路領域とを同一基板上に形成した半導体チップを有し、
前記半導体チップの固体撮像素子形成領域は湾曲されて形成され、前記周辺回路領域が平坦に形成されている、
ことを特徴とする半導体装置。A solid-state imaging element forming region for imaging a subject by a plurality of photoelectric conversion elements, and a semiconductor chip in which a peripheral circuit region is formed on the same substrate;
The solid-state imaging element forming region of the semiconductor chip is formed to be curved, and the peripheral circuit region is formed flat.
A semiconductor device. 前記周辺回路領域は前記固体撮像素子形成領域の各素子の駆動回路又は信号処理回路の少なくとも一方を含むことを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the peripheral circuit region includes at least one of a drive circuit and a signal processing circuit for each element in the solid-state imaging device formation region. 前記半導体チップは、前記固体撮像素子形成領域と同一基板上に形成され該固体撮像素子形成領域の各素子と外部回路とを接続するための電極パッド領域を有し、前記半導体チップの電極パッド領域は平坦に形成されていることを特徴とする請求項１記載の半導体装置。  The semiconductor chip has an electrode pad area formed on the same substrate as the solid-state imaging element forming area and for connecting each element of the solid-state imaging element forming area to an external circuit, and the electrode pad area of the semiconductor chip The semiconductor device according to claim 1, wherein the semiconductor device is flat. 前記半導体チップを実装する実装用基板を有し、前記実装用基板に設けられた応力付与手段によって前記半導体チップの基板面方向に応力を付与することにより、前記固体撮像素子形成領域が湾曲されていることを特徴とする請求項１記載の半導体装置。  The solid-state imaging element forming region is curved by having a mounting substrate for mounting the semiconductor chip, and applying stress in the substrate surface direction of the semiconductor chip by a stress applying means provided on the mounting substrate. The semiconductor device according to claim 1, wherein: 前記半導体チップの周辺回路領域を設けた部分が、前記固体撮像素子形成領域を設けた部分に対して半導体チップの裏面方向に折れ曲がっていることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein a portion of the semiconductor chip provided with a peripheral circuit region is bent in a back surface direction of the semiconductor chip with respect to a portion provided with the solid-state imaging element forming region. 複数の光電変換素子により被写体の撮像を行う固体撮像素子形成領域と、前記固体撮像素子形成領域の各素子と外部回路とを接続するための電極パッド領域とを同一基板上に形成した半導体チップを有し、
前記半導体チップの固体撮像素子形成領域が所定の曲率で湾曲されて形成され、前記電極パッド領域が平坦に形成されている、
ことを特徴とする半導体装置。A semiconductor chip in which a solid-state image sensor formation region for imaging a subject by a plurality of photoelectric conversion elements and an electrode pad region for connecting each element of the solid-state image sensor formation region and an external circuit are formed on the same substrate Have
The solid-state imaging element forming region of the semiconductor chip is formed with a predetermined curvature and the electrode pad region is formed flat.
A semiconductor device. 前記半導体チップを実装する実装用基板を有し、前記実装用基板に設けられた応力付与手段によって前記半導体チップの基板面方向に応力を付与することにより、前記固体撮像素子形成領域が湾曲されていることを特徴とする請求項５記載の半導体装置。  The solid-state imaging element forming region is curved by having a mounting substrate for mounting the semiconductor chip, and applying stress in the substrate surface direction of the semiconductor chip by a stress applying means provided on the mounting substrate. 6. The semiconductor device according to claim 5, wherein: 前記半導体チップが前記電極パッド領域を介して前記実装用基板に設けられた回路配線に接続されていることを特徴とする請求項７記載の半導体装置。  8. The semiconductor device according to claim 7, wherein the semiconductor chip is connected to circuit wiring provided on the mounting substrate via the electrode pad region. 複数の光電変換素子により被写体の撮像を行う固体撮像素子形成領域と、周辺回路領域とを同一基板上に形成した半導体チップを有する半導体装置の製造方法であって、A method of manufacturing a semiconductor device having a semiconductor chip in which a solid-state imaging element forming region for imaging a subject by a plurality of photoelectric conversion elements and a peripheral circuit region are formed on the same substrate,
前記半導体チップの固体撮像素子形成領域を湾曲して形成し、前記周辺回路領域を平坦に形成する、Forming the solid-state imaging element forming region of the semiconductor chip by curving and forming the peripheral circuit region flat;
ことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device. 前記周辺回路領域は前記固体撮像素子形成領域の各素子の駆動回路又は信号処理回路の少なくとも一方を含むことを特徴とする請求項９記載の半導体装置の製造方法。10. The method of manufacturing a semiconductor device according to claim 9, wherein the peripheral circuit region includes at least one of a drive circuit and a signal processing circuit for each element in the solid-state imaging device formation region. 前記半導体チップを前記固体撮像素子形成領域と同一基板上に形成して、該固体撮像素子形成領域の各素子と外部回路とを接続するための電極パッド領域を設け、前記半導体チップの電極パッド領域を平坦に形成することを特徴とする請求項９記載の半導体装置の製造方法。The semiconductor chip is formed on the same substrate as the solid-state image sensor formation region, and an electrode pad region for connecting each element of the solid-state image sensor formation region and an external circuit is provided, and the electrode pad region of the semiconductor chip The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor device is formed flat. 前記半導体チップを実装する実装用基板を設け、前記実装用基板に設けられた応力付与手段によって前記半導体チップの基板面方向に応力を付与することにより、前記固体撮像素子形成領域を湾曲することを特徴とする請求項９記載の半導体装置の製造方法。A mounting substrate for mounting the semiconductor chip is provided, and the solid-state imaging element forming region is curved by applying stress in the substrate surface direction of the semiconductor chip by a stress applying means provided on the mounting substrate. The method for manufacturing a semiconductor device according to claim 9, wherein: 前記半導体チップの周辺回路領域を設けた部分を、前記固体撮像素子形成領域を設けた部分に対して半導体チップの裏面方向に折れ曲げることを特徴とするA portion of the semiconductor chip provided with a peripheral circuit region is bent in a back surface direction of the semiconductor chip with respect to a portion provided with the solid-state imaging element formation region. 請求項９記載の半導体装置の製造方法。A method for manufacturing a semiconductor device according to claim 9. 複数の光電変換素子により被写体の撮像を行う固体撮像素子形成領域と、前記固体撮像素子形成領域の各素子と外部回路とを接続するための電極パッド領域とを同一基板上に形成した半導体チップを有する半導体装置の製造方法であって、A semiconductor chip in which a solid-state image sensor formation region for imaging a subject by a plurality of photoelectric conversion elements and an electrode pad region for connecting each element of the solid-state image sensor formation region and an external circuit are formed on the same substrate A method for manufacturing a semiconductor device comprising:
前記半導体チップの固体撮像素子形成領域を所定の曲率で湾曲して形成し、前記電極パッド領域を平坦に形成する、Forming the solid-state imaging element formation region of the semiconductor chip with a predetermined curvature and forming the electrode pad region flat;
ことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device. 前記半導体チップを実装する実装用基板を設け、前記実装用基板に設けられた応力付与手段によって前記半導体チップの基板面方向に応力を付与することにより、前記固体撮像素子形成領域を湾曲することを特徴とする請求項１４記載の半導体装置の製造方法。A mounting substrate for mounting the semiconductor chip is provided, and the solid-state imaging element forming region is curved by applying stress in the substrate surface direction of the semiconductor chip by a stress applying means provided on the mounting substrate. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the method is a semiconductor device. 前記半導体チップを前記電極パッド領域を介して前記実装用基板に設けられた回路配線に接続することを特徴とする請求項１５記載の半導体装置の製造方法。16. The method of manufacturing a semiconductor device according to claim 15, wherein the semiconductor chip is connected to circuit wiring provided on the mounting substrate through the electrode pad region.
JP2002233756A 2002-08-09 2002-08-09 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4352664B2 (en)

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JP2002233756A JP4352664B2 (en) 2002-08-09 2002-08-09 Semiconductor device and manufacturing method thereof

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JP2004079578A JP2004079578A (en) 2004-03-11
JP2004079578A5 true JP2004079578A5 (en) 2005-10-20
JP4352664B2 JP4352664B2 (en) 2009-10-28

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Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
JP4806957B2 (en) * 2005-05-12 2011-11-02 コニカミノルタオプト株式会社 Imaging device
JP4969237B2 (en) * 2006-12-25 2012-07-04 パナソニック株式会社 Solid-state imaging device and manufacturing method thereof
JP5676171B2 (en) * 2010-07-26 2015-02-25 シャープ株式会社 Solid-state imaging device, manufacturing method thereof, and electronic apparatus
JP5724322B2 (en) * 2010-11-24 2015-05-27 ソニー株式会社 Method for manufacturing solid-state imaging device
JP5720305B2 (en) * 2011-02-28 2015-05-20 ソニー株式会社 Solid-state imaging device manufacturing method, solid-state imaging device, and electronic apparatus
US8878116B2 (en) * 2011-02-28 2014-11-04 Sony Corporation Method of manufacturing solid-state imaging element, solid-state imaging element and electronic apparatus
JP5720304B2 (en) * 2011-02-28 2015-05-20 ソニー株式会社 Solid-state imaging device and electronic device
JP5720306B2 (en) * 2011-02-28 2015-05-20 ソニー株式会社 Manufacturing method of solid-state imaging device
JP6491519B2 (en) * 2015-04-02 2019-03-27 キヤノン株式会社 Imaging device and imaging apparatus

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