JP2004074792A - Semiconductor silicon wafer, its manufacturing process and wire guided roll of wire saw for manufacturing semiconductor wafer - Google Patents

Semiconductor silicon wafer, its manufacturing process and wire guided roll of wire saw for manufacturing semiconductor wafer Download PDF

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Publication number
JP2004074792A
JP2004074792A JP2003207478A JP2003207478A JP2004074792A JP 2004074792 A JP2004074792 A JP 2004074792A JP 2003207478 A JP2003207478 A JP 2003207478A JP 2003207478 A JP2003207478 A JP 2003207478A JP 2004074792 A JP2004074792 A JP 2004074792A
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Prior art keywords
semiconductor wafer
wire
saw
manufacturing
guide roll
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Inventor
Gerhard Palme
ゲアハルト パルメ
Maximilian Kaeser
マクシミリアン ケーザー
Manfred Grundner
マンフレート グルントナー
Johann Steiner
ヨハン シュタイナー
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Siltronic AG
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Wacker Siltronic AG
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Publication of JP2004074792A publication Critical patent/JP2004074792A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23DPLANING; SLOTTING; SHEARING; BROACHING; SAWING; FILING; SCRAPING; LIKE OPERATIONS FOR WORKING METAL BY REMOVING MATERIAL, NOT OTHERWISE PROVIDED FOR
    • B23D57/00Sawing machines or sawing devices not covered by one of the preceding groups B23D45/00 - B23D55/00
    • B23D57/003Sawing machines or sawing devices working with saw wires, characterised only by constructional features of particular parts
    • B23D57/0053Sawing machines or sawing devices working with saw wires, characterised only by constructional features of particular parts of drives for saw wires; of wheel mountings; of wheels
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/04Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools
    • B28D5/045Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools by cutting with wires or closed-loop blades

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Weting (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor silicon wafer which can be manufactured inexpensively while satisfying requirements as a base material for manufacturing an electronic component. <P>SOLUTION: The semiconductor silicon wafer as a base material for manufacturing the electronic component having a gloss of at least 70 % and a roughness R<SB>a</SB>of 0.1 μm to 0.5 μm. The roughness is achieved by wire cutting a single crystal as the only mechanical operation in the manufacturing of the semiconductor wafer. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明の対象はシリコンからなる半導体ウェーハおよびその製造方法である。
【0002】
【従来の技術】
シリコンからなる半導体ウェーハは電子部品を製造するための基材である。この目的に適した半導体ウェーハはできる限り平坦である少なくとも1個の側面を有していなければならない。従ってこの種の特性を有する側面を生じる、複数の機械的処理工程を用意することが一般的である。これらの機械的処理工程には単結晶からの半導体ウェーハの分離、半導体ウェーハのラッピング、研削およびポリッシングが挙げられる。
【0003】
【発明が解決しようとする課題】
本発明の課題は、安い費用で製造することができ、それにもかかわらず電子部品の製造のために基材に課せられる要求を満足するシリコンからなる半導体ウェーハを提供することである。
【0004】
【課題を解決するための手段】
前記課題は、本発明により解決される。
【0005】
本発明の対象は、電子部品を製造するための基材としてのシリコンからなる半導体ウェーハであり、少なくとも70%の光沢および0.1μm〜0.5μmの粗さRを有することを特徴とし、前記粗さが半導体ウェーハを製造する際に唯一の機械的処理工程として単結晶のワイヤー切断により達成される。
【0006】
半導体ウェーハは、有利には電子電力部品を製造するための基材として使用される。
【0007】
本発明の対象は、更に、半導体ウェーハを多数の半導体ウェーハと一緒に、ワイヤー案内ロールの溝内を走行するワイヤーソーのソーワイヤーを存在させて、単結晶から分離する、シリコンからなる半導体ウェーハの製造方法であり、半導体ウェーハを製造する際の唯一の機械的処理工程であるワイヤー切断により半導体ウェーハを分離することを特徴とする。
【0008】
意想外にも、本発明による半導体ウェーハを製造するために、ワイヤー切断の−ほかにラッピング、研削またはポリッシングのような他の機械的処理工程は必要でない。分離方法の実施に応じて半導体ウェーハの光沢を高めるおよび粗さを減少するための他の非機械的処理工程が有利である。他の機械的処理工程の節約により本発明の方法は特に経済的である。
【0009】
本発明により製造される半導体ウェーハは少なくとも100μm、有利には100〜300μmの厚さを有し、従ってかなり薄い。ワイヤー切断の際に多数のこれらの半導体ウェーハが同時に形成される。ソーワイヤーはワイヤーソーのワイヤー案内ロールに巻き付けられ、この巻き体に沿って移動する。ソーワイヤーに結合しているかまたは切断用懸濁液の形で添加され、ソーワイヤーにより切断位置に搬送される研磨材が半導体ウェーハの分離に必要な材料の切除を生じる。ソーワイヤーは一定の摩耗を受け、この摩耗は利用する際に半導体ウェーハを分離する該当する部分が長いほど、ソーワイヤーのこの部分で大きい。これは、半導体ウェーハを単結晶の一方の端部でソーワイヤーの部分を存在させて分離し、ソーワイヤーが摩耗のために薄くなっているので、単結晶から分離した半導体ウェーハの厚さ分布に不利に作用する。これらの半導体ウェーハは、単結晶の他の端部に由来し、そのためになお負荷を受けないかまたは負荷が少ないソーワイヤーの部分の存在で分離した半導体ウェーハより厚い。
【0010】
本発明の枠内で、ワイヤー案内ロール上の溝の間隔を同じでなく形成することによりこの不利な作用を防ぐことが配慮される。ソーワイヤーの溝の間隔および直径が分離された半導体ウェーハの厚さに決定的に影響するので、摩耗により減少するワイヤー直径に相当して狭くなる溝間隔を対応することが提案される。これにより多くの同時に分離した半導体ウェーハの厚さ分布がきわめて狭くなる。特に有利には厚さ分布、従って目標値からのウェーハ厚さの実際値の誤差はソー断面で得られる半導体ウェーハの数に対して多くても±10μm、特に有利には±5μmである。
【0011】
起伏が少ない半導体ウェーハを形成する、ワイヤー切断法を使用することが有利である。この方法は、例えばドイツ特許(A1)第10054265号明細書に記載されている。この方法の重要な特徴は、ワイヤー移動方向が繰り返して変更され(振動法)、同じワイヤー速度を有する位相がソーワイヤーが加速または減速する位相より明らかに短いことである。特に有利にはドイツ特許(A1)第10054265号明細書に示される、一定の速度の位相の時間と0.5未満の速度増加または速度減少の位相の時間との関係である。
【0012】
DIN4774により起伏度Wtは、測定区間の起伏断面の最も高い位置と最も低い位置の間の垂直な距離として定義される。分離された半導体ウェーハの起伏度は多くても8μm、特に有利には多くても3μmである。
【0013】
半導体ウェーハの光沢は、光、例えばレーザー光線を40〜80°の所定の角度で、有利には60°で半導体ウェーハに照射し、反射した割合を測定することにより測定する。これに関する基準としてDIN67530/ISO2813による規格Aを用いる。本発明による半導体ウェーハは少なくとも70%、特に有利には少なくとも90%の光沢および0.1〜0.5μm、特に有利には0.15〜0.35μmの粗さRを有する。
【0014】
DIN4768により粗さRは全部の断面の中心線からの粗い断面のすべての誤差の算術平均値である。粗さは市販されている測定装置、例えばいわゆるペルソメーター(Perthometer)を使用して、決められた距離、例えば5mmを測定針で触診し、前記の誤差を測定することにより測定する。
【0015】
半導体ウェーハの光沢を高め、粗さを減少するために、以下の手段が提案される。
【0016】
単結晶からワイヤー切断により分離した半導体ウェーハをエッチングし、エッチングが半導体ウェーハの光沢および粗さを改良する唯一の処理工程である。
【0017】
単結晶からワイヤー切断により分離した半導体ウェーハをエッチングし、引き続き清浄化し、エッチングおよび清浄化が半導体ウェーハの光沢および粗さを改良するこの方法の唯一の処理工程である。
【0018】
半導体ウェーハのエッチングの際に、有利には硝酸(HNO)を有するエッチング剤を使用する。損傷した表面の近くの結晶領域(ダメージ)を除去するために、エッチングによりウェーハ側面当たり35μmまで、有利には8〜12μmの材料の切除が達成されることが有利である。
【0019】
半導体ウェーハの清浄化の際に、有利には界面活性剤を有する清浄化剤を使用する。
【0020】
【実施例】
図1A、1Bには異なるワイヤー案内ロールを使用する点でのみ異なる、本発明による2つの分離法の結果が対比されて示されている。方法A(図1A)においては溝の間隔が同じワイヤー案内ロールが使用され、方法B(図1B)においてはワイヤー導入側からワイヤー排出側に狭くなっている溝間隔を有するワイヤー案内ロールが使用される。図1A、1Bは得られた半導体ウェーハの溝間隔および厚さ分布を拡大して示す。方法Bによりほぼ均一な厚さの半導体ウェーハが得られる。
【図面の簡単な説明】
【図1A】溝の間隔が同じワイヤー案内ロールを使用して得られた半導体ウェーハの溝間隔および厚さ分布を示す図である。
【図1B】ワイヤー導入側からワイヤー排出側に狭くなっている溝間隔を有するワイヤー案内ロールを使用して得られた半導体ウェーハの溝間隔および厚さ分布を示す図である。
[0001]
TECHNICAL FIELD OF THE INVENTION
An object of the present invention is a semiconductor wafer made of silicon and a method for manufacturing the same.
[0002]
[Prior art]
A semiconductor wafer made of silicon is a base material for manufacturing electronic components. Semiconductor wafers suitable for this purpose must have at least one side that is as flat as possible. Therefore, it is common to provide a plurality of mechanical processing steps that result in aspects having such properties. These mechanical processing steps include separation of the semiconductor wafer from the single crystal, lapping, grinding and polishing of the semiconductor wafer.
[0003]
[Problems to be solved by the invention]
It is an object of the present invention to provide a semiconductor wafer made of silicon which can be manufactured at a low cost and which nevertheless satisfies the requirements imposed on the substrate for the production of electronic components.
[0004]
[Means for Solving the Problems]
The object is achieved by the present invention.
[0005]
The object of the present invention is a semiconductor wafer made of silicon as a substrate for producing electronic components, characterized in that it has a gloss of at least 70% and a roughness Ra of 0.1 μm to 0.5 μm, Said roughness is achieved by single crystal wire cutting as the only mechanical processing step in manufacturing semiconductor wafers.
[0006]
Semiconductor wafers are advantageously used as substrates for producing electronic power components.
[0007]
The subject of the present invention is furthermore a semiconductor wafer comprising silicon, together with a large number of semiconductor wafers, in which the saw wire of a wire saw running in the groove of the wire guide roll is present and separated from the single crystal, This is a manufacturing method, characterized in that the semiconductor wafer is separated by wire cutting, which is the only mechanical processing step when manufacturing the semiconductor wafer.
[0008]
Surprisingly, no other mechanical processing steps, such as lapping, grinding or polishing, are required besides wire cutting to produce a semiconductor wafer according to the invention. Other non-mechanical processing steps for increasing the gloss and reducing the roughness of the semiconductor wafer depending on the implementation of the separation method are advantageous. The method of the present invention is particularly economical due to savings in other mechanical processing steps.
[0009]
The semiconductor wafer produced according to the invention has a thickness of at least 100 μm, preferably 100-300 μm, and is therefore quite thin. A large number of these semiconductor wafers are formed simultaneously during wire cutting. The saw wire is wound around a wire guide roll of the wire saw and moves along the winding body. Abrasive material that is bonded to the saw wire or added in the form of a cutting suspension and conveyed to the cutting location by the saw wire results in ablation of the material required for semiconductor wafer separation. The saw wire is subject to a certain amount of wear, and this wear is greater in this part of the saw wire, the longer the corresponding part separating the semiconductor wafer in use. This is because the semiconductor wafer is separated by the presence of a saw wire portion at one end of the single crystal, and the thickness distribution of the semiconductor wafer separated from the single crystal is reduced because the saw wire is thinned due to wear. Acts disadvantageously. These semiconductor wafers are derived from the other end of the single crystal and are therefore thicker than semiconductor wafers separated by the presence of portions of the saw wire that are still unloaded or lightly loaded.
[0010]
Within the framework of the present invention, care is taken to prevent this disadvantageous effect by making the spacing of the grooves on the wire guide roll unequal. Since the spacing and diameter of the saw wire grooves have a decisive effect on the thickness of the separated semiconductor wafers, it is proposed to accommodate a groove spacing that is reduced correspondingly to the reduced wire diameter due to wear. This results in a very narrow thickness distribution of many simultaneously separated semiconductor wafers. Particularly preferably, the error of the actual value of the thickness distribution and thus of the wafer thickness from the target value is at most ± 10 μm, particularly preferably ± 5 μm, relative to the number of semiconductor wafers obtained in the saw section.
[0011]
It is advantageous to use a wire cutting method that forms a semiconductor wafer with less undulations. This method is described, for example, in DE-A 100 54 265. An important feature of this method is that the direction of wire movement is repeatedly changed (oscillation method), and the phase with the same wire speed is clearly shorter than the phase at which the saw wire accelerates or decelerates. Particular preference is given to the relation between the time of a constant speed phase and the time of a speed increase or decrease phase of less than 0.5, as shown in DE 100 54 265 A1.
[0012]
According to DIN 4774, the undulation Wt is defined as the vertical distance between the highest and lowest positions of the undulating section of the measurement section. The degree of undulation of the separated semiconductor wafer is at most 8 μm, particularly preferably at most 3 μm.
[0013]
The gloss of a semiconductor wafer is measured by irradiating the semiconductor wafer with light, for example a laser beam, at a predetermined angle between 40 and 80 °, preferably at 60 °, and measuring the percentage of reflection. The standard A according to DIN 67530 / ISO 2813 is used as a standard for this. Semiconductor wafer according to the present invention is at least 70%, more preferably at least 90% of the gloss and 0.1 to 0.5 [mu] m, particularly preferably has a roughness R a of 0.15~0.35Myuemu.
[0014]
According to DIN 4768, the roughness Ra is the arithmetic mean of all the errors of the coarse section from the center line of all the sections. The roughness is measured by using a commercially available measuring device, for example, a so-called Perthometer, by palpating a predetermined distance, for example, 5 mm with a measuring needle, and measuring the above-mentioned error.
[0015]
In order to increase the gloss and reduce the roughness of the semiconductor wafer, the following measures are proposed.
[0016]
Etching a semiconductor wafer separated from a single crystal by wire cutting, and etching is the only processing step that improves the gloss and roughness of the semiconductor wafer.
[0017]
Etching and subsequently cleaning a semiconductor wafer separated from a single crystal by wire cutting is the only processing step in this method that improves the gloss and roughness of the semiconductor wafer.
[0018]
During the etching of the semiconductor wafer, an etchant with nitric acid (HNO 3 ) is preferably used. Advantageously, etching removes up to 35 μm, preferably 8-12 μm, of material per wafer side by etching to remove crystalline areas (damage) near the damaged surface.
[0019]
During the cleaning of the semiconductor wafer, a cleaning agent with a surfactant is preferably used.
[0020]
【Example】
1A and 1B contrast the results of two separation methods according to the invention, which differ only in that different wire guide rolls are used. In method A (FIG. 1A), a wire guide roll having the same groove interval is used, and in method B (FIG. 1B), a wire guide roll having a groove interval narrowing from the wire introduction side to the wire discharge side is used. You. 1A and 1B are enlarged views showing the groove spacing and thickness distribution of the obtained semiconductor wafer. According to the method B, a semiconductor wafer having a substantially uniform thickness is obtained.
[Brief description of the drawings]
FIG. 1A is a diagram showing groove spacing and thickness distribution of a semiconductor wafer obtained using a wire guide roll having the same groove spacing.
FIG. 1B is a diagram showing a groove interval and a thickness distribution of a semiconductor wafer obtained by using a wire guide roll having a groove interval narrowing from a wire introduction side to a wire discharge side.

Claims (8)

電子部品を製造するための基材としてのシリコンからなる半導体ウェーハにおいて、前記半導体ウェーハが少なくとも70%の光沢および0.1μm〜0.5μmの粗さRを有し、前記粗さが半導体ウェーハを製造する際に唯一の機械的処理工程として単結晶のワイヤー切断により達成されることを特徴とするシリコンからなる半導体ウェーハ。A semiconductor wafer made of silicon as a substrate for the production of electronic components, the semiconductor wafer has a roughness R a of at least 70% of the gloss and 0.1 .mu.m to 0.5 .mu.m, the roughness is a semiconductor wafer A semiconductor wafer made of silicon, which is achieved by cutting a single crystal wire as the only mechanical processing step when manufacturing the semiconductor wafer. 半導体ウェーハが帯域引き上げされたシリコンからなり、電子電力部品を製造するための基材である請求項1記載の半導体ウェーハ。2. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is made of band-raised silicon and is a base material for manufacturing electronic power components. 半導体ウェーハを多数の半導体ウェーハと一緒に、ワイヤー案内ロールの溝内を走行するワイヤーソーのソーワイヤーを存在させて、単結晶から分離する、シリコンからなる半導体ウェーハの製造方法において、半導体ウェーハを製造する際の唯一の機械的処理工程であるワイヤー切断により半導体ウェーハを分離することを特徴とする半導体ウェーハの製造方法。In a method of manufacturing a semiconductor wafer made of silicon, the semiconductor wafer is separated from a single crystal by allowing a saw wire of a wire saw running in a groove of a wire guide roll to be present together with a large number of semiconductor wafers. A method for manufacturing a semiconductor wafer, comprising: separating a semiconductor wafer by wire cutting, which is the only mechanical processing step when performing the process. ソーワイヤーがワイヤー案内ロールの溝内を走行し、溝が軸方向に互いに離れており、その際隣接する溝の間隔はワイヤー案内ロールの一方の端部からワイヤーロールの反対側の端部に向かって狭くなっている請求項3記載の方法。The saw wire runs in the groove of the wire guide roll, the grooves being axially separated from one another, with the spacing between adjacent grooves from one end of the wire guide roll to the opposite end of the wire roll. 4. The method of claim 3, wherein the width is reduced. 分離した半導体ウェーハをエッチングし、エッチングがこの方法の半導体ウェーハの光沢を高める唯一の処理工程である請求項3または4記載の方法。5. The method according to claim 3, wherein the separated semiconductor wafer is etched, and etching is the only processing step for increasing the gloss of the semiconductor wafer in this method. 分離した半導体ウェーハをエッチングし、清浄化し、エッチングおよび清浄化がこの方法の半導体ウェーハの光沢を高める唯一の処理工程である請求項3または4記載の方法。5. The method according to claim 3, wherein the separated semiconductor wafer is etched and cleaned, and the etching and cleaning are the only processing steps for increasing the gloss of the semiconductor wafer in this method. 多数の分離した半導体ウェーハが鋸断面に対して多くても±10μmの厚さ分布を有する請求項4から6までのいずれか1項記載の方法。7. The method according to claim 4, wherein the plurality of separated semiconductor wafers have a thickness distribution of at most. +-. 10 .mu.m with respect to the saw section. 軸方向に互いに離れており、ソーワイヤーの収容のために用いる溝を有するワイヤーソーのためのワイヤー案内ロールにおいて、隣接する溝の間隔がワイヤー案内ロールの一方の端部で、ワイヤー案内ロールの反対側の端部より狭くなっていることを特徴とするワイヤーソーのためのワイヤー案内ロール。In a wire guide roll for a wire saw axially separated from each other and having a groove used for receiving the saw wire, the distance between adjacent grooves is at one end of the wire guide roll and opposite to the wire guide roll. A wire guide roll for a wire saw, characterized in that it is narrower than the side end.
JP2003207478A 2002-08-14 2003-08-13 Semiconductor silicon wafer, its manufacturing process and wire guided roll of wire saw for manufacturing semiconductor wafer Pending JP2004074792A (en)

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