JP2004071041A - Device and method for information processing, program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable decoding processing by switching between quenching correction, mixture correction, and non-correction by using an error detection result when the error is detected by identification data, and by using the parity effectively. <P>SOLUTION: A position of a detected sync error is stored, a C1 error position indicating the position of the error, which cannot be corrected by C1 decoding, is stored, and the position of over write protect (OWP) error is stored. Then, In S31 of the decoding processing of a C2 code, it is decided whether or not the sum of the number of sync errors, the number of OWP errors and the number of C1 errors is below the number of parities of C2 decoding C2tmax. If the sum is below C2tmax, quenching correction processing is executed in S32. When it is decided in S34 that the sum of the number of sync errors and the number of OWP errors is below the number of parities C2tmax, mixture correction processing is performed in S35; otherwise, the C2 decoding process is completed by way of S37. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus and method, a program, and a recording medium for correcting a data error that occurs when recording cannot be performed normally during recording.
[0002]
[Prior art]
2. Description of the Related Art An error correction technique for correcting an error generated on a transfer path of data transferred by communication or on a recording medium is becoming popular. However, in the conventional error correction device, an error of reproduced data is considered, but a data error when data cannot be normally recorded during recording is not considered. For example, when digital data is recorded by a magnetic recording head mounted on a rotating drum, the magnetic recording head may be caught on the magnetic tape due to the instantaneous clogging of the magnetic recording head, debris on the magnetic tape, and folds of the magnetic tape. In some cases, recording data is not normally recorded on the magnetic tape despite scanning of. Not only in the rotary head type VTR but also in a disk recording / reproducing apparatus, the same problem may occur due to the presence of fingerprints, dust, and the like.
[0003]
Such a state is called instantaneous recording clog, and when reproducing a magnetic tape in this state, generally, there are many errors and normal data cannot be reproduced, or there is no error, but the data before and after the recorded data In some cases, unrelated data recorded in the past (hereinafter, appropriately referred to as background data) may be reproduced. In the latter case, it is generally difficult to perform error detection using the inner code parity of the error correction inner code added in sync block units. If the outer code parity of the outer code for error correction is added, there is a possibility that the error sync block is detected by solving the outer code for error correction.
[0004]
The inner code and the outer code mean an error correction code in the product code. In other words, a predetermined number of symbols, for example, bytes, which are aligned in the vertical direction of the two-dimensional array of data to be error-corrected, are encoded with an outer code (hereinafter, appropriately referred to as C2 code), and an outer code parity (hereinafter, referred to as C2 code). , Where appropriate referred to as C2 parity). A predetermined number of C2 parities or data arranged in the horizontal direction of the two-dimensional array are encoded with an inner code (hereinafter, appropriately referred to as C1 code), and an inner code parity (hereinafter, appropriately referred to as C1 parity) is generated. Is done. C2 parity or data and C1 parity aligned horizontally are included in the same sync block. Continuous data of the sync block is recorded on the magnetic tape.
[0005]
In the product code, each symbol is doubly encoded with a C2 code and a C1 code. Therefore, even if an error cannot be detected by the decoding process of the C1 code, the error is detected by the C2 code, and the error is corrected by the C2 code if the detected error is within a correctable range. However, detecting and correcting an error with the C2 code means that the C2 parity is consumed for detecting a sync block in which an instantaneous clog has occurred, which leads to a decrease in the ability to correct other random errors.
[0006]
As a countermeasure against such a recording instantaneous clog, when newly performing overwrite recording on a tape on which a base has already been recorded, identification data (hereinafter referred to as OWP (Over Write Protect) as appropriate, which is clearly different from the base). Is recorded. For example, an OWP having a length of 1 byte is used, and the value of the OWP is randomly changed every time recording is performed. OWP is inserted into each sync block.
[0007]
At the time of reproduction, in order to determine whether the OWP is the OWP of the base portion or the OWP recorded by overwriting, several tracks immediately after the start of overwriting recording are different from the normal recording track, and there are many sync blocks with OWP in the valid data section. There is a method of recording and acquiring this sync block at the time of reproduction, thereby making it possible to determine what the value of the OWP after this track is. This method has a very high probability that a correct value of OWP after the overwritten track can be obtained. On the other hand, the OWP is recorded in an effective data portion where video data or the like can be originally recorded. There is a problem.
[0008]
On the other hand, there is a method of recording a sync block in which OWP is changed to a new value from the overwrite recording start track. Although this method can prevent a substantial decrease in recording capacity, when a sync block in which an OWP has changed during reproduction is acquired, a memory area different from the memory area in which the previously acquired sync block is written is used. It is necessary to avoid mixing of the base sync block and the overwrite sync block in the memory, for example, by writing to the area. Of course, it is not possible at this point to determine whether the change in OWP is due to the recording instantaneous clog or whether the overwriting has actually started, so it is necessary to secure a new memory area every time the OWP changes. Requires a lot of memory.
[0009]
The present applicant has proposed a device and a method that can prevent a decrease in recording capacity, do not require extra memory, do not consume parity for detecting an instantaneous clog, and can perform a majority decision of OWP satisfactorily. Is out. That is, in this improved method, the OWP exists one data at a time in the sync block where the C1 code is completed, takes the same value in a plurality of track units where the C2 code is completed, and takes the same value in a plurality of track units where the C2 code is completed. It is recorded under the condition that the value can be changed only in units. A predetermined number of OWPs sampled in units of a plurality of tracks are subjected to majority processing, and the majority is determined to be correct OWP. Whether the OWP of each sync block matches or is different from the correct OWP is detected.
[0010]
[Problems to be solved by the invention]
At this time, the OWP is different from the OWP obtained in the majority decision process because the OWP has changed due to the recording instantaneous clog, or an OWP data error or a random error has occurred during reading at the time of reading. There is an OWP sync block. When an error is mixed by the recording instantaneous clog, all data in the sync block where the error correction C1 code including the OWP is completed may be erroneous. On the other hand, if an error is mixed in when reading at the time of reproduction, there is a possibility that only the OWP is an error. Therefore, in order to completely correct the error, it is desirable to perform the correction process on the assumption that all the data of the sync block in which the C1 code including the OWP different from the correct OWP is completed is erroneous.
[0011]
Further, even if all errors can be corrected by the conventional error correction method, extra error correction processing is performed because the error correction end condition is determined by the state of the error flag.
[0012]
Therefore, it is an object of the present invention to correct a data error caused by a failure in normal recording at the time of recording based on the result of majority processing of identification data (OWP). An object of the present invention is to provide an information processing apparatus and method, a program, and a recording medium that can be shortened.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, according to the invention of claim 1, an inner code is encoded in a first direction of a two-dimensional array of recording data, and an outer code is encoded in a second direction. The sync data is added to the encoded data to form a sync block, the sync block configuration data is recorded on the recording medium, and the sync block includes identification data whose value is changed every recording. And, in the range in which the outer code is completed, digital data in which the identification data has the same value is reproduced, and in an information processing apparatus for correcting an error in the reproduced digital data,
Sync block detecting means for detecting a sync block;
First error position storage means for storing a position in the second direction of a sync block not detected by the sync block detection means;
First inner code decoding means for performing decoding processing of the inner code;
Second error position storage means for storing the position of the error in the second direction;
A memory in which an output of the first inner code decoding means is stored;
In the data stored in the memory, majority processing is performed on a predetermined number of identification data in a range where the outer code is completed, and the value of the identification data on the majority side is determined as the originally recorded identification data. Majority processing means for detecting coincidence between the identification data on the majority side and the identification data of each sync block included in the range where the interleaving is completed, and determining a mismatched sync block as an error sync block;
Third error position storage means for storing the position in the second direction of the error sync block detected by the majority processing means;
Outer code decoding means for performing an outer code decoding process using the data stored in the memory with reference to the error position stored in the first, second, and third error position storage means;
A second inner code decoding for performing an inner code decoding process using data that has been subjected to an outer code decoding process and stored in a memory, and changes the content of a second error position storage unit according to the decoding process. Means,
The outer code decoding means performs erasure correction when the total number of errors stored in the first, second, and third error position storage means is equal to or less than the number of parities of the outer code,
When the sum of the number of errors stored in the first, second and third error position storage means is larger than the number of parities of the outer code decoding means, the error is stored in the first and third error position storage means. If the total number of errors is equal to or less than the parity number of the outer code,
The information processing apparatus is configured not to perform correction when the total number of errors stored in the first and third error position storage units is larger than the number of parities of the outer code decoding unit.
[0014]
According to a fifth aspect of the present invention, in the outer code decoding step, when the total number of errors stored in the first, second, and third error position storage steps is equal to or less than the number of parities of the outer code, erasure correction is performed;
When the total number of errors stored in the first, second, and third error position storage steps is larger than the parity number in the outer code decoding step, the error number stored in the first and third error position storage steps is calculated. If the sum is less than or equal to the number of parities of the outer code, perform mixed correction,
This is an information processing method in which when the total number of errors stored in the first and third error position storing steps is larger than the number of parities in the outer code decoding step, no correction is performed.
[0015]
According to the present invention, when a sync error detection, a first inner code decoding process, an OWP error detection by majority decision process, and an outer code decoding process are sequentially performed, the outer code decoding process includes a sync error, an inner code error, With reference to the number of OWP errors, one of erasure correction processing, mixed correction processing, and no correction processing is selected. Thereby, an error can be corrected by effectively using a plurality of parities. In addition, since the decoding process is terminated when there are too many errors, the decoding process can be completed in a shorter time.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a recording / reproducing apparatus according to the present invention. The input data is data reproduced from a recording medium such as a magnetic tape and an optical disk. Alternatively, it is data received in a communication system. One embodiment is an example in which the present invention is applied to a rotary head type digital VTR that records data on a magnetic tape by a rotary head.
[0017]
FIG. 2 shows a data format of a sync block according to an embodiment of the present invention. One sync block length is 111 bytes, and a sync word consisting of 2 bytes indicating the sync head is located at the head of the sync block. Subsequently, one byte including the track number in which the sync block is recorded or the track pair number obtained by shifting the track number toward the LSB side by one bit is located. Further, data OWP (1 byte) for identifying that the data on the base of the magnetic tape has been reproduced is located. Thereafter, 96 bytes of main data including video data, audio data, auxiliary data, search data, or C2 parity are located. C1 parity (10 bytes) is added to 99 bytes from the byte including the track pair number to the main data.
[0018]
In one embodiment, a pair of magnetic recording heads having different azimuths are attached to the rotating drum at 180 ° facing intervals. It travels with a magnetic tape wound obliquely around the peripheral surface of the rotating drum. While the rotating drum makes a half turn, one head contacts the magnetic tape and records data as an oblique track. The data is, for example, MPEG (Moving Picture Experts Group) data. One frame of MPEG data is recorded as a predetermined number of tracks. The track pair number is added to every two tracks formed by a pair of magnetic recording heads.
[0019]
The above-mentioned sync blocks are continuously arranged and recorded in one track. In one track, for example, data of 141 sync blocks to which sync block numbers from 0 to 140 are assigned in the order in which the magnetic recording head scans on the tape is recorded. The 18 sync blocks with sync block numbers 0 to 17 have a C2 parity in the main data portion, and the main data portion of each sync block with a sync block number of 18 or later contains video data and the like. Is in.
[0020]
In one embodiment, a product code is used as the error correction code. FIG. 3 shows the configuration of the product code. C2 code such as Reed-Solomon code is encoded on 123 bytes aligned in the vertical direction (second direction) of the main data, and an 18-byte C2 parity is formed. Therefore, data for 123 + 18 = 141 sync blocks are arranged in the vertical direction. Next, a track interleave process described later is performed to read the main data (96 bytes) of each sync block or the track pair number, sync block number, OWP and main data (1 + 1 + 1 + 96 = 99 bytes) other than the sync word. The C1 code such as the Solomon code is encoded, and a 10-byte C1 parity is formed. Then, a sync word is added to form sync block data.
[0021]
Thus, C2 parity for 18 sync blocks is added to the main data portion for 123 sync blocks. When the arrangement of the 141 sync blocks is called a surface, as shown in FIG. 4, sync blocks for 16 surfaces are arranged in an interleaved manner over 16 tracks. This process is called track interleaving. In FIG. 4, the sync block number increases from top to bottom in the recording order (0 to 140), and the track number increases to (0 to 15) in the order of the tracks. In FIG. 4, one rectangular area represents a sync block, and surface numbers (0 to 15) are written in the area.
[0022]
At the time of reproduction, decoding processing of the C1 code is performed on each sync block reproduced from each track in real time. Then, the reproduction data for 16 tracks shown in FIG. 4 is stored in the memory, and sync blocks having the same surface number are collected to form one surface. For example, 141 sync blocks to which the surface number “0” is added are collected. A decoding process of the C2 code is performed for each configured surface. When a burst error represented by an instantaneous clog occurs due to track interleaving, a plurality of error sync blocks can be distributed on 16 planes on average. Thereby, the correction capability of the C2 code can be sufficiently exhibited.
[0023]
In one embodiment of the present invention, the OWP has the same value in 16 tracks where the track interleaving of the C2 code is completed, and the OWP value can be changed only in the 16 track period. The OWP uses a value different from the OWP identification data recorded before the splicing position as the OWP identification data after the splicing is started when the splicing is performed on the magnetic tape. In this embodiment, since the OWP is one byte, there are 256 possible values. The OWP is changed every time recording is performed in a splicing mode or the like. OWP changes are irregular.
[0024]
Returning to FIG. 1, the data read from the magnetic tape is input to the sync error detection unit 1. The sync error detection unit 1 generates a sync error flag when an input signal cannot be detected as a sync block. For example, if a sync word cannot be detected, a sync error is determined. The sync error flag is written to the sync error flag memory 7. In this case, a sync error flag having information on the position where the sync block should be recorded on the ECC memory 10 is generated. For example, a sync error flag is stored in a position of the sync error flag memory 7 corresponding to a position to be recorded. The input data that has passed through the sync error detection unit 1 is output to the C1 decoder 2.
[0025]
The C1 decoder 2 performs error correction of the C1 code for each sync block. Output data of the C1 decoder 2 is recorded in the ECC memory 10. After performing the normal correction process, the C1 decoder 2 stores the processed data in the ECC memory 10 as reproduced data, and stores a flag indicating a position that could not be corrected by the normal correction in the C1 error flag memory 6. . The C1 error flag has information on a position where the sync block is to be recorded on the ECC memory 10. For example, the C1 error flag is stored in the position of the C1 error flag memory 6 corresponding to the position to be recorded.
[0026]
The ECC memory 10 stores data input two-dimensionally in the horizontal direction (C1 direction) and the vertical direction (C2 direction) as shown in FIG. All the sync blocks for a plurality of tracks in which the combination of the C2 codes is completed are all recorded in the ECC memory 10. At this time, the reproduction data is vertically arranged on the ECC memory 10 in units of sync blocks, and is written line by line.
[0027]
FIG. 5 corresponds to FIG. 3. For example, a two-dimensional array of data excluding the sync word in FIG. 3 corresponds to the array in FIG. Therefore, data other than the sync word of one sync block is encoded by the product code. Since the reproduction data continuously arrives, the ECC memory 10 has two or more memory banks having a capacity capable of storing data for 16 surfaces on which track interleaving is completed.
[0028]
The C1 decoder 3, the C2 decoder 4, and the OWP majority processing unit 5 are connected so that the ECC memory 10 can be accessed. As described above, even if the same OWP value is recorded over 16 tracks, sync blocks previously recorded on the tape may be mixed due to errors occurring during reproduction or recording instantaneous clogs. It cannot be immediately determined whether or not a sync block contains the OWP value of. Therefore, the OWP majority decision processing unit 5 accumulates a certain number of sync blocks in the ECC memory 10, performs a majority decision of OWP in the accumulated sync blocks, and determines a large number of OWP values as correct OWP values.
[0029]
Then, the OWP of each sync block is compared again with the OWP determined to be correct. An OWP error flag is generated according to the result, and is stored in the OWP error flag memory 9. In other words, the OWP error flag corresponding to the recording position on the ECC memory 10 for the sync block belonging to the one with the smaller OWP is set to "error".
[0030]
The C2 decoder 4 performs normal correction based on the number of sync errors stored in the sync error flag memory 7, the number of OWP errors stored in the OWP error flag memory 9, and the number of C1 errors stored in the C1 error flag memory 6. , Erasure correction, or mixed correction, and performs C2 decoding. The C2 decoder 9 executes an error correction process included in each of the columns arranged in the vertical direction in the arrangement of the reproduction data stored in the ECC memory 10. The decoding result is stored in the ECC memory 10, and a flag indicating the position of the error that could not be corrected is stored in the C2 error flag memory 8.
[0031]
There are two types of error correction: normal correction and erasure correction. The normal correction is a process of correcting an error by obtaining an error position and an error value. Erasure correction is a process of correcting only the value of an error while the position of the error is known in advance. Further, the mixed correction is a process of performing correction by combining normal correction and erasure correction.
[0032]
For example, in the case of a Reed-Solomon code, when there are four parities, four syndromes S0, S1, S2, and S3 are obtained by calculating reproduced data. When there is no error, the values of all the syndromes become zero. In the case of one symbol error, the syndrome S0 is equal to the error value. In the case of a two-symbol error, the two errors can be corrected by determining the positions of two error symbols from the four syndromes and determining the values of the two errors. This is usually a correction. Furthermore, if the positions of up to four errors have been determined, the values of the errors at each position can be determined by calculating the four syndromes, and the errors can be corrected. This is erasure correction.
[0033]
As described above, when one erasure correction is performed, since the position of the error is known in advance, the parity is consumed by 1 in order to specify the value of the error. Further, when performing one normal correction, two parities are consumed in order to identify the position of the error and the value of the error. For example, when the number of parities t = 2, the number of symbols that can be corrected only by normal correction is 1 (t / 2 = 2/2). Further, when the number of parities t = 2, the number of symbols that can be corrected only by erasure correction is 2 symbols (= t). Furthermore, the condition under which the mixed correction is possible is that, when the number of parities t, the number of normal corrections i and the number of erasure corrections e are satisfied, the expression 2i + e ≦ t is satisfied.
[0034]
Similarly to the C1 decoder 2, the C1 decoder 3 is based on the flag stored in the sync error flag memory 7, the flag stored in the OWP error flag memory 9, and the number of flags stored in the C2 error flag memory 8. , An error correction process of the reproduction data stored in the ECC memory 10 is executed line by line. The data of the decoding result of the C1 decoder 3 is stored in the ECC memory 10 and the uncorrectable flag is stored in the C1 error flag memory 6. In one embodiment, the C1 decoding and the C2 decoding are each repeated twice at the maximum. That is, C1 decoding by the C1 decoder 2, C2 decoding by the C2 decoder 4, decoding by the C1 decoder 3, and decoding by the C2 decoder 4 are performed.
[0035]
Data read from the ECC memory 10 is supplied to the signal generator 11. The signal generation unit 11 reads out the error-corrected image data stored in the ECC memory 10, and reads the error information stored in the C1 error flag memory 6 and the error information stored in the C2 error flag memory 8. Output.
[0036]
As described above, four types of error flags, ie, a C1 error flag, a C2 error flag, a sync error flag, and an OWP error flag, are prepared. The error flags are all 1-bit. When the error is determined to be present, the flag is set (the value is “1”), and when it is determined that there is no error, the flag is not set. (Value is "0"). When all of these error flags are "0", a sync word is acquired, indicating that no error exists in the sync block.
[0037]
The C1 error flag is defined as a flag indicating that “a sync block has been acquired, but an error has occurred due to C1 decoding”. The C2 error flag is defined as a flag indicating that “an error has occurred due to C2 decoding”. The sync error flag is defined as a flag indicating that "since the sync block itself has not been acquired, there is a possibility that past data may remain in the memory". The OWP error flag is defined as a flag indicating that “a sync block has been acquired, but has become inconsistent by comparison with the OWP representative value”.
[0038]
Among the four types of flags, the sync block in which the sync error flag or the OWP error flag is set does not have a part of the sync block garbled as in the case of a random error. It is highly likely that the data is completely different. Therefore, it is desirable to treat such data as an erasure error when solving the C2 code. By informing the C2 decoder 4 of the position information of the error in advance as the erasure error, the error can be corrected without using extra parity.
[0039]
In the above-described error flags, errors may overlap, such as a sync error and an OWP error. If the number of error flags is counted individually and used as the number of error flags, the total number of error flags will be larger than the number of actual errors occurring. It happens to consume. Therefore, the following two methods can be considered as a method of obtaining the total number of each error flag.
[0040]
In the first method, a sync with a sync error flag set is treated as a sync error regardless of the state of the OWP error flag and the C1 error flag. Next, among the sinks for which the sync error flag is not set, the sinks for which the OWP error flag is set are treated as OWP errors regardless of the state of the C1 error flag. Finally, an error in which a sync error and an OWP error have not occurred but a C1 error has occurred is treated as a C1 error.
[0041]
In the second method, a sink in which a sync error has occurred is treated as a sync error regardless of the state of other error flags. Next, regarding the sink where no sync error has occurred, the sink where the C1 error flag is set is treated as a C1 error regardless of the state of the OWP error flag. Finally, a sync in which an OWP error has occurred but no sync error or C1 error has occurred is treated as an OWP error.
[0042]
The difference between the first and second methods described above is in the handling of the priority of the error flag. The priority order of the error flags in the first method is a sync error flag, an OWP error flag, and a C1 error flag in descending order of priority, whereas the second method is a sync error flag, a C1 error flag, It is an OWP error flag. The reason why the priority of the sync error flag is the highest is that all the data included in the sync for which the sync data could not be obtained cannot be trusted.
[0043]
There are two types of priorities, the OWP error flag and the C1 error flag, because some of the sync data could be recorded at the time of recording, but most of the data has the underlayer remaining, so the OWP data also has the underlayer. This depends on whether there is a large amount of sync data in which a C1 error has occurred as a result, or whether there is a lot of data in which an error has occurred at the time of reading the OWP data and a C1 error has occurred as a result. When the former error is large, the priority of the OWP error flag is higher than that of the C1 error flag, but when the latter error is large, the priority of the C1 error flag is higher than that of the OWP error flag.
[0044]
Which of these priorities is used depends on whether the number of errors occurring during recording or the number of errors occurring during reproduction is greater, and it depends on the system. Therefore, it is determined which priority is to be used by actually performing error correction or the like.
[0045]
FIG. 5 shows error flags stored in the C1 error flag memory 6, the sync error flag memory 7, the OWP error flag memory 9 and the C2 error flag memory 8, respectively, in relation to the ECC memory 10. The positional relationship between these error flag memories and the ECC memory 10 corresponds.
[0046]
In the ECC memory 10, input data is stored in a unit of a sync block, one row at a time in the vertical direction in FIG. At this time, if a read error such as a failure to detect a sync word in sync block units occurs, the sync error flag of the position where the sync block is stored (the position of the line in which all errors occur) is stored in the sync error flag memory 7. Set. In the example of FIG. 5, a sync error flag indicating that the sync block for one row at the position Y in the vertical direction could not be read is set.
[0047]
The C2 decoder 4 can specify an error position by referring to a sync error flag when performing error correction processing for each column of the ECC memory 10 in order from the leftmost column to the rightmost column as viewed in the drawing. The erasure correction of the error at the error position can be executed.
[0048]
Also, for a row for which an error could not be corrected after being decoded by the C1 decoders 2 and 3, a flag indicating the position of the row is similarly stored in the C1 error flag memory 6. Therefore, when an error that cannot be corrected occurs at the position of the Y-th row, the C1 error flag at that position is set in the C1 error flag memory 6 as having an error.
[0049]
After the majority of the OWP value is determined by the OWP majority processing unit, a row indicating an OWP value different from the value obtained by the majority decision is regarded as not correctly recorded when the sync block is recorded, and an OWP error is determined. The OWP error flag at that position is set in the flag memory 9 to indicate that there is an error.
[0050]
Furthermore, when the C2 decoder 4 decodes one column at a time in the vertical direction, a flag indicating the position of the column for which error correction was not possible is stored in the C2 error flag memory 8. For example, as shown in FIG. 5, when a C2 error has occurred at the position of column X among the C2 error flags stored in the C2 error flag memory 8, the C2 error flag at the position of X is determined to have an error. Set.
[0051]
Next, a decoding process of the error correction device will be described with reference to a flowchart of FIG.
[0052]
In step S1, the sync error detection unit 1 detects a sync error and stores the sync error in the sync error flag memory 7. In step S2, the C1 decoder 2 executes a first C1 decoding process. The correctable error is corrected, and a C1 error flag indicating the position of the uncorrectable error is stored in the C1 error flag memory 6.
[0053]
Here, the processing of the C1 decoder 2 (first C1 decoding) will be described with reference to the flowchart of FIG. In step S11, the C1 decoder 2 performs a normal correction process. In step S12, the C1 decoder 2 stores the C1 error flag indicating the position of the error data that could not be corrected in the C1 error flag memory 6.
[0054]
Here, returning to the description of the flowchart of FIG. 6, in step S3, the OWP majority decision processing unit 5 executes OWP majority decision processing.
[0055]
Here, the processing of the OWP majority decision processing unit 11 will be described with reference to the flowchart of FIG.
[0056]
In step S21, the OWP value recorded in each sync block is read from the ECC memory 10. If the OWP values of all the sync blocks are used, the processing becomes troublesome. Therefore, actually, the OWP values of a predetermined number of appropriately sampled sync blocks are read. The OWP majority decision process is performed using the read values.
[0057]
Next, a representative value of OWP for the error correction block is determined in step S22 based on the result of the majority decision performed in step S21. Next, in step S23, an OWP error flag is set for a sync block having an OWP value different from the representative OWP, and the error flag is stored in the OWP error flag memory 9.
[0058]
Here, returning to the description of the flowchart in FIG. 6, in step S4, the C2 decoder 4 executes a decoding process of the C2 code.
[0059]
Here, the decoding process of the C2 decoder 4 will be described with reference to the flowchart of FIG. The first decoding process and the second decoding process performed by the C2 decoder 4 are both performed in the order shown in the flowchart of FIG.
[0060]
In step S31, the sum of the number of errors recorded in the sync error flag memory 7, the number of errors recorded in the OWP error flag memory 9, and the number of errors recorded in the C1 error flag memory 6 is the parity number C2tmax for C2 decoding. It is determined whether or not: That is, step S31 is a process in which the C2 decoder 4 determines whether or not erasure correction is possible based on the total number of errors included in one column. If it is determined that erasure correction is possible, the process proceeds to step S32.
[0061]
In step S32, the C2 decoder 4 refers to the sync error flag memory 7, the OWP error flag memory 9, and the C1 error flag memory 8 to confirm the position where the error has occurred, and executes the erasure correction process. I do. In step S33, the C2 decoder 4 clears the error flag of the error corrected for each column and adds an error flag according to the correction result.
[0062]
In step S31, the sum of the number of errors recorded in the sync error flag 7, the number of errors recorded in the OWP error flag 9, and the number of errors recorded in the C1 error flag memory 6 is equal to or smaller than the parity number of the C2 decoder 4. If not, the process proceeds to step S34.
[0063]
In step S34, the C2 decoder 4 determines whether the sum of the number of sync errors and the number of OWP errors is equal to or less than the number of parity C2tmax. If it is determined that the parity number is equal to or smaller than C2tmax, the process proceeds to step S35.
[0064]
In step S35, the C2 decoder 4 performs a mixed correction process on the image data stored in the ECC memory 10 for each column. That is, correction is performed by combining normal correction and erasure correction. In step S36, the C2 decoder 4 detects an error for each column, detects an error position that could not be corrected, and sets an error flag in the C2 error flag memory 8.
[0065]
If it is determined in step S34 that the sum of the number of sync errors and the number of OWP errors is not less than the number of parities C2tmax, the C2 decoding process ends via step S37. In step S37, it is determined that the decoding process is not performed, and the fact that the decoding process is not performed is stored. That is, since there are too many errors that cannot be corrected, the C2 decoding process is not performed.
[0066]
Here, the description returns to the flowchart of FIG.
[0067]
In step S5, it is determined whether the C2 decoding process has not been performed in step S4 or whether all errors have been corrected. If all errors have been corrected, no further decoding processing is necessary, and the process proceeds to step S9. If the C2 decoding process is not performed due to too many errors, it is meaningless to perform the further process, and the process also proceeds to step S9. In step S9, the signal generation unit 11 reads out the decoded and corrected image data from the ECC memory 10, and also reads out the error flag information stored in the C1 error flag memory 6 and the C2 error flag memory 8 to obtain the image data. Add and output.
[0068]
If it is determined in step S5 that the C2 decoding process has been performed, but all errors have not been corrected, the process proceeds to step S6. In step S6, the C1 decoder 3 performs a decoding process.
[0069]
Here, the decoding process of the C1 decoder 3 (second C1 decoding process) will be described with reference to the flowchart of FIG.
[0070]
In step S41, the C1 decoder 3 determines whether the number of errors in the C2 error flag memory 8 is equal to or less than the number of parity C1tmax of the C1 decoder 3. If it is determined that the number of errors is equal to or smaller than the number of parity C1tmax of the C1 decoder 3, the process proceeds to step S42.
[0071]
In step S42, the C1 decoder 3 checks the error position with reference to the C2 error flag stored in the C2 error flag memory 8, and executes erasure correction. Then, in step S43, the C1 error flag at the corrected position in the C1 error flag memory 8 is cleared.
[0072]
If it is determined in step S41 that the total number of C2 error flags stored in the C2 error flag memory 8 is not less than or equal to the parity number C1tmax of the C1 code, the process proceeds to step S44.
[0073]
In step S44, the C1 decoder 3 refers to the error flags stored in the sync error flag memory 7, the OWP error flag memory 9, and the C1 error flag memory 6, and attaches a sync error flag or an OWP error flag. The correction processing is not performed on the row that has been changed, and the normal correction is performed on the other rows. The row in which the sync error flag or the OWP error flag is set is a part of the data in the C2 decoding in step S4 in FIG. Although the data is corrected to correct data, the C1 decoding process is performed for the purpose of preventing the data from being decoded into the base data again by performing the correction process using the parity added to the base data. Not performed. In step S45, the C1 decoder 3 records the processed error flag in the C1 error flag memory 6.
[0074]
The above-described embodiment of the present invention will be described more specifically. For example, assume that an ECC memory 10 stores 8 × 8 data (symbols) as shown in FIG. One piece of data (symbol) corresponds to one rectangular area (mesh) in the figure. One piece of data (symbol) is, for example, one byte. The reproduced sync blocks are recorded in the ECC memory 10 in order from top to bottom. In FIG. 11, a black rectangular area indicates error data, a white rectangular area indicates error-free data, and a hatched rectangular area indicates data having different OWPs. The same applies to the following description.
[0075]
A sync error flag memory 7 is shown on the right side of the ECC memory 10 represented by an 8 × 8 rectangular area, an OWP error flag memory 9 is shown on the right side, and a C1 error flag memory 6 is shown on the right side. In addition, a C2 error flag memory 8 is shown below the ECC memory 10.
[0076]
Further, the number of parities C1tmax of the C1 decoders 2 and 3 is set to 2, and the number of parities C2tmax of the C2 decoder 4 is set to 3. That is, the C1 decoders 2 and 3 have the ability to correct one error in the case of normal correction and the ability to correct two errors in the case of erasure correction. In addition, the C2 decoder 4 has a capability of correcting one error in the case of normal correction and a capability of correcting three errors in the case of erasure correction. Further, the C2 decoder 4 can normally correct one symbol and can perform erasure correction of one symbol in the mixed correction.
[0077]
When a sync word cannot be detected when sync data is input, the sync block detecting unit 1 detects a sync error and records a sync error flag indicating that an error has occurred. When a sync error occurs, it is considered that all data included in the sync data is erroneous. In the case of FIG. 11A, the second row from the top has an error in the data of one row. This is because when a sync word is not detected when this sync data is input, a sync error is detected and recorded in a position corresponding to the second row of the sync error flag memory 7, and the data in the second row is read. Indicates that all are errors. The input image signal is output to the C1 decoder 2 as a sync error flag indicating that this error has occurred.
[0078]
Next, the C1 decoder 2 executes a first decoding process (step S2). In step S11 in FIG. 7, the C1 decoder 2 performs a normal correction process. In the example of FIG. 11A, one error has occurred in each of the first, third, seventh, and eighth rows (the first row is the fourth column from the left, the third row is the third row). Is the sixth column from the left, the seventh row is the third column from the left, and the eighth row is the second column from the left). The C1 decoder 2 can execute the erasure correction processing up to the parity number C1tmax = 2, and can normally correct one error by the normal correction processing. Therefore, as shown in FIG. 11B, the errors in the first, third, seventh and eighth rows are corrected by the normal correction.
[0079]
However, as shown in FIG. 11A, four errors have occurred in the fifth row, and the C1 decoder 2 cannot correct the errors. As shown by, the four errors in the fifth row are left as they are. Although the fourth row has different OWP data, there is no error if only the sync block is viewed, so that at this stage, the error correction processing is not performed on this row.
[0080]
Since the error that could not be corrected in the process of step S11 is left in the fifth row, the C1 decoder 2 stores the error in the fifth row of the C1 error flag memory 6 as shown in FIG. An error flag is added to the eyes (step S12 in FIG. 7).
[0081]
Next, in step S3 in FIG. 6, the OWP majority decision processing unit 5 executes OWP majority decision processing (see the flowchart in FIG. 8).
[0082]
In the example of FIG. 11, since the OWP of the fourth row is different from the OWP of the other sync blocks, the error flag of the OWP error flag memory 9 of the fourth row is set as shown in FIG. I do.
[0083]
Next, the C2 decoder 4 executes a decoding process (step S4 in FIG. 6). The decoding process of the C2 decoder 4 is performed according to the flowchart of FIG. In the example of FIG. 11C, the sync error flag memory 7 has one error, the OWP error flag memory 9 has one error, and the C1 error flag memory 6 has one error. Therefore, the total is three. Since this is equal to or less than the parity number C2tmax = 3 of the C2 code, the process proceeds from step S31 to step S32 in FIG.
[0084]
In step S32, the C2 decoder 4 refers to the sync error flag memory 7, the OWP error flag memory 9, and the C1 error flag memory 8 to confirm the position where the error has occurred, and executes the erasure correction process. I do. That is, in the example of FIG. 11C, an error has occurred in the second line of the sync error flag memory 7, and an error has occurred in the fourth line of the OWP error flag memory 9. In the C1 error flag memory 6, since an error has occurred in the fifth row, the number of errors in each column is three in the first, fifth, seventh and eighth columns from the left, and Since there are two in the third, fourth, and sixth columns, erasure correction can be performed by the C2 decoder 4 for any column. As a result, all errors are corrected as shown in FIG. In this case, no C2 error flag is added.
[0085]
Then, in step S5 in FIG. 6, it is determined whether the C2 decoding process has not been performed in step S4 or whether all errors have been corrected. In the case of FIG. 11D, although the C2 decoding process has been performed, all errors have been corrected, so the process proceeds to step S9.
[0086]
In step S9, the signal generation unit 11 reads out the decoded image data from the ECC memory 10 and reads out and outputs the error information stored in the C1 error flag memory 6 and the C2 error flag memory 9.
[0087]
As described above, in the example of FIG. 11, all errors are corrected by performing only the erasure correction processing.
[0088]
Next, a correction process when image data as shown in FIG. 12A is input will be described.
[0089]
In step S1, the sync block detection unit 1 executes a sync error detection process, detects a sync error, and stores a sync error flag in the sync error flag memory 7. In the case of FIG. 12A, since no sync error exists, the input image signal is output to the C1 decoder 2 without adding a sync error flag.
[0090]
The first decoding process (see the flowchart in FIG. 7) of the C1 decoder is executed. That is, the C1 decoder 2 performs a normal correction process. In the example of FIG. 12A, one error has occurred in each of the first, third, sixth, and eighth rows. Since the C1 decoder 2 can correct an error up to the parity number C1tmax = 2 by the erasure correction process and can correct one error by the normal correction process, as shown in FIG. , The first, third, seventh and eighth rows will be corrected. However, as shown in FIG. 12A, the second, third, and fourth errors occur in the fourth, fifth, and seventh rows, respectively. As shown in FIG. 12B, the error cannot be corrected.
[0091]
The C1 decoder 2 adds a C1 error flag to a location corresponding to a row that could not be corrected in the process of step S11 (step S12). In the example of FIG. 12, as shown in FIG. 12B, an error flag is set in the fourth, fifth, and seventh rows of the C1 error flag memory 6.
[0092]
In step S3 in FIG. 6, the OWP majority decision processing unit 11 executes an OWP majority decision process. In the example of FIG. 12, since the OWP of the second row is different from the OWP of the other sync blocks, an error flag is added to the OWP error flag memory 9 of the second row as shown in FIG.
[0093]
Next, in step S4 of FIG. 6, the C2 decoder 4 executes a decoding process (see the flowchart of FIG. 9). The sum of the number of errors recorded in the sync error flag memory 7, the number of errors recorded in the OWP error flag 9, and the number of errors recorded in the C1 error flag memory 6 is equal to or less than the parity number C2tmax = 3 of the C2 decoder. It is determined whether or not there is.
[0094]
In the example of FIG. 12C, the sync error flags in the sync error flag memory 7 are all error-free, the OWP error flag memory 9 has one error, and the C1 error flag memory 6 has three errors. Since there are errors, the sum is four. Therefore, the number of parities of the C2 decoder is not smaller than C2tmax = 3, and the process proceeds to step S34.
[0095]
In step S34, the C2 decoder 4 determines whether or not the sum of the number of sync errors and the number of OWP errors is equal to or less than the number of parity C2tmax = 3. In the case of FIG. 12C, since the number of sync errors is 0 and the number of OWP errors is 1, the sum is 1 and it is determined that the number of parity is C2tmax = 3 or less, and the process proceeds to step S35. .
[0096]
In step S35, the C2 decoder 4 performs a mixed correction process for each column of the image data stored in the ECC memory 10. In the case of FIG. 12C, since the data in the second row from the top is an error whose position is determined by the OWP error flag memory 9, it can be corrected by erasure correction using one C2 parity.
[0097]
Further, in the second, seventh, and eighth columns from the left, the position of the error is not specified (the position of the error on the ECC memory 10 in the figure is shown for the sake of convenience; However, an error position cannot be detected at a position other than the position where the sync error flag is recorded.) Therefore, an error that exists in the seventh row from the top of the second column from the left, the seventh row from the top of the seventh column, and the fifth row from the top of the eighth column from the left indicates two C2 parities. It can be used and corrected by normal correction. In addition, since the first column and the fifth column from the left cannot perform error correction, data other than the first column and the fifth column are corrected as shown in FIG. Will be.
[0098]
The C2 decoder 4 performs a process of detecting an error for each column and adding an error flag. In the case of FIG. 12D, the C2 decoder 4 detects the error position in the first column from the left and the fifth column from the left since the error could not be corrected, and detects the error position. 8 is set.
[0099]
Next, it is determined whether the C2 decoding process has not been performed or whether all errors have been corrected (step S5). In the case of FIG. 12D, the C2 decoding process was performed, but all errors could not be corrected, so the process proceeds to the decoding process of the C1 decoder 3 (step S6).
[0100]
In step S41 in FIG. 10, the C1 decoder 3 determines whether or not the number of errors in the C2 error flag memory 8 is equal to or less than the number of parity C1tmax = 2 of the C1 decoder. In the case of FIG. 12 (D), since errors exist in the first and fifth columns in the C2 error flag memory 8, the number of errors in the C2 error flag memory 8 becomes 2 in total, and It is determined that the number of parities C1tmax = 2 or less, and the process proceeds to step S42.
[0101]
In step S42, the C1 decoder 3 refers to the C2 error flag memory 8 to confirm an error position, and performs erasure correction. In the case of FIG. 12 (D), the C2 error flag memory 8 has errors in the first and fifth columns from the left and the second, fourth, fifth and seventh rows from the top, respectively. As shown in FIG. 12E, the error is corrected by the erasure correction processing.
[0102]
In step S43, the C1 decoder 3 records the current error flag in the C1 error flag memory 6. In the case of FIG. 12 (E), since no error exists, no error is recorded in the C1 error flag memory 8 as shown in FIG. 12 (E).
[0103]
Then, in step S7 in FIG. 6, it is determined whether the C1 decoding process has not been performed in step S6 or whether all errors have been corrected. In the case of FIG. 12E, although the C1 decoding process has been performed, all errors have been corrected, so the process proceeds to step S9.
[0104]
In step S9, the signal generation unit 11 reads out the decoded image data from the ECC memory 10 and reads out and outputs the error information stored in the C1 error flag memory 6 and the C2 error flag memory 9.
[0105]
Thus, in the case of the example of FIG. 12, virtually all errors are corrected by performing the mixed correction processing.
[0106]
Next, a correction process when image data as shown in FIG. 13 is input will be described.
[0107]
In step S1, a sync error is detected, and a sync error flag is stored in the sync error flag memory 7. In the case of FIG. 13A, when data in the third, fourth, and seventh rows from the top is input, sync data cannot be detected. For this reason, the sync block detecting unit 1 detects a sync error, records a flag indicating that an error has occurred in the third, fourth, and seventh rows of the sync error flag memory, and outputs the input image data. To the C1 decoder 2.
[0108]
In step S2, the first decoding process (see the flowchart in FIG. 7) by the C1 decoder 2 is executed. In the case of FIG. 13A, one error has occurred in each of the first and eighth rows. The C1 decoder 2 can execute the erasure correction processing up to the parity number C1tmax = 2, and can correct one error in the normal correction processing. Therefore, as shown in FIG. 13B, the errors in the first and eighth rows are corrected. However, as shown in FIG. 13A, three errors have occurred in the fifth row, so that the C1 decoder 2 cannot correct the errors in the fifth row.
[0109]
In step S12, the C1 decoder 2 responds to the error in the fifth row that could not be corrected by the processing in step S11, as shown in FIG. Set the error flag on the fifth line.
[0110]
Next, in step S3, the OWP majority decision processing section 5 executes OWP majority decision processing. In FIG. 13, since the OWP of the second row is different from the OWP of the other sync blocks, the OWP error flag of the second row of the OWP error flag memory 9 is set as shown in FIG.
[0111]
Then, in step S4, the C2 decoder 4 executes a decoding process (see the flowchart of FIG. 9). In step S31, the sum of the number of errors recorded in the sync error flag 7, the number of errors recorded in the OWP error flag memory 9, and the number of errors recorded in the C1 error flag memory 6 is the parity number of the C2 decoder 4. It is determined whether or not C2tmax = 3 or less.
[0112]
In the example of FIG. 13C, the sync error flag memory 7 has three errors, the OWP error flag memory 9 has one error, and the C1 error flag memory 6 has one error. Since the sum is 5, the sum is 5, and in step S31, the number of parities of the C2 decoder is not equal to or less than C2tmax = 3, and the process proceeds to step S34.
[0113]
In step S34, the C2 decoder 4 determines whether or not the sum of the number of sync errors and the number of OWP errors is equal to or less than the number of parity C2tmax = 3. In the case of FIG. 13C, since the number of sync errors is 3 and the number of OWP errors is 1, the total is 4, and it is determined that the number of parities is not less than C2tmax = 3, and the process proceeds to step S37.
[0114]
In step S37, it is determined that the correction process is not performed, and the fact that the C2 decoding process is not performed is stored. In step S5 in FIG. 6, it is determined whether the C2 decoding process has not been performed in step S4 or whether all errors have been corrected. In the case of FIG. 13D, since the C2 decoding process has not been performed in step S4, the process proceeds to step S9.
[0115]
In step S9, the signal generating unit 11 reads out the decoded image data from the ECC memory 10, and reads out and outputs the error information stored in the C1 error flag memory 6 and the C2 error flag memory 8.
[0116]
As described above, in the case of the example of FIG. 13, since there are more errors than the number of correctable errors in the C1 decoder 2 and the C2 decoder 4, substantially no correction processing is performed. Will be output. After the first C1 decoding process and the OWP majority decision process, the decoding process is terminated because the first C2 decoding process is not performed. Can be prevented, and the decoding process can be performed quickly.
[0117]
Next, a correction process for data as shown in FIG. In step S1, a sync error detection process is executed, and a sync error flag corresponding to the detected sync error is stored in the sync error flag memory 7. In the example of FIG. 14A, since no sync error exists, recording is not performed on the sync error flag.
[0118]
In step S2, the decoding process of the C1 decoder (see the flowchart of FIG. 7) is performed. In step S11, the C1 decoder 2 performs a normal correction process. In the example of FIG. 14A, one error has occurred in each of the first, fourth, and eighth rows. The C1 decoder 2 can execute the erasure correction processing up to the parity number C1tmax = 2, and can correct one error in the normal correction processing. Therefore, as shown in FIG. 14B, the errors in the first, fourth, and eighth rows are corrected. However, as shown in FIG. 14A, four errors occur on the fifth line, and two errors occur on the sixth and seventh lines. Cannot be corrected.
[0119]
In step S12, the C1 decoder 2 has an error in the fifth, sixth, and seventh rows that could not be corrected by the processing in step S11, and therefore, as shown in FIG. The error flags in the fifth, sixth, and seventh rows of the flag memory 6 are set.
[0120]
Then, the OWP majority decision processing section 11 executes the OWP majority decision process (step S3). In step S21 in the flowchart of FIG. 8, the OWP value recorded in each sync block is read from the ECC memory 10. The OWP majority decision process is performed using the read values.
[0121]
Next, as a result of the majority decision performed in step S21, a representative value of OWP for the block is determined in step S22. Next, an OWP error flag is set for a sync block having an OWP value different from the representative value OWP selected in step S22. In FIG. 14, since the OWP of the second row is different from the OWP of the other sync blocks, the error flag of the second row of the OWP error flag memory 9 is set as shown in FIG.
[0122]
Next, the C2 decoder 4 executes a decoding process (Step S4 in FIG. 6). In step S31, the C2 decoder 4 determines whether the sum of the number of errors recorded in the sync error flag 7, the number of errors recorded in the OWP error flag 9, and the number of errors recorded in the C1 error flag memory 6 is C2 decoding. It is determined whether or not the parity number C2tmax of the device is 3 or less. In the example of FIG. 14 (C), there is no error in the sync error flag memory 7, one error flag is added to the OWP error flag memory 9, and three errors are stored in the C1 error flag memory 6. Since the flag is added, the total is four. Therefore, if the sum of the error flags is larger than C2tmax, it is determined in step S31, and the process proceeds to step S34.
[0123]
In step S34, the C2 decoder 4 determines whether or not the sum of the number of sync errors and the number of OWP errors is equal to or less than the number of parity C2tmax = 3. In the case of FIG. 14C, since the number of sync errors is 0 and the number of OWP errors is 1, the sum is 1, and it is determined that the number of parities is C2tmax = 3 or less. Proceed to S35.
[0124]
In step S35, the C2 decoder 4 refers to the sync error flag memory 7 and the OWP error flag memory 6 to check the position where the error has occurred, and executes the mixed correction processing. That is, in the case of FIG. 14C, since the data in the second row from the top is an error whose position is determined by the OWP error flag memory 9, it can be corrected by using one C2 parity by erasure correction. it can.
[0125]
Further, in the first, second, third, fourth and fifth columns from the left, the position of the error is not specified (the position of the error on the ECC memory 10 in the figure is shown for convenience). Actually, the error position cannot be detected except at the position where the sync error flag is recorded.) Therefore, the fifth row from the top of the fourth column from the left and the sixth row from the top of the fifth column from the left. Errors present in the eyes can be corrected by a normal correction process. Further, the first column, the second column, and the third column from the left cannot perform error correction. As a result, as shown in FIG. 14D, data other than the first column, the second column, and the third column are corrected.
[0126]
In step S36, the C2 decoder 4 executes a process of detecting an error for each column and adding an error flag. In the case of FIG. 14D, the first column, the second column, and the third column from the left of the C2 decoder 4 cannot correct the error. The flag is set.
[0127]
In step S5 in FIG. 6, it is determined whether the C2 decoding process has not been performed in step S4 or whether all errors have been corrected. In this case, although the C2 decoding process has been performed as shown in FIG. 14 (D), but all the errors could not be corrected, the process proceeds to step S6.
[0128]
In step S6, the C1 decoder 3 executes a second decoding process (see the flowchart in FIG. 10). In step S41, the C1 decoder 3 determines whether or not the number of errors in the C2 error flag memory 8 is equal to or less than the number of parity C1tmax = 2 of the C1 decoder. In the case of FIG. 14 (D), since errors exist in the first to third columns in the C2 error flag memory 8, the number of errors in the C2 error flag memory 8 becomes 3 in total, and the number of parity C1tmax of the C1 decoder. = 2 or less, and the process proceeds to step S44.
[0129]
In step S44, the C1 decoder 3 refers to the sync error flag memory 7, the OWP error flag memory 9 and the C1 error flag memory 6 to correct the row to which the sync error flag or the OWP error flag is added. Do not execute, but perform normal correction on the other lines. In the case of FIG. 14D, no error exists in the sync error flag memory 7, and the OWP error flag memory 9 has an OWP error flag in the second line from the top, so that the correction processing is executed. do not do. Also, since the C1 error flag memory 6 has three, one, and two errors in the fifth through seventh rows from the top, respectively, normal correction is performed. In this case, since the number of parities C1tmax of the C1 decoder 3 is equal to or greater than 2, only the sixth row can correct the correction processing. Therefore, as shown in FIG. An uncorrectable error remains in the seventh line.
[0130]
In step S45, the C1 decoder 3 records the current error flag in the C1 error flag memory 6. In the case of FIG. 14E, the error flags at the fifth and seventh rows from the top, which could not be corrected, remain without being cleared.
[0131]
Next, in step S7 of FIG. 6, it is determined whether the C1 decoding process has not been performed in step S6 or whether all errors have been corrected. In this case, the C1 decoding process is performed as shown in FIG. 14E, but all errors cannot be corrected, so the process proceeds to step S8.
[0132]
In step S8, the C2 decoder 4 performs a decoding process (see the flowchart in FIG. 9). In step S31, the sum of the number of errors recorded in the sync error flag 7, the number of errors recorded in the OWP error flag 9, and the number of errors recorded in the C1 error flag memory 6 is the parity number C2tmax of the C2 decoder 4. = 3 or less. In the case of FIG. 14 (E), there is no error in the sync error flag memory 7, there is one error in the OWP error flag memory 9, and there are two errors in the C1 error flag memory 6. Is 3, so in step S31, it is determined that the number of parities C2tmax is 3 or less, and the process proceeds to step S32.
[0133]
In step S32, the C2 decoder 4 refers to the sync error flag memory 7, the OWP error flag memory 9 and the C1 error flag memory 6, refers to the C2 error flag memory 8, and confirms the position where the error has occurred. Then, the erasure correction processing is performed. In the case of FIG. 14E, three, two, and three error flags are attached to the first to third columns from the left, respectively, and as shown in FIG. Is corrected by the erasure correction processing.
[0134]
In step S33, the C2 decoder 4 executes a process of detecting an error for each column and adding an error flag. However, in the case of FIG. 14 (F), since all the errors have been corrected, the flag added to the C2 error flag memory 8 is deleted, and the processing ends.
[0135]
In step S9 in FIG. 6, the signal generation unit 11 reads out the decoded image data from the ECC memory 10, and reads out and outputs the error information stored in the C1 error flag memory 6 and the C2 error flag memory 8. .
[0136]
As described above, in the case of the example in FIG. 14, the normal correction processing is performed in the first decoding processing of the C1 decoder 2, the mixed correction is performed in the first decoding processing of the C2 decoder 4, and the second correction processing is performed. In the decoding process of the C1 decoder 3, the normal correction is performed, and in the second decoding process of the C2 decoder 4, the erasure correction is performed, and as a result, all errors are corrected.
[0137]
As described above, the decoding process is executed in the order of the C1 decoder 2, the C2 decoder 4, the C1 decoder 3, and the C2 decoder 4, and the sync error flag memory 7, the OWP error flag memory 9, the C1 error flag memory 6 and the error flag added to the C2 error flag memory 8, the decoding process is executed by using the normal correction, the erasure correction and the mixed correction properly.
[0138]
The present invention is not limited to the embodiment of the present invention described above, and various modifications and applications are possible without departing from the gist of the present invention. For example, in the above description, an example in which the ECC memory 10 has an 8 × 8 data configuration has been described. However, it is needless to say that the ECC memory 10 is a memory that can handle two-dimensional data having other numbers of configurations. You may. Further, the steps of describing the program recorded on the recording medium may be performed in parallel or individually, even if not necessarily performed in chronological order in the described order. This includes the following processing.
[0139]
The decryption processing according to the present invention can be realized by either hardware or software. When the decoding process is realized by software, an information processing apparatus can be realized by installing a program for the decoding process (see FIG. 6) on a computer.
[0140]
The present invention is not limited to the embodiment of the present invention described above, and various modifications and applications are possible without departing from the gist of the present invention. For example, the present invention can be applied to a case where digital data is recorded and reproduced using a recording medium other than a magnetic tape, for example, an optical disk. The present invention is also applicable to a case where digital data is communicated via a transmission medium.
[0141]
【The invention's effect】
According to the present invention, an error is corrected by any one of the erasure correction, the normal correction, and the mixed correction by using the identification data (OWP) for an error generated at the time of recording or generation of transmission data. be able to. According to the present invention, it is possible to increase the number of errors that can be corrected. Further, according to the present invention, it is detected that all errors have been corrected or that there are too many errors and decoding processing has not been performed, and as a result, error correction is completed, thereby shortening the error correction processing time. can do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating a data configuration of a sync block according to an embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating a data configuration within a track according to an embodiment of the present invention.
FIG. 4 is a schematic diagram illustrating an example of an inter-track interleave pattern using 16 error-correcting outer codes.
FIG. 5 is a schematic diagram illustrating a configuration of an ECC memory according to an embodiment of the present invention.
FIG. 6 is a flowchart showing an overall flow of a decoding process according to an embodiment of the present invention.
FIG. 7 is a flowchart illustrating a flow of a first C1 decoding process during the decoding process.
FIG. 8 is a flowchart showing the flow of OWP majority decision processing during decoding processing.
FIG. 9 is a flowchart illustrating a flow of a C2 decoding process during the decoding process.
FIG. 10 is a flowchart showing a flow of a second C1 decoding process during the decoding process.
FIG. 11 is a schematic diagram illustrating a first example of a decoding process according to an embodiment of the present invention;
FIG. 12 is a schematic diagram illustrating a second example of a decoding process according to an embodiment of the present invention.
FIG. 13 is a schematic diagram illustrating a third example of the decoding process according to the embodiment of the present invention;
FIG. 14 is a schematic diagram illustrating a fourth example of the decoding process according to the embodiment of the present invention;
[Explanation of symbols]
Reference Signs List 1 ... Sync error detection unit, 2, 3 ... C1 decoder, 4 ... C2 decoder, 5 ... OWP majority processing unit, 6 ... C1 error flag memory, 7 ... Sync Error flag memory, 8 ... C2 error flag memory, 9 ... OWP error flag memory, 10 ... ECC memory, 11 ... Signal generation unit

Claims (10)

An inner code is encoded in a first direction of a two-dimensional array of recording data, an outer code is encoded in a second direction, and sync data is added to the encoded data. A sync block is configured, data of the sync block configuration is recorded on the recording medium, and the sync block includes identification data whose value is changed every recording, and the identification data is the same in a range where the outer code is completed. Digital data reproduced so as to have a value of, and an information processing apparatus for correcting an error of the reproduced digital data,
Sync block detecting means for detecting the sync block,
First error position storage means for storing a position in a second direction of a sync block not detected by the sync block detection means;
First inner code decoding means for performing the decoding process of the inner code,
Second error position storage means for storing the position of the error in the second direction;
A memory in which an output of the first inner code decoding means is stored;
In the data stored in the memory, a majority process is performed on a predetermined number of the identification data within a range in which the outer code is completed, and the value of the identification data on the majority side is originally stored in the identification data. Majority processing means for detecting coincidence between the identification data on the majority side and the identification data of each sync block included in the range where the interleaving is completed, and determining a mismatched sync block as an error sync block. When,
Third error position storage means for storing a position in the second direction of the error sync block detected by the majority processing means;
Outer code decoding means for performing an outer code decoding process using the data stored in the memory with reference to the error position stored in the first, second and third error position storage means;
A decoding process of the inner code is performed using the data stored in the memory after the decoding process of the outer code is performed, and the content of the second error position storage unit is changed according to the decoding process. And inner code decoding means,
The outer code decoding means performs erasure correction when the total number of errors stored in the first, second, and third error position storage means is equal to or less than the number of parities of the outer code,
When the total number of errors stored in the first, second and third error position storage means is larger than the parity number of the outer code decoding means, the first and third error position storage means If the total number of stored errors is equal to or less than the number of parities of the outer code, perform mixed correction,
An information processing apparatus wherein, when the total number of errors stored in the first and third error position storage means is larger than the number of parities of the outer code decoding means, no correction is performed. In claim 1,
Storing that the outer code decoding means did not perform the decoding process,
Information that terminates the decoding process without performing the decoding process of the second inner code decoding unit when the outer code decoding unit does not perform the decoding process or when all errors are corrected. Processing equipment. In claim 1,
Further, an information processing apparatus wherein the data after the decoding processing by the second inner code decoding means is decoded again by the outer code decoding means. In claim 3,
Storing that the second inner code decoding means did not perform the decoding process;
Information that terminates the decoding process without performing the decoding process of the outer code decoding unit when the second inner code decoding unit does not perform the decoding process or when all errors are corrected. Processing equipment. An inner code is encoded in a first direction of a two-dimensional array of recording data, an outer code is encoded in a second direction, and sync data is added to the encoded data. A sync block is configured, data of the sync block configuration is recorded on the recording medium, and the sync block includes identification data whose value is changed every recording, and the identification data is the same in a range where the outer code is completed. In the information processing method of reproducing digital data having a value of
A sync block detecting step of detecting the sync block;
A first error position storing step of storing a position in a second direction of a sync block not detected by the sync block detecting step;
A first inner code decoding step of performing the inner code decoding process;
A second error position storing step of storing the position of the error in the second direction;
The output of the first inner code decoding step is stored, and a majority process is performed on a predetermined number of the identification data within a range where the outer code is completed in the stored data. Is determined as the originally recorded identification data, the identification data of the majority side and the identification data of each sync block included in the range where the interleaving is completed are detected, and the mismatched sync is detected. A majority processing step of determining the block as an error sync block;
A third error position storing step of storing the position of the error sync block detected in the majority processing step in the second direction;
An outer code decoding step of performing an outer code decoding process using the stored data with reference to the error positions stored in the first, second and third error position storage steps;
A second inner code for performing a decoding process for the outer code and performing a decoding process for the inner code using the stored data, and changing the content of the second error position storage step according to the decoding process. Decoding step,
In the outer code decoding step, erasure correction is performed when the total number of errors stored in the first, second, and third error position storage steps is equal to or less than the parity number of the outer code.
When the total number of errors stored in the first, second, and third error position storage steps is larger than the number of parities in the outer code decoding step, the error number is stored in the first and third error position storage steps. If the total number of errors is equal to or less than the parity number of the outer code, perform mixed correction,
An information processing method in which when the total number of errors stored in the first and third error position storing steps is larger than the number of parities in the outer code decoding step, no correction is performed. In claim 5,
It stores that the process of the outer code decoding step was not performed,
When the processing of the outer code decoding step is not performed or when all errors are corrected, the decoding processing is terminated without performing the decoding processing of the second inner code decoding step. Method. In claim 5,
Further, an information processing method wherein the data after the decoding process in the second inner code decoding step is decoded again in the outer code decoding step. In claim 7,
Storing that the second inner code decoding step did not perform correction;
When the second inner code decoding step does not perform correction or when all errors are corrected, the information processing apparatus terminates the decoding processing without performing the decoding processing in the outer code decoding step. Method. An inner code is encoded in a first direction of a two-dimensional array of recording data, an outer code is encoded in a second direction, and sync data is added to the encoded data. A sync block is configured, data of the sync block configuration is recorded on the recording medium, and the sync block includes identification data whose value is changed every recording, and the identification data is the same in a range where the outer code is completed. Digital data reproduced so as to have a value of, and a program for causing a computer to execute a process of correcting an error of the reproduced digital data,
A sync block detecting step of detecting the sync block;
A first error position storing step of storing a position in a second direction of a sync block not detected by the sync block detecting step;
A first inner code decoding step of performing the inner code decoding process;
A second error position storing step of storing the position of the error in the second direction;
The output of the first inner code decoding step is stored, and a majority process is performed on a predetermined number of the identification data within a range where the outer code is completed in the stored data. Is determined as the originally recorded identification data, the identification data of the majority side and the identification data of each sync block included in the range where the interleaving is completed are detected, and the mismatched sync is detected. A majority processing step of determining the block as an error sync block;
A third error position storing step of storing the position of the error sync block detected in the majority processing step in the second direction;
An outer code decoding step of performing an outer code decoding process using the stored data with reference to the error positions stored in the first, second and third error position storage steps;
A second inner code for performing a decoding process for the outer code and performing a decoding process for the inner code using the stored data, and changing the content of the second error position storage step according to the decoding process. Decoding step,
In the outer code decoding step, erasure correction is performed when the total number of errors stored in the first, second, and third error position storage steps is equal to or less than the parity number of the outer code.
When the total number of errors stored in the first, second, and third error position storage steps is larger than the number of parities in the outer code decoding step, the error number is stored in the first and third error position storage steps. If the total number of errors is equal to or less than the parity number of the outer code, perform mixed correction,
A program for performing no correction when the total number of errors stored in the first and third error position storage steps is larger than the number of parities in the outer code decoding step. An inner code is encoded in a first direction of a two-dimensional array of recording data, an outer code is encoded in a second direction, and sync data is added to the encoded data. A sync block is configured, data of the sync block configuration is recorded on the recording medium, and the sync block includes identification data whose value is changed every recording, and the identification data is the same in a range where the outer code is completed. Digital data made to have the value of is reproduced, in a computer-readable recording medium recording a program for causing a computer to execute a process of correcting an error in the reproduced digital data,
A sync block detecting step of detecting the sync block;
A first error position storing step of storing a position in a second direction of a sync block not detected by the sync block detecting step;
A first inner code decoding step of performing the inner code decoding process;
A second error position storing step of storing the position of the error in the second direction;
The output of the first inner code decoding step is stored, and a majority process is performed on a predetermined number of the identification data within a range where the outer code is completed in the stored data. Is determined as the originally recorded identification data, the identification data of the majority side and the identification data of each sync block included in the range where the interleaving is completed are detected, and the mismatched sync is detected. A majority processing step of determining the block as an error sync block;
A third error position storing step of storing the position of the error sync block detected in the majority processing step in the second direction;
An outer code decoding step of performing an outer code decoding process using the stored data with reference to the error positions stored in the first, second and third error position storage steps;
A second inner code for performing a decoding process for the outer code and performing a decoding process for the inner code using the stored data, and changing the content of the second error position storage step according to the decoding process. Decoding step,
In the outer code decoding step, erasure correction is performed when the total number of errors stored in the first, second, and third error position storage steps is equal to or less than the parity number of the outer code.
When the total number of errors stored in the first, second, and third error position storage steps is larger than the number of parities in the outer code decoding step, the error number is stored in the first and third error position storage steps. If the total number of errors is equal to or less than the parity number of the outer code, perform mixed correction,
When the total number of errors stored in the first and third error position storage steps is larger than the parity number in the outer code decoding step, a computer-readable recording in which a program for preventing correction is recorded. Medium.

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