JP2004070224A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which is further miniaturized even when it has a plurality of display panels. <P>SOLUTION: The display device is equipped with a main panel 2 formed on a glass substrate 1, a sub panel 3 formed on the same glass substrate 1 in an area other than the area where the main panel 2 is formed, a V shift register 4 and an H shift register 6 shared by the main panel 2 and the sub panel 3. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device, and more particularly, to a display device including a plurality of display panels.
[0002]
[Prior art]
Conventionally, a portable display device used as a display panel of a mobile phone or the like has been known. In addition, a foldable mobile phone including two display panels, a main panel and a sub panel, is conventionally known.
[0003]
5 and 6 are perspective views showing a conventional foldable mobile phone including two liquid crystal display panels, a main panel and a sub panel. With reference to FIGS. 5 and 6, a conventional foldable mobile phone 100 includes a display unit 100a and an operation unit 100b. The display unit 100a includes a main panel 101 provided on a surface on the operation unit 100b side, and a sub panel 102 provided on a surface opposite to the operation unit 100b. When not in use, as shown in FIG. 5, the display unit 100a is folded with respect to the operation unit 100b. In this folded state, sub-panel 102 displays time information and the like. In use, the display unit 100a is opened from the state shown in FIG. 5 in the direction of the arrow in FIG. 5 to be in the state shown in FIG. In this state, the main panel 101 displays a telephone number, a moving image, and the like.
[0004]
In the above-described conventional mobile phone 100 including the main panel 101 and the sub panel 102, since the main panel 101 and the sub panel 102 are separately mounted, there is a disadvantage that the housing of the mobile phone 100 becomes large. For this reason, it has been difficult to reduce the size of the mobile phone 100.
[0005]
Therefore, conventionally, in a portable device such as a mobile phone including a main panel and a sub panel, a main panel and a sub panel are arranged above and below the backlight, respectively, so that the main panel and the sub panel share the backlight. Has been proposed. Thus, the size of the housing can be reduced by the share of the backlight.
[0006]
[Problems to be solved by the invention]
Here, in a liquid crystal display device used for a mobile device such as the mobile phone 100, particularly, there is a strong demand for miniaturization, so that further miniaturization is required. However, in the above-described technology for sharing the backlight, the main panel and the sub panel are mounted separately, and thus there is a limit to downsizing. As a result, there is a problem that it is difficult to further reduce the size of the backlight by using the technology for sharing the backlight.
[0007]
Further, in the technique of sharing the backlight, since the panels of the main panel and the sub-panel are separately mounted, it is difficult to further reduce the number of components and to further simplify the assembling process. As a result, there is a problem that it is difficult to further reduce the apparatus cost.
[0008]
The present invention has been made to solve the above problems,
One object of the present invention is to provide a display device that can be further reduced in size when including a plurality of display panels.
[0009]
Another object of the present invention is to further reduce the number of components and further simplify the assembling process in the above display device.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a display device according to one aspect of the present invention includes a first display panel formed on a substrate, and a region on the same substrate as the substrate and on which the first display panel is formed. A second display panel formed in a different area from the first display panel, and a shift register shared by the first display panel and the second display panel.
[0011]
In the display device according to this aspect, as described above, the first display panel and the second display panel are formed in different regions on the same substrate, and the shift register is shared by the first display panel and the second display panel. Accordingly, the size can be further reduced as compared with the case where the first display panel and the second display panel are formed on different substrates. Further, by sharing the substrate and the shift register between the first display panel and the second display panel, the number of components can be further reduced, and the assembling process can be further simplified. Thereby, the apparatus cost can be further reduced.
[0012]
In the display device according to the above aspect, preferably, the shift register shared by the first display panel and the second display panel drives the gate line of the first display panel and the gate line of the second display panel. And a second shift register for driving a drain line of the first display panel and a drain line of the second display panel. With this configuration, the gate line of the first display panel and the gate line of the second display panel can be easily driven by one first shift register, and the first display is performed by one second shift register. The drain line of the panel and the drain line of the second display panel can be driven.
[0013]
In this case, preferably, the first display panel and the second display panel are arranged along the direction in which the drain lines extend. According to this structure, the drain line can be easily shared between the first display panel and the second display panel.
[0014]
Further, in this case, the first shift register is not arranged in a portion corresponding to the second display panel, but is arranged in a portion of the first shift register corresponding to the first display panel, and is connected to a gate line of the first display panel. A level shifter for converting a voltage level of a signal to be provided is further provided. According to this structure, for example, when a negative voltage needs to be applied only to the gate line of the first display panel, such as in the case where only the first display panel is driven by the counter electrode AC, the level shifter can be easily used. The level-converted negative voltage can be applied to the gate line of the first display panel. Further, by providing the level shifter only in a portion corresponding to the first display panel, power consumption can be reduced.
[0015]
In the above case, preferably, an output stop circuit for stopping output of any one of a portion corresponding to the first display panel and a portion corresponding to the second display panel of the first shift register is further provided. With this configuration, even when the first shift register is shared by the first display panel and the second display panel, only the first display panel or the second display panel can be easily displayed. In addition, if the output from the output stop circuit is output only once in a plurality of scans, for example, a first display panel for displaying a moving image or the like that requires a large number of data rewriting times and a moving image or the like are displayed. When the first shift register is shared with the second display panel, which does not require a large number of data rewrites, the output stop circuit can extend only the rewrite cycle of the second display panel. Thus, it is possible to reduce only the number of times of data rewriting of the second display panel while keeping the number of times of data rewriting of the first display panel large.
[0016]
In the above case, preferably, one of the gate line and the drain line is shared by the first display panel and the second display panel. According to this structure, the number of one of the gate line and the drain line can be reduced, so that the power consumption can be reduced and the frame can be narrowed.
[0017]
In this case, preferably, the first display panel and the second display panel are arranged along the direction in which the drain lines extend, and the drain lines are continuous from the first display panel to the second display panel. With this configuration, the number of drain lines can be easily reduced.
[0018]
Further, when the first display panel and the second display panel are arranged along the direction in which the drain lines extend, the second shift register that drives the drain lines includes the first display panel, the second display panel, May be arranged between them. According to this structure, compared with the case where the second shift register is arranged at one end of the first display panel or the second display panel, the distance from the second shift register to the first display panel or the second display panel is reduced. Since the distance is shortened, the load on the drain line can be reduced.
[0019]
A display device according to another aspect of the present invention includes a first display panel formed on a substrate and a first display panel formed on the same substrate as the substrate and in a region different from a region where the first display panel is formed. A second display panel, and a drain line and a gate line disposed so as to intersect each other. One of the drain line and the gate line is continuous from the first display panel to the second display panel.
[0020]
In the display device according to this other aspect, as described above, one of the drain line and the gate line is formed so as to be continuous from the first display panel to the second display panel, so that the gate line or the drain line is formed. Since the number of either one can be reduced, the power consumption can be reduced and the frame can be narrowed.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
(1st Embodiment)
FIG. 1 is a plan view showing a liquid crystal display device for a mobile phone including two display panels, a sub panel and a main panel, according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an internal configuration around the V shift register of the liquid crystal display device according to the first embodiment shown in FIG.
[0023]
First, referring to FIG. 1, in the first embodiment, a main panel 2 and a sub panel 3 are formed in different regions on the same glass substrate 1. The main panel 2 and the sub-panel 3 are arranged along the direction in which the drain lines extend. The main panel 2 is of a transmissive type or a transflective type, and the sub panel 3 is of a reflective type. As a result, a double-sided display type liquid crystal display device capable of displaying the main panel 2 and the sub-panel 3 on opposite surfaces is obtained. The glass substrate 1 is an example of the “substrate” of the present invention. The main panel 2 is an example of the “first display panel” of the present invention, and the sub panel 3 is an example of the “second display panel” of the present invention.
[0024]
On the side of the main panel 2 opposite to the side on which the sub panel 3 is disposed, an H shift register 6 for driving (scanning) the drain lines is disposed. A drain line switch 7 is arranged between the H shift register 6 and the main panel 2. The drain line switch 7 is provided for sequentially supplying the video signal to each drain line by sequentially turning on the switches in accordance with the sampling signal. Further, a V shift register 4 for driving (scanning) the gate lines of the main panel 2 and the sub panel 3 is arranged in a direction orthogonal to the direction in which the gate lines of the main panel 2 and the sub panel 3 extend. ing. Further, between the V shift register 4 and the main panel 2, a V level shifter 5 for converting a level of a negative voltage of a signal applied to a gate line of the main panel 2 is arranged. The V shift register 4 is an example of the “first shift register” of the present invention, and the H shift register 6 is an example of the “second shift register” of the present invention. The V level shifter 5 is an example of the “level shifter” of the present invention.
[0025]
Here, in the first embodiment, the V shift register 4 is shared by the main panel 2 and the sub panel 3, and the H shift register 6 is shared by the main panel 2 and the sub panel 3. Further, the drain line is shared by the main panel 2 and the sub panel 3. That is, the drain line extends from the H shift register 6 to the sub panel 3 through the main panel 2.
[0026]
Further, an external IC 10 is provided separately from the glass substrate 1 constituting the liquid crystal display panel. The external IC 10 includes a power supply circuit 11 and an ENB signal control circuit 12. The power supply circuit 11 has a positive voltage V _DD And a negative voltage V _BB And a circuit for generating Thereby, the positive voltage V is applied from the external IC 10 to the V shift register 4 and the H shift register 6. _DD Is supplied to the V level shifter 5 and the negative voltage V _BB Is supplied. The V shift register 4 is supplied with a vertical clock signal VCLK, a start signal VST, and an ENB signal from the external IC 10. The H shift register 6 is supplied with a horizontal clock signal HCLK and a start signal HST from the external IC 10.
[0027]
Next, an internal configuration of the V shift register 4 of the liquid crystal display device according to the first embodiment will be described with reference to FIG. V shift register 4 includes shift registers 4a, 4b, 4c, 4d and 4e. Further, the V shift register 4 includes AND1, AND2, AND3, and AND4, which are formed by AND circuits having three input terminals and one output terminal. The outputs of the shift registers 4a and 4b and the ENB signal are input to the input terminal of AND1. The outputs of the shift registers 4b and 4c and the ENB signal are input to the input terminal of AND2. The output terminals of the shift registers 4c and 4d and the ENB signal are input to the input terminal of the AND3. The outputs of the shift registers 4d and 4e and the ENB signal are input to the input terminal of the AND4.
[0028]
In AND1, AND2, AND3, and AND4, an H level is output only when all three inputs are at an H level, and an L level is output when at least one of the three inputs has an L level. .
[0029]
The output terminals of AND1 and AND2 are connected to gate lines G1 and G2, respectively. The output terminals of AND3 and AND4 are connected to gate lines G3 and G4 via level shifters 5a and 5b of V level shifter 5, respectively.
[0030]
Here, AND1 and AND2 constitute an output stop circuit 41 for stopping output to the sub-panel 3. AND3 and AND4 constitute an output stop circuit 42 for stopping output to the main panel 2.
[0031]
Each pixel of the main panel 2 includes a switching transistor 21, a liquid crystal 22, and an auxiliary capacitor 23. The gate of the switching transistor 21 is connected to the gate line G3 or G4, and the drain of the switching transistor 21 is connected to the drain line D1. The display electrode of the liquid crystal 22 is connected to the source of the switching transistor 21. Further, one electrode of the auxiliary capacitance 23 is connected to the source of the switching transistor 21. Each pixel of the sub panel 3 includes a switching transistor 31, a liquid crystal 32, and an auxiliary capacitor 33. The gate of the switching transistor 31 is connected to the gate line G1 or G2, and the drain of the switching transistor 31 is connected to the drain line D1. The display electrode of the liquid crystal 32 is connected to the source of the switching transistor 31. The source of the switching transistor 31 is connected to one electrode of the auxiliary capacitance 33. The auxiliary capacitor 33 has a larger capacity than the auxiliary capacitor 23 of the main panel 2 in order to hold the data of the sub-panel 3 with a small number of rewrites for a certain period.
[0032]
The main panel 2 is driven by the counter electrode AC drive, and the sub panel 3 is driven by the counter electrode DC drive. Here, the counter-electrode AC drive is a drive for reducing the amplitude of the video signal to approximately half by alternating-current driving another electrode (counter electrode: COM) different from one electrode (display electrode) of the display pixel to which the video signal is applied. Refers to the method. When the counter electrode AC driving is used, the potential of the pixel electrode may be negative depending on the potential of the counter electrode (COM) and the potential of the video signal. In this case, when the gate potential of the switching transistor 21 is a positive potential or 0, the switching transistor 21 is turned on. Therefore, it is necessary to apply a negative voltage to the gate lines G3 and G4 of the main panel 2. Therefore, in order to perform the counter-electrode AC driving, it is necessary to supply the negative voltage whose level has been converted by the V level shifter 5 to the gate lines G3 and G4 of the main panel 2.
[0033]
On the other hand, the counter electrode DC drive is a driving method in which the counter electrode (COM) is set to a constant voltage, so that the potential of the video signal does not become negative. Therefore, it is not necessary to supply a negative voltage to the gate lines G1 and G2 of the sub-panel 3 that performs the counter electrode DC drive. For this reason, in the first embodiment, the V level shifter 5 is arranged only in a portion of the main panel 2 corresponding to the gate lines G3 and G4, and is arranged in a portion of the sub panel 3 corresponding to the gate lines G1 and G2. Not.
[0034]
FIG. 3 is a timing chart for explaining a method of driving the V shift register of the liquid crystal display device according to the first embodiment shown in FIG. Next, a method of driving the V shift register 4 of the liquid crystal display device according to the first embodiment will be described with reference to FIGS.
[0035]
First, driving of the V shift register 4 is started by a start signal VST (see FIG. 2). Then, the shift registers 4a to 4e (SR1 to SR5) of the V shift register 4 sequentially go to the H level for a certain period in synchronization with the vertical clock signal VCLK as shown in FIG. In this case, during the first scan, H-level ENB signals (ENB1 and ENB2) are supplied to AND1 and AND2 corresponding to sub-panel 3, and H-level ENB signals are also supplied to AND3 and AND4 corresponding to main panel 2. (ENB3 and ENB4). The control of the ENB signal is performed by the ENB signal control circuit 12 built in the external IC 10 shown in FIG. As a result, as shown in FIG. 3, at the time of the first scan, the outputs of AND1, AND2, AND3, and AND4 are each at the H level for a certain period. Thus, in the first scan, all of the gate lines G1, G2, G3, and G4 are each at the H level for a certain period.
[0036]
Note that the ENB signal is conventionally used to prevent a pixel transistor (switching transistor) from turning on during a precharge period. The precharging of the drain line is performed in order to raise the drain line to a certain voltage in advance, and to make a state where only a slight addition of the video signal is required. In the first embodiment, the ENB signal is used as a control signal for changing a rewrite cycle between the main panel 2 and the sub panel 3 and a control signal for stopping the sub panel 3 or the main panel 2.
[0037]
As described above, at the time of the first scanning of the sub-panel 3 and the main panel 2, the switching transistors 31 of the sub-panel 3 are turned on by setting the gate lines G1 and G2 corresponding to the sub-panel 3 to the H level. Thereby, the video signal supplied to the drain line D1 is supplied to the display electrode of the liquid crystal 32 and the auxiliary capacitance 33 via the switching transistor 31. As a result, the display of the corresponding pixel of the sub panel 3 is performed.
[0038]
The outputs of AND3 and AND4 are supplied to the switching lines 21 of the main panel 2 to the gate lines G3 and G4 via the level shifters 5a and 5b of the V level shifter 5. When the outputs of AND3 and AND4 are at the H level, the same H level voltage is supplied to gate lines G3 and G4 via level shifters 5a and 5b of V level shifter 5. Thereby, the switching transistor 21 is turned on. In this state, a video signal for the main panel 2 is supplied to the drain line D1, so that the video signal is supplied to the display electrode of the liquid crystal 22. Thereby, the display of the corresponding pixel of the main panel 2 is performed.
[0039]
During a period in which data is not supplied to the pixels of the main panel 2, the outputs of AND3 and AND4 are at L level, and the gate lines G3 and G4 are supplied with a negative voltage whose level has been converted by the level shifters 5a and 5b. .
[0040]
In the first embodiment, during the second and subsequent scans of the gate line by the V shift register 4, the outputs of AND1 and AND2 corresponding to the sub-panel 3 are forced to L level. That is, by setting the ENB signal to the L level (ENB1, ENB2) as shown in FIG. 3 at the time of scanning the second and subsequent gate lines of the sub-panel 3, the outputs of AND1 and AND2 corresponding to the sub-panel 3 are forcibly made. Set to L level. Thus, the output to the gate lines G1 and G2 is stopped at the time of the second and subsequent scans of the gate line by the V shift register 4. In this case, since the switching transistor 31 is turned off, no video signal is written. That is, in this case, AND1 and AND2 constitute the output stop circuit 41.
[0041]
In the sub-panel 3, the ENB signals (ENB1, ENB2) are set to the H level at a rate of about 10 to 50 times per second (about 10 Hz to 50 Hz) for a certain period of time, so that about 10 to 50 times per second. Since the switching transistor 31 is turned on, the video signal is written to the liquid crystal 32 of the sub panel 3 about 10 to 50 times per second.
[0042]
On the other hand, the gate lines G3 and G4 of the main panel 2 are set to the H level for a certain period during the second and subsequent scans, similarly to the first scan, by setting the ENB signals (ENB3 and ENB4) to the H level. And the G level is output to G4 for a certain period. As a result, the switching transistor 21 of the main panel 2 is turned on, so that a video signal is written to the liquid crystal 22 of the main panel 2.
[0043]
As described above, in the first embodiment, when both the main panel 2 and the sub panel 3 are used, the main panel 2 on which a moving image or the like is displayed is always driven at a high frequency (about 60 Hz) and the sub panel 3 Is rewritten at a frequency of about 10 to 50 times per second (about 10 Hz to about 50 Hz). In this case, if the number of times of rewriting of the liquid crystal 32 of the sub-panel 3 decreases, flicker (flicker) and display unevenness are likely to appear. 33 are provided. The auxiliary capacitance 33 of the sub-panel 3 preferably has a capacitance value that is three times or more the auxiliary capacitance 23 of the main panel 2. The auxiliary capacitance 33 of the sub-panel 3 having a capacitance value about three to four times the auxiliary capacitance 23 of the main panel 2 can be easily formed on the layout of the sub-panel 3. In this case, it is preferable that the sub panel 3 be rewritten at a frequency of about 15 to 20 times per second (about 15 Hz to about 20 Hz).
[0044]
When only the main panel 2 is used, the ENB signals (ENB1, ENB2) corresponding to the sub panel 3 need only be kept at the L level. In this case, since the outputs from AND1 and AND2 are always at L level, gate lines G1 and G2 are always held at L level. As a result, the switching transistor 31 is always turned off, so that no data is written in the liquid crystal 32 of the sub panel 3. In this case, the display of the sub panel 3 is not performed, and only the display of the main panel 2 is performed. In this case, AND1 and AND2 constitute an output stop circuit 41.
[0045]
When only the sub-panel 3 is used, the ENB signals (ENB3, ENB4) corresponding to the main panel 2 need only be kept at L level. In this case, since the outputs from AND3 and AND4 are always at L level, gate lines G3 and G4 are always kept at L level (negative voltage). As a result, the switching transistor 21 is always turned off, so that no data is written in the liquid crystal 22 of the main panel 2. In this case, the main panel 2 is not displayed, and only the sub panel 3 is displayed. AND3 and AND4 in this case constitute an output stop circuit 42.
[0046]
In the first embodiment, as described above, the main panel 2 and the sub panel 3 are provided on the same glass substrate 1, and the V shift register 4 and the H shift register 6 are shared by the main panel 2 and the sub panel 3. The size can be further reduced as compared with the case where the main panel 2 and the sub panel 3 are formed on separate glass substrates. Further, by sharing the glass substrate 1 with the V shift register 4 and the H shift register 6 between the main panel 2 and the sub panel 3, the number of parts can be further reduced and the assembling process can be further simplified. be able to. Thereby, the apparatus cost can be further reduced.
[0047]
In the first embodiment, the number of drain lines can be reduced by sharing the drain lines between the main panel 2 and the sub panel 3. As a result, power consumption can be reduced, and the frame can be narrowed.
[0048]
In the first embodiment, the power consumption can be reduced by providing the V level shifter 5 only in a portion corresponding to the main panel 2.
[0049]
Further, in the first embodiment, by providing the output stop circuit 41 for stopping the output of the portion corresponding to the sub-panel 3 of the V shift register 4, the main panel 2 for displaying a moving image or the like which requires a large number of data rewrites is provided. In the case where the V shift register 4 is shared with the sub-panel 3 which does not need a large number of times of data rewriting because a moving image or the like is not displayed, the output stop circuit 41 can lengthen only the rewriting cycle of the sub-panel 3. . As a result, even when the V shift register 4 is shared by the main panel 2 and the sub-panel 3, only the number of data rewrites of the sub-panel 3 can be easily reduced while the number of data rewrites of the main panel is kept large. .
[0050]
In the first embodiment, when only the main panel 2 is used without using the sub panel 3, the ENB signals (ENB 1, ENB 2) stop the output from the output stop circuit 41 (turn to L level). Is always at the L level, the sub-panel 3 can be easily put into a non-use state. When only the sub panel 3 is used without using the main panel 2, the ENB signals (ENB3, ENB4) are always set to the L level so that the output from the output stop circuit 42 is stopped (to the L level). Thus, the main panel 2 can be easily put into a non-use state.
[0051]
(2nd Embodiment)
FIG. 4 is a plan view illustrating a liquid crystal display device for a mobile phone including two display panels, a main panel and a sub panel, according to a second embodiment of the present invention. Referring to FIG. 4, in the second embodiment, unlike the first embodiment, an H shift register is arranged between a main panel and a sub panel. The details will be described below.
[0052]
In the second embodiment, as shown in FIG. 4, a main panel 52 and a sub panel 53 are formed in different regions on the same glass substrate 51. The main panel 52 and the sub panel 53 are arranged along the direction in which the drain line extends. The main panel 52 is of a transmissive type or a transflective type, and the sub panel 53 is of a reflective type. Thereby, a double-sided display type liquid crystal display device capable of displaying the main panel 52 and the sub-panel 53 on surfaces opposite to each other is obtained. The glass substrate 51 is an example of the “substrate” of the present invention. The main panel 52 is an example of the “first display panel” of the present invention, and the sub panel 53 is an example of the “second display panel” of the present invention.
[0053]
Here, in the second embodiment, an H shift register 56 is arranged between the main panel 52 and the sub panel 53. A drain line switch 57a for the main panel 52 is disposed between the H shift register 56 and the main panel 52. Further, a drain line switch 57b for the sub panel 53 is disposed between the H shift register 56 and the sub panel 53. The drain line switches 57a and 57b are provided for sequentially supplying video signals to the respective drain lines by sequentially turning on the switches in accordance with the sampling signal. Further, a V shift register 54 is arranged in a direction orthogonal to the direction in which the gate lines of the main panel 52 and the sub panel 53 extend. Further, between the V shift register 54 and the main panel 52, a V level shifter 55 is arranged only in a corresponding portion of the main panel 52. The V shift register 54 is shared by the main panel 52 and the sub panel 53, and the H shift register 56 is shared by the main panel 52 and the sub panel 53. Further, the drain line is shared by the main panel 52 and the sub panel 53.
[0054]
The V shift register 54 is an example of the “first shift register” of the present invention, and the H shift register 56 is an example of the “second shift register” of the present invention. The V level shifter 55 is an example of the “level shifter” of the present invention. The internal configurations of the main panel 52, the sub panel 53, the V shift register 54, and the V level shifter 55 are respectively the same as those of the main panel 2, the sub panel 3, the V shift register 4, and the V level shifter 5 of the first embodiment. The same is true.
[0055]
The V shift register 54 receives a positive voltage V from the external IC 10. _DD , A vertical clock signal VCLK, a start signal VST and an ENB signal. The V level shifter 55 receives a negative voltage V from the external IC 10. _BB Is supplied. The H shift register 56 receives a horizontal clock signal HCLK, a start signal HST, and a positive voltage V _DD Is supplied.
[0056]
The method of driving the V shift register 54 of the second embodiment is the same as the method of driving the V shift register 4 of the first embodiment.
[0057]
In the second embodiment, as described above, the H shift register 56 for driving the drain lines of the main panel 52 and the sub-panel 53 is disposed between the main panel 52 and the sub-panel 53, so that the H shift register 56 shown in FIG. Since the distance from the H shift register 56 to the sub-panel 53 is shorter than in the first embodiment, the load on the drain line of the sub-panel 53 can be reduced. Thereby, the transistor constituting the drain line switch 57b for the sub panel 53 can be reduced in size.
[0058]
In the second embodiment, as in the first embodiment, the main panel 52 and the sub-panel 53 are provided on the same glass substrate 51, and the V shift register 54 and the H shift register 56 are divided by the main panel 52 and the sub-panel 53. By sharing, the size can be further reduced as compared with the case where the main panel 52 and the sub-panel 53 are formed on separate glass substrates. Further, by sharing the glass substrate 51 and the V shift register 54 and the H shift register 56 between the main panel 52 and the sub panel 53, the number of parts can be further reduced and the assembling process can be further simplified. can do. Thereby, the apparatus cost can be further reduced.
[0059]
Other effects of the second embodiment are similar to those of the above-described first embodiment.
[0060]
It should be noted that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and includes all modifications within the scope and meaning equivalent to the terms of the claims.
[0061]
For example, in the above-described embodiment, an example in which the drain line is shared between the main panel and the sub-panel has been described. However, the present invention is not limited to this, and the gate line may be shared between the main panel and the sub-panel. . In this case, the main panel and the sub-panel may be arranged along the direction in which the gate lines extend.
[0062]
Further, in the above-described embodiment, an example in which both the V shift register and the H shift register are shared by the main panel and the sub panel has been described. However, the present invention is not limited to this, and the V shift register may be shared by the main panel and the sub panel. Only one of the register and the H shift register may be shared.
[0063]
Further, in the above-described embodiment, the liquid crystal display device for a mobile phone including two liquid crystal display panels of a main panel and a sub panel has been described as an example. However, the present invention is not limited to this, and other than a mobile phone including a plurality of display panels. The present invention can be similarly applied to a display device for portable devices and a display device for devices other than portable devices.
[0064]
Further, in the above-described embodiment, a case where two liquid crystal display panels including a main panel and a sub panel are included has been described. However, the present invention is not limited to this, and is similarly applicable to a case where three or more display panels are included. .
[0065]
In the above embodiment, the case where the present invention is applied to a display device including a liquid crystal display panel has been described. However, the present invention is not limited to this, and can be applied to a display device including a self-light emitting element such as an EL display panel. It is. When applied to an EL display panel, for example, the main panel may be of a top emission (Top Emission) type and the sub-panel may be of a bottom emission (Bottom Emission) type.
[0066]
In the above embodiment, the storage capacitor is connected to each pixel of the sub-panel for holding data for a certain period. However, the present invention is not limited to this, and the data is held for each pixel of the sub-panel for a certain period. For this purpose, an SRAM (static memory) may be incorporated.
[0067]
【The invention's effect】
As described above, according to the present invention, the first display panel and the second display panel are formed on the same glass substrate, and the shift register is shared. The size can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a liquid crystal display device for a mobile phone including a main panel and a sub panel according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing an internal configuration around a V shift register of the liquid crystal display device according to the first embodiment shown in FIG.
FIG. 3 is a timing chart for explaining a method of driving a V shift register of the liquid crystal display device according to the first embodiment shown in FIG.
FIG. 4 is a plan view illustrating a liquid crystal display device for a mobile phone including a main panel and a sub panel according to a second embodiment of the present invention.
FIG. 5 is a perspective view showing a conventional foldable mobile phone including a main panel and a sub panel.
FIG. 6 is a perspective view showing a conventional foldable mobile phone including a main panel and a sub panel.
[Explanation of symbols]
1,51 glass substrate (substrate)
2, 52 Main panel (first display panel)
3, 53 sub panel (second display panel)
4, 54 V shift register (first shift register)
5, 55 V level shifter (level shifter)
6, 56 H shift register (second shift register)
41, 42 output stop circuit

Claims (9)

A first display panel formed on a substrate,
A second display panel formed on the same substrate as the substrate and in a region different from a region where the first display panel is formed;
A display device, comprising: a shift register shared by the first display panel and the second display panel. A shift register shared by the first display panel and the second display panel,
A first shift register for driving a gate line of the first display panel and a gate line of the second display panel;
The display device according to claim 1, further comprising: a second shift register configured to drive a drain line of the first display panel and a drain line of the second display panel. The display device according to claim 2, wherein the first display panel and the second display panel are arranged along a direction in which the drain line extends. The first shift register is not disposed on a portion corresponding to the second display panel, but is disposed on a portion of the first shift register corresponding to the first display panel, and is disposed on a gate line of the first display panel. The display device according to claim 3, further comprising a level shifter for converting a voltage level of a signal to be applied. 5. The display according to claim 3, further comprising an output stop circuit that stops output of one of a portion corresponding to the first display panel and a portion corresponding to the second display panel of the first shift register. 6. apparatus. The display device according to any one of claims 2 to 5, wherein one of the gate line and the drain line is shared by the first display panel and the second display panel. The first display panel and the second display panel are arranged along a direction in which the drain line extends,
The display device according to claim 6, wherein the drain line is continuous from the first display panel to the second display panel. The display device according to claim 3, wherein a second shift register that drives the drain line is disposed between the first display panel and the second display panel. A first display panel formed on a substrate,
A second display panel formed on the same substrate as the substrate and in a region different from a region where the first display panel is formed;
Comprising a drain line and a gate line arranged to cross each other,
The display device, wherein one of the drain line and the gate line is continuous from the first display panel to the second display panel.

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