JP2004055882A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide such a technology that can specify the position of an LSI chip in a semiconductor wafer without adding a step for manufacturing a semiconductor device. <P>SOLUTION: The LSI chip is specified in vertical and horizontal positions according to the surface pattern of the LSI chip, and then the grinding trace on the backside of the LSI chip is fetched as an image data by an image fetching device for image processing. Next, an image data of the grinding trace of the backside of a semiconductor wafer that is beforehand fetched by the image fetching device is overlapped on the image data of the grinding trace of the backside of the LSI chip for verification, thus specifying the acquisition position of the LSI chip on the semiconductor wafer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology that is effective when applied to position detection of an LSI (Large Scaled Integrated Circuit) chip for specifying an LSI chip position in a semiconductor wafer.
[0002]
[Prior art]
In the manufacture of a semiconductor device, a large number of semiconductor integrated circuits are formed on one semiconductor wafer, and a group of regions of the semiconductor integrated circuit is cut out as rectangular LSI chips of several mm square to form one semiconductor device.
[0003]
By the way, when a defect occurs in an LSI chip in a customer, end user or in-house screening process, a failure analysis is performed to investigate the cause of the defect. However, the position of the LSI chip in a semiconductor wafer is determined by identifying the cause of the defect. It can be important.
[0004]
Therefore, a method of detecting the acquisition position of the LSI chip on the semiconductor wafer by giving the LSI chip information that can determine the position information has been studied. For example, a method has been proposed in which a pattern having position information is formed on the front or back surface of a semiconductor wafer by lithography and etching techniques, and the chip coordinates of the LSI chip on the semiconductor wafer are determined from the pattern data.
[0005]
For example, in Japanese Patent Application Laid-Open No. 9-246126, a concentric circle centered on the origin is formed on the back surface of a wafer, and the line width of the concentric circle is changed according to a quadrant of a coordinate composed of an X axis and a Y axis. A method for specifying chip coordinates of individual chips after cutting out a semiconductor integrated circuit substrate is disclosed.
[0006]
[Problems to be solved by the invention]
However, in the above-described chip position detection technology for forming a pattern having position information on the front surface or the back surface of a semiconductor wafer, since a detection pattern is formed, there is a problem that the number of manufacturing steps increases.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a technology capable of specifying a position in a semiconductor wafer where an LSI chip is located without adding a semiconductor device manufacturing process.
[0008]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
The present invention relates to a process for forming a semiconductor integrated circuit on a main surface of a semiconductor wafer, a process for grinding the back surface of the semiconductor wafer, and capturing grinding marks on the back surface of the semiconductor wafer as image data, Dividing the analysis chip, which is one of the plurality of LSI chips, from the top surface pattern information of the analysis chip, and capturing the grinding marks on the back surface of the analysis chip as image data; Superimposing the image data of the back surface grinding mark of the semiconductor wafer and the image data of the back surface grinding mark of the analysis chip to specify the acquisition position of the analysis chip on the semiconductor wafer.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0012]
FIG. 1 is a plan view showing an example of a surface of a semiconductor wafer according to an embodiment of the present invention, and shows an arrangement of LSI chips in the semiconductor wafer. FIG. 2 is a back view showing the back surface of the semiconductor wafer shown in FIG.
[0013]
The diameter of the semiconductor wafer 1 is, for example, 8 inches, and a plurality of LSI chips 2 are arranged in the semiconductor wafer 1. A semiconductor integrated circuit is formed on each of the LSI chips 2 on the main surface of each of the LSI chips 2 using a known technique.
[0014]
After the semiconductor integrated circuit is formed on the semiconductor wafer 1, the back surface of the semiconductor wafer 1 is ground using an infeed type (automatic intersection type) grinding device in order to remove deposits or process to a predetermined thickness. You. The grinding marks are left in a spiral form from the center of the semiconductor wafer 1, and the pattern has no difference between the apparatuses, and a spiral grinding mark always occurs.
[0015]
Next, a method of obtaining an acquisition position of an LSI chip on a semiconductor wafer will be described below.
[0016]
FIG. 3 is a process chart showing an example of a procedure of a method for specifying an acquisition position of an LSI chip on a semiconductor wafer. FIG. 4 is a diagram in which image data of the back surface grinding mark of the semiconductor wafer and image data of the back surface grinding mark of the LSI chip are superimposed.
[0017]
Grinding marks on the back surface of the semiconductor wafer are previously captured in the image capturing device as image data 1a (step 100 in FIG. 3). Next, when positional information is required for an LSI chip cut into a rectangular shape of several mm square, first, top, bottom, left and right of the LSI chip are specified from surface pattern information of the LSI chip (step 101 in FIG. 3).
[0018]
Next, a grinding mark on the back surface of the LSI chip is captured as image data 2a by an image capturing device (step 102 in FIG. 3), and the contrast or brightness is changed so that the image data 2a of the grinding mark becomes clear. (Step 103 in FIG. 3). Next, the image data 1a of the back surface grinding mark of the semiconductor wafer and the image data 2a of the back surface grinding mark of the LSI chip are superimposed and collated (Step 104 in FIG. 3), and the acquisition position of the LSI chip on the semiconductor wafer is specified. (Step 105 in FIG. 3).
[0019]
As described above, since the acquisition position of the LSI chip in the semiconductor wafer can be obtained from the grinding mark on the back surface of the LSI chip, even if the LSI chip is separated from the semiconductor wafer, the LSI chip can be easily obtained. The acquisition position can be specified. Therefore, even if the LSI chip is packaged, the acquisition position can be specified if the LSI chip can be peeled off from the package and a grinding mark on the back surface can be confirmed.
[0020]
Next, a method for manufacturing a semiconductor device to which the present invention is applied will be briefly described with reference to FIGS. FIGS. 5 and 6 illustrate a CMOS (Complementary Metal Oxide Semiconductor) device as an example of a device included in a semiconductor device.
[0021]
First, as shown in FIG. 5, a semiconductor substrate (semiconductor wafer processed into a thin circular plate) 11 made of, for example, p-type silicon single crystal is prepared. Next, after the element isolation portion 12 is formed in the semiconductor substrate 11, impurities are ion-implanted into the semiconductor substrate 11 using the resist pattern as a mask to form a p-well 13 and an n-well 14. A p-type impurity, for example, boron is ion-implanted into the p-well 13, and an n-type impurity, for example, phosphorus is ion-implanted into the n-well 14. Thereafter, impurities for controlling the threshold value of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) may be ion-implanted into each well region.
[0022]
Next, after a silicon oxide film serving as a gate insulating film, a silicon polycrystalline film serving as a gate electrode, and a silicon oxide film serving as a cap insulating film are sequentially deposited to form a stacked film, the stacked film is formed using a resist pattern as a mask. By etching, the gate insulating film 15, the gate electrode 16, and the cap insulating film 17 are formed. Thereafter, a silicon oxide film is deposited on the semiconductor substrate 11 by a CVD (Chemical Vapor Deposition) method, and the silicon oxide film is anisotropically etched to form a sidewall spacer 18 on the side wall of the gate electrode 16. Thereafter, an n-type impurity, for example, arsenic is ion-implanted into the p-well 13 using the resist pattern as a mask to form an n-type semiconductor region 19 on both sides of the gate electrode 16 in the p-well 13. The n-type semiconductor region 19 is formed in a self-aligned manner with respect to the gate electrode 16 and the sidewall spacer 18, and functions as a source / drain of the n-channel MISFET Qn.
[0023]
Similarly, a p-type impurity, for example, boron fluoride is ion-implanted into the n-well 14 using the resist pattern as a mask, and p-type semiconductor regions 20 are formed on both sides of the gate electrode 16 in the n-well 14. The p-type semiconductor region 20 is formed in a self-aligned manner with respect to the gate electrode 16 and the sidewall spacer 18, and functions as a source / drain of the p-channel MISFET Qp.
[0024]
Next, as shown in FIG. 6, after forming a silicon oxide film 21 on the semiconductor substrate 11, the surface of the silicon oxide film 21 is flattened by polishing it by, for example, a CMP (Chemical Mechanical Polishing) method. Subsequently, connection holes 22 are formed in the silicon oxide film 21 by dry etching using the resist pattern as a mask. The connection hole 22 is formed in a necessary portion such as on the n-type semiconductor region 19 or the p-type semiconductor region 20.
[0025]
Subsequently, a titanium nitride film is formed on the entire surface of the semiconductor substrate 11 including the inside of the connection hole 22 by, for example, the CVD method, and a tungsten film for filling the connection hole 22 is formed by, for example, the CVD method. The titanium nitride film and the tungsten film in the region are removed by the CMP method to form a plug 23 having the tungsten film as a main conductor layer inside the connection hole 22.
[0026]
Next, after forming, for example, a tungsten film on the semiconductor substrate 11, the tungsten film is processed by dry etching using a resist pattern as a mask to form the wiring 24 of the first wiring layer. The tungsten film can be formed by, for example, a CVD method or a sputtering method.
[0027]
Next, after an insulating film covering the wiring 24, for example, a silicon oxide film is formed, the insulating film is polished by, for example, a CMP method to form an interlayer insulating film 25 having a flattened surface. Next, a connection hole 26 is formed in a predetermined region of the interlayer insulating film 25 by dry etching using the resist pattern as a mask.
[0028]
Subsequently, a barrier metal layer is formed on the entire surface of the semiconductor substrate 11 including the inside of the connection hole 26, and a copper film filling the connection hole 26 is formed. The barrier metal layer is, for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like, and is formed by, for example, a CVD method or a sputtering method. The copper film functions as a main conductor layer and can be formed by, for example, a plating method. Before forming a copper film by plating, a thin copper film can be formed as a seed layer by, for example, a CVD method or a sputtering method. Thereafter, the copper film and the barrier metal layer in a region other than the connection hole 26 are removed by the CMP method, and a plug 27 is formed inside the connection hole 26.
[0029]
Next, a stopper insulating film 28 is formed on the semiconductor substrate 11, and an insulating film 29 for forming a wiring is further formed. The stopper insulating film 28 is, for example, a silicon nitride film, and the insulating film 29 is, for example, a silicon oxide film. Next, wiring grooves 30 are formed in predetermined regions of the stopper insulating film 28 and the insulating film 29 by etching using the resist pattern as a mask.
[0030]
Subsequently, a barrier metal layer is formed on the entire surface of the semiconductor substrate 11 including the inside of the wiring groove 30, and a copper film filling the wiring groove 30 is formed. After that, the copper film and the barrier metal layer in the region other than the wiring groove 30 are removed by the CMP method, and the wiring 31 of the second wiring layer having the copper film as a main conductor layer is formed inside the wiring groove 30. Further, a CMOS device is completed by forming a wiring in an upper layer, and a semiconductor integrated circuit having a predetermined device as an example of the CMOS device is formed in each semiconductor chip.
[0031]
Next, the back surface of the semiconductor substrate 11 is removed by using an in-feed type grinding device in order to remove a formed film and foreign substances attached to the back surface of the semiconductor substrate 11 and to make the thickness of the semiconductor substrate 11 a predetermined thickness. Grind. As shown in FIG. 2, the grinding marks are left swirling from the center of the semiconductor substrate 11. Subsequently, the grinding marks on the back surface of the semiconductor substrate 11 are captured as image data by an image capturing device.
[0032]
Next, after determining whether each semiconductor chip formed on the semiconductor substrate 11 is good or bad, the semiconductor substrate 11 is cut into individual semiconductor chips.
[0033]
Next, as shown in FIG. 7, the semiconductor chip 32 determined to be non-defective is placed on the island (tab) 33 of the lead frame, and the back surface of the semiconductor chip 32 is attached to the island 33. Subsequently, after connecting the electrode pads on the semiconductor chip 32 and the leads 34 of the lead frame with gold wires 35, the lead frame on which the semiconductor chip 32 is mounted is set in a mold, and the resin 36 is pressure-fed to send the semiconductor chip 32. Wrap and mold the whole. Next, the individual semiconductor devices are separated from the lead frame, the leads are formed, and the leads are plated with solder. Then, the trademark, product name, lot number, and the like are stamped on the surface of the mold with a laser. Further, the semiconductor device is selected by performing a characteristic inspection, an appearance inspection, a reliability test, and the like of the semiconductor device.
[0034]
Thereafter, the semiconductor device determined to be non-defective is shipped. If a defective semiconductor device is found in the customer, end-user, or in-house selection process, a failure analysis of the semiconductor device to determine the cause of the failure is performed. The result is fed back to the apparatus or process conditions of the manufacturing process. In the failure analysis of the semiconductor device, first, the semiconductor chip 32 is taken out from the package, and then the grinding marks on the back surface of the semiconductor chip 32 are taken as image data into an image capturing device. By superimposing the image data of the grinding marks on the back surface of the chip 32, the acquisition position of the semiconductor chip 32 on the semiconductor substrate 11 is specified.
[0035]
Next, taking as an example a semiconductor device in which a semiconductor integrated circuit having a predetermined device including the CMOS device shown in FIG. 6 is built, a method of analysis (here, a method of failure analysis) shown in FIG. This will be described with reference to the drawings.
[0036]
When a defect is found in a semiconductor device in a customer, end user or in-house screening process, a chip to be analyzed (hereinafter, referred to as an analysis chip) is first taken out of the package, and according to the method shown in FIG. The acquisition position is specified (step 100 in FIG. 8).
[0037]
Next, the cause of the failure of the semiconductor device is clarified (step 101 in FIG. 8). Further, the manufacturing process that caused the cause of the failure of the semiconductor device is estimated from the result, and the device or process conditions used in the manufacturing process are compared with the position information of the analysis chip on the semiconductor wafer, thereby obtaining the semiconductor device in the manufacturing process. The cause is clarified (step 102 in FIG. 8).
[0038]
For example, if the cause of the failure of the semiconductor device is confirmed to be the opening failure of the connection hole 22 of the CMOS device, the manufacturing process that further causes the opening failure of the connection hole 22 is estimated. As a manufacturing process that causes a defective opening of the connection hole 22, for example, a lithography process or a dry etching process can be given. For example, the distribution of a plurality of analysis chips on a semiconductor wafer is a dry etching device for forming the connection hole 22. In this case, the manufacturing process that caused the opening failure of the connection hole 22 can be a dry etching process, and the cause of the manufacturing process can be the non-uniformity of the plasma distribution of the dry etching apparatus.
[0039]
Next, the result obtained by the failure analysis is fed back to the manufacturing process that caused the cause of the failure of the semiconductor device (step 103 in FIG. 8). For example, the uniformity of the plasma distribution of the dry etching apparatus when forming the connection hole 22 is improved, and the opening of the connection hole 22 is ensured. Thereby, high reliability of the semiconductor device can be obtained without the opening defect of the connection hole 22.
[0040]
In the present embodiment, a method for manufacturing a CMOS device is described as an example of a method for manufacturing a semiconductor device. However, the present invention can be applied to a semiconductor device on which any device is mounted.
[0041]
Further, in the present embodiment, the semiconductor chip packaged by the transfer molding method has been exemplified. The present invention can be applied to a semiconductor chip or the like attached to a tab using an agent.
[0042]
As described above, according to the present embodiment, the acquisition position of the LSI chip 2 can be specified using the grinding marks on the back surface of the semiconductor wafer 1, so that the LSI chip 2 can be mounted on the semiconductor wafer 1 without increasing the number of manufacturing steps. Even after cutting out from the wafer 1, it is possible to easily specify the position in the semiconductor wafer 1 where the LSI 2 chip is located.
[0043]
Further, even in the failure analysis using the LSI chip 2, since accurate position information of the defective portion in the semiconductor wafer 1 can be obtained, the manufacturing process causing the failure in the semiconductor device and the cause thereof can be more accurately and quickly performed. Can be grasped.
[0044]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0045]
For example, in the above-described embodiment, a case has been described in which the present invention is applied to the analysis of defective LSI chips. However, the present invention is not limited to the analysis of defective products, and positional information in a semiconductor wafer is required. It can be applied to any LSI chip.
[0046]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0047]
Even without cutting out the LSI chip from the semiconductor wafer, it is possible to easily specify the position in the semiconductor wafer where the LSI chip is located without adding a semiconductor device manufacturing process.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a surface of a semiconductor wafer according to an embodiment of the present invention.
FIG. 2 is a back view showing a back surface of the semiconductor wafer shown in FIG. 1;
FIG. 3 is a process diagram showing an example of a procedure of a method for specifying an acquisition position of an LSI chip on a semiconductor wafer according to an embodiment of the present invention.
FIG. 4 is a diagram in which image data of a back surface grinding mark of a semiconductor wafer and image data of a back surface grinding mark of an LSI chip according to an embodiment of the present invention are superimposed.
FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a semiconductor device to which the present invention is applied in the order of steps;
FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a semiconductor device to which the present invention is applied in the order of steps;
FIG. 7 is a schematic diagram of a package structure showing a method of manufacturing a semiconductor device to which the present invention is applied in the order of steps.
FIG. 8 is a process chart showing a method for analyzing a failure of a semiconductor device in which a semiconductor integrated circuit according to an embodiment of the present invention is fabricated.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Image data 2 LSI chip 2a Image data 11 Semiconductor substrate 12 Element separation part 13 P well 14 N well 15 Gate insulating film 16 Gate electrode 17 Cap insulating film 18 Sidewall spacer 19 N type semiconductor region 20 P type semiconductor region Reference Signs List 21 silicon oxide film 22 connection hole 23 plug 24 wiring 25 interlayer insulating film 26 connection hole 27 plug 28 stopper insulating film 29 insulating film 30 wiring groove 31 wiring 32 semiconductor chip 33 island 34 lead 35 gold wire 36 resin Qn n-channel MISFET
Qp p-channel MISFET

Claims (4)

(A) forming a semiconductor integrated circuit on a main surface of a semiconductor wafer;
(B) grinding the back surface of the semiconductor wafer and capturing grinding marks on the back surface of the semiconductor wafer as image data;
(C) dividing the semiconductor wafer into a plurality of chips;
(D) specifying the top, bottom, left and right of an analysis chip, which is one of the plurality of chips, from surface pattern information of the analysis chip;
(E) capturing grinding marks on the back surface of the analysis chip as image data;
(F) superimposing the image data of the back surface grinding mark of the semiconductor wafer and the image data of the back surface grinding mark of the analysis chip to specify an acquisition position of the analysis chip on the semiconductor wafer. A method for manufacturing a semiconductor device, comprising: (A) forming a semiconductor integrated circuit on a main surface of a semiconductor wafer;
(B) grinding the back surface of the semiconductor wafer and capturing grinding marks on the back surface of the semiconductor wafer as image data;
(C) dividing the semiconductor wafer into a plurality of chips;
(D) specifying the top, bottom, left and right of an analysis chip, which is one of the plurality of chips, from surface pattern information of the analysis chip;
(E) capturing grinding marks on the back surface of the analysis chip as image data;
(F) superimposing the image data of the back surface grinding mark of the semiconductor wafer and the image data of the back surface grinding mark of the analysis chip to specify an acquisition position of the analysis chip on the semiconductor wafer. ,
A method for manufacturing a semiconductor device, wherein image data of a back grinding mark of the analysis chip is subjected to image processing so that the pattern becomes clear. (A) forming a semiconductor integrated circuit on a main surface of a semiconductor wafer;
(B) grinding the back surface of the semiconductor wafer and capturing grinding marks on the back surface of the semiconductor wafer as image data;
(C) dividing the semiconductor wafer into a plurality of chips;
(D) specifying the top, bottom, left and right of an analysis chip, which is one of the plurality of chips, from surface pattern information of the analysis chip;
(E) capturing grinding marks on the back surface of the analysis chip as image data;
(F) superimposing the image data of the back surface grinding mark of the semiconductor wafer and the image data of the back surface grinding mark of the analysis chip to specify an acquisition position of the analysis chip on the semiconductor wafer. ,
A method of manufacturing a semiconductor device, wherein grinding marks on the back surface of the semiconductor wafer are left so as to swirl from a central portion of the semiconductor wafer. (A) forming a semiconductor integrated circuit on a main surface of a semiconductor wafer;
(B) grinding the back surface of the semiconductor wafer and capturing grinding marks on the back surface of the semiconductor wafer as image data;
(C) dividing the semiconductor wafer into a plurality of chips;
(D) specifying the top, bottom, left and right of an analysis chip, which is one of the plurality of chips, from surface pattern information of the analysis chip;
(E) capturing grinding marks on the back surface of the analysis chip as image data;
(F) superimposing the image data of the back surface grinding mark of the semiconductor wafer and the image data of the back surface grinding mark of the analysis chip to specify an acquisition position of the analysis chip on the semiconductor wafer. ,
A method of manufacturing a semiconductor device, comprising: performing a failure analysis on the analysis chip including an acquisition position of the analysis chip on the semiconductor wafer; and feeding back a result of the failure analysis to a manufacturing process.

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