JP2004048928A - Motor and disk unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor that allows stable speed control until the motor reaches steady state rotation from startup without causing fault detection at a PWM-off time, and to provide a disk unit using the motor. <P>SOLUTION: The motor comprises a position detector 30 that includes a voltage comparator 31, a detection pulse generator 32, a removal pulse generator 33 and a position detection switch 34. The motor is configured such that: a position detection switch signal DS of the position detection switch 34 is outputted in response to a speed command signal Ac of a command unit 40; and the position detector 30 performs position detection using the position detection switch signal DS by switching first position detection that performs position detection at only a PWM-on side and second position detection that performs position detection at both PWM-on/off sides. The second position detection is performed until the motor reaches the steady state rotation from the startup, and the first position detection is performed at the steady state rotation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a motor that is driven and controlled by a PWM (pulse width modulation) sensorless drive, and a disk device using the motor.
[0002]
[Prior art]
FIG. 12 is a block diagram showing a configuration of a conventional motor. The operation of the conventional motor will be briefly described with reference to FIG. The rotor 1010 has a field portion made of a permanent magnet, and generates a rotating force by interaction with the coils 1011, 1012, and 1013. The power supply 1020 includes three upper power transistors 1021, 1022, 1023 and three lower power transistors 1025, 1026, 1027, and supplies power to the coils 1011, 1012, 1013, respectively. The position detector 1030 compares the terminal voltages V1, V2, V3 at one ends of the coils 1011, 1012, 1013 with the common voltage Vc, and outputs a detection pulse signal FG corresponding to the comparison result. The command device 1040 outputs a speed command signal EC for controlling the speed of the rotor 1010. The switching controller 1050 outputs a main PWM signal Wp for causing the upper power transistors 1021, 1022, and 1023 of the power supply 1020 to perform a high-frequency switching operation in response to the speed command signal EC of the command device 1040. The energization controller 1060 controls the energization of the coils 1011, 1012, and 1013 in response to the detection pulse signal FG of the position detector 1030 and the main PWM signal Wp of the switching controller 1050. , 1023 and lower power supply control signals M1, M2, M3 for controlling the lower power transistors 1025, 1026, 1027. The power supply 1020 to which the upper energization control signals N1, N2, and N3 and the lower energization control signals M1, M2, and M3 are input supplies power to the coils 1011, 1012, and 1013, and performs PWM sensorless driving of the motor. .
[0003]
[Problems to be solved by the invention]
However, the conventional motor configured as described above has the following problems. In the conventional motor shown in FIG. 12, while performing the PWM operation, the position detector 1030 detects the position of the rotor 1010 by comparing the terminal voltages V1, V2, V3 of the coils 1011, 1012, 1013 with the common voltage Vc. I have. In the conventional motor, since the PWM sensorless drive is performed, the voltage on the “L” side (PWM off side) of the PWM signal is unstable, and erroneous detection is performed when the position is detected on the PWM off side. The likelihood was high. In the erroneous detection in the position detector 1030, the fluctuation of the detection pulse signal FG becomes large. When the speed control of the rotor 1010 is performed using the detection pulse signal FG, the speed fluctuation of the rotor 1010 becomes large, so that there is a problem that the jitter is deteriorated. Therefore, for the purpose of eliminating erroneous detection on the PWM off side, a system that does not perform position detection on the PWM off side can be considered. However, in the case of this method, erroneous detection or no detection is performed in a transitional state from the start to the steady rotation, and the erroneous detection or non-detection may cause a failure in pulling in the PWM sensorless drive. . Therefore, it has been a problem in this field to eliminate the erroneous detection on the PWM off side and to obtain a configuration capable of performing stable speed control from the start to the steady rotation.
[0004]
The present invention has been made to solve the above-described problem, and provides a motor capable of eliminating erroneous detection on the PWM off side and performing stable speed control from startup to steady rotation, and a disk device using the same. The purpose is to provide.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a motor according to the present invention includes a rotor having a permanent magnet,
A multi-phase coil arranged on the stator,
DC power supply means serving as a power supply source,
First switching means for supplying power from one terminal side of the DC power supply means to one end of the multi-phase coil, and power supply from the other terminal side of the DC power supply means to one end of the multi-phase coil. Power supply means including second switching means for performing
Command means for outputting a speed command signal;
Switching operation means for outputting a switching pulse signal for causing at least one of the first switching means and the second switching means of the power supply means to perform a high-frequency switching operation in response to the speed command signal;
Position detection switching means for outputting a position detection switching signal in response to a speed command signal of the command means, and detecting a rotation position of the rotor from terminal voltages of the coils of the plurality of phases to output a detection signal Means,
Energization control means for controlling energization of the power supply means in response to a detection signal of the position detection means,
The position detection means performs first position detection for detecting the position of the rotor in an ON period of the switching pulse signal, and second position detection for detecting the position of the rotor in both ON and OFF periods of the switching pulse signal. 2 is switched and executed by the position detection switching signal.
With this configuration, by using the first position detection, erroneous detection on the PWM off side of the position detection unit can be eliminated, and the fluctuation of the output signal can be reduced. Further, by performing the position detection by switching the first position detection and the second position detection by the position detection switching signal, stable speed control can be performed from the start to the steady rotation.
[0006]
A disk device according to the present invention reproduces a signal from a disk, or a head unit that performs signal recording on a disk,
An information processing means for processing the output signal of the head means to output a reproduction information signal, or for processing the recording information signal to output to the head means;
A rotor having a permanent magnet that directly drives the disk to rotate,
A multi-phase coil arranged on the stator,
DC power supply means serving as a power supply source,
First switching means for supplying power from one terminal side of the DC power supply means to one end of the multi-phase coil, and power supply from the other terminal side of the DC power supply means to one end of the multi-phase coil. Power supply means including second switching means for performing
Command means for outputting a speed command signal;
Switching operation means for outputting a switching pulse signal for causing at least one of the first switching means and the second switching means of the power supply means to perform a high-frequency switching operation in response to the speed command signal;
Position detection switching means for outputting a position detection switching signal in response to a speed command signal of the command means, and detecting a rotation position of the rotor from terminal voltages of the coils of the plurality of phases to output a detection signal Means,
Energization control means for controlling energization of the power supply means in response to a detection signal of the position detection means,
A first position detection unit that performs position detection of the rotor during an ON period of the switching pulse signal; and a second position detection unit that performs position detection of the rotor during both an ON period and an OFF period of the switching pulse signal. 2 is switched and executed by the position detection switching signal.
With this configuration, by using the first position detection, erroneous detection on the PWM off side of the position detection unit can be eliminated, and the fluctuation of the output signal can be reduced. Further, by performing the position detection by switching the first position detection and the second position detection by the position detection switching signal, stable speed control can be performed from the start to the steady rotation.
These and other configurations and operations will be described in detail in the embodiments.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment according to the present invention will be described as a first embodiment with reference to the attached FIGS. 1 to 11.
[0008]
<< Embodiment 1 >>
FIG. 1 is a block diagram showing the overall configuration of the disk device according to the first embodiment of the present invention. In FIG. 1, a permanent magnet is attached to a rotor 10 as a field part, and a magnetic flux generated by the permanent magnet generates a field magnetic flux of a plurality of poles. The three-phase coils 11, 12, and 13 are provided on a stator that is a fixed body, and are electrically shifted from the rotor 10 by 120 degrees. One of the coils 11, 12, 13 is connected to a power supply 20 as a power supply means, and the other is commonly connected. Three-phase driving currents I1, I2, and I3 flow through the three-phase coils 11, 12, and 13, respectively, to generate three-phase magnetic flux, and a driving force is generated by interaction with the rotor 10. As a result, the rotor 10 and the disk 1 attached to the rotor 10 rotate.
Digital information is recorded on the disk 1, and the digital information is read by a head 2 which is a magnetic means or an optical head which is a head means. The information processing device 3 as an information processing means performs signal processing on the read digital information and outputs it as a reproduction information signal. In the case where the disc 1 is a recordable disc, when a recording information signal is input to the information processing device 3, the information processing device 3 outputs digital information subjected to signal processing to the head 2, and Digital information is recorded.
[0009]
A DC power supply 5 serving as a DC power supply means of a power supply source has a negative terminal side at a ground potential and supplies a required DC voltage (Vm) to a positive terminal side. To the positive terminal (Vm side) of the DC power supply 5, the current inflow terminals of three upper power transistors 21, 22, and 23, which are the first switching means, are commonly connected via a current detector 51. The power supply terminals of the three-phase coils 11, 12, and 13 are connected to the current outflow terminals of the three-phase upper power transistors 21, 22, and 23, respectively.
On the other hand, to the negative terminal side (earth side) of the DC power supply 5, the current outflow terminals of the three lower power transistors 25, 26, and 27, which are the second switching means, are commonly connected. Power supply terminals of the three-phase coils 11, 12, and 13 are connected to current inflow terminals of the lower power transistors 25, 26, and 27, respectively.
Further, upper power diodes 21d, 22d, and 23d are connected in anti-parallel to upper power transistors 21, 22, 23, respectively, and lower power diodes 25d, 26d, and 27d are connected to lower power transistors 25, 26, and 27, respectively. They are connected in parallel.
[0010]
In the first embodiment, N-channel field-effect power transistors are used as the upper power transistors 21, 22, 23 and the lower power transistors 25, 26, 27. Parasitic diodes formed in anti-parallel to these N-channel field effect power transistors are used as upper power diodes 21d, 22d, 23d and lower power diodes 25d, 26d, 27d.
The power supply 20 includes upper power transistors 21, 22, 23 and lower power transistors 25, 26, 27, and upper power diodes 21d, 22d, 23d and lower power diodes 25d, 26d, 27d. The power supply 20 responds to the upper power supply control signals N1, N2, and N3 and the lower power supply control signals M1, M2, and M3 of the power supply controller 60, which is a power supply control unit, and receives a signal from the DC power supply 5 that is a power supply source. A current path to the three-phase coils 11, 12, and 13 is formed, and power is supplied to the three-phase coils 11, 12, and 13.
[0011]
In the power supply 20, the upper power transistors 21, 22 and 23 are controlled to open and close in response to the upper power control signals N 1, N 2 and N 3 from the power controller 60, and the positive terminal of the DC power supply 5 and the three-phase coil 11 are controlled. , 12, and 13, the power supply path between the power supply terminals opens and closes. By this opening / closing operation, a current path for supplying the driving currents I1, I2, I3 to the positive electrodes of the three-phase coils 11, 12, 13 is formed.
The upper energization control signals N1, N2, and N3 input to the power supply 20 are formed into digital PWM signals in each energization section by a main PWM signal Wp from a switching operation device 50 as a switching operation means. Therefore, the upper power transistors 21, 22, and 23 perform a high-frequency switching operation.
Further, in the power supply 20, in response to the lower energization control signals M1, M2, M3 from the energization controller 60, the lower power transistors 25, 26, 27 are opened and closed, and the negative terminal of the DC power supply 5 The power supply path between the power supply terminals of the three-phase coils 11, 12, 13 opens and closes. By this opening / closing operation, a current path for supplying the driving currents I1, I2, I3 to the positive electrodes of the three-phase coils 11, 12, 13 is formed. The lower energization control signals M1, M2, and M3 are complementary to the on / off high-frequency switching operation of the upper power transistors 21, 22, and 23 in the same phase and complementarily by the auxiliary PWM signal Ws of the switching operator 50. 26 and 27 are turned on / off by a high-frequency switching operation (synchronous rectification operation). The details of the switching operation device 50 will be described later.
[0012]
The position detector 30, which is a position detecting means, includes a voltage comparator 31, a detection pulse generator 32, a noise removal pulse generator 33, and a position detection switch 34, and detects the rotational positions of the disk 1 and the rotor 10. Then, a detection pulse signal FG corresponding to the detected position is output. The voltage comparator 31 directly compares the three-phase terminal voltages V1, V2, and V3 generated at one ends of the three-phase coils 11, 12, and 13 with the commonly connected midpoint voltage Vc, respectively, and a voltage corresponding to the comparison result. It outputs comparison signals C1, C2 and C3. The detection pulse creator 32 removes the switching noise caused by the high frequency switching operation included in the voltage comparison signals C1, C2, and C3 of the voltage comparator 31 by the noise elimination signal Wm of the noise elimination pulse creator 33, and removes the disk 1 and the rotor. 10 is detected, and a detection pulse signal FG is output. The noise elimination pulse generator 33 selectively switches between the first position detection and the second position detection in accordance with the position detection switching signal DS of the position detection switch 34 serving as the position detection switching means. Wm is output to the detection pulse generator 32. The position detection switch 34 outputs a position detection switch signal DS in response to the speed command signal Ac of the command device 40. That is, the position detector 30 performs position detection by switching between the first position detection and the second position detection in response to the speed command signal Ac, and outputs the detection pulse signal FG. The detection pulse signal FG output from the position detector 30 is input to the command device 40 and the conduction controller 60.
The details of the detection operation (the first position detection operation and the second position detection operation) will be described later.
[0013]
The command device 40 as a command means includes a speed control circuit for controlling the rotation speed of the disk 1 and the rotor 10 to a predetermined value, and the rotation speed of the disk 1 and the rotor 10 is determined by the detection pulse signal FG of the position detector 30. And outputs a speed command signal Ac corresponding to the difference from the target rotation speed to the switching actuator 50 and the position detector 30. Here, the speed command signal Ac is a voltage signal.
The switching operation device 50 includes a current detector 51 and a switching controller 52. FIG. 2 is a block diagram showing a specific configuration of the switching operation device 50. The current detector 51 includes a current detection resistor 110, and supplies the current from the positive terminal side (Vm side) of the DC power supply 5 to the three-phase coils 11, 12, and 13 via the upper power transistors 21, 22, and 23. It outputs a current detection signal Ad proportional to the conduction current or the supply current. The switching controller 52 compares the current detection signal Ad of the current detector 51 with the speed command signal Ac from the command device 40, and responds to the comparison result with the basic PWM signal Wb, the main PWM signal Wp, and the auxiliary PWM signal Ws. Is output.
[0014]
The basic PWM signal Wb is input to the noise removal pulse generator 33 of the position detector 30, and the main PWM signal Wp and the auxiliary PWM signal Ws are input to the energization controller 60. The main PWM signal Wp causes the upper power transistors 21, 22, 23 of the power supply 20 to perform a PWM operation, and the auxiliary PWM signal Ws causes the lower power transistors 25, 26, 27 to perform a synchronous rectification operation. The switching controller 52 includes a comparison circuit 111, a reference trigger generation circuit 112, a PWM signal generation circuit 113, and a PWM pulse circuit 114. The comparison circuit 111 compares the current detection signal Ad of the current detector 51 with the speed command signal Ac of the command device 40, and outputs a PWM reset signal Pr corresponding to the comparison result. Specifically, when the current detection signal Ad becomes larger than the speed command signal Ac, the state of the PWM reset signal Pr changes from “L” level to “H” level. The reference trigger generation circuit 112 is a circuit that outputs a reference trigger signal Ps at a constant frequency. The PWM signal creation circuit 113 outputs a basic PWM signal Wb based on the PWM reset signal Pr of the comparison circuit 111 and the reference trigger signal Ps of the reference trigger generation circuit 112. The basic PWM signal Wb is a signal that changes its state to “H” level by the reference trigger signal Ps and changes to “L” level by the PWM reset signal Pr.
[0015]
FIG. 3 is a waveform diagram showing the relationship among the reference trigger signal Ps, the PWM reset signal Pr, the basic PWM signal Wb, and the like. The state of the basic PWM signal Wb changes to “H” level at the rising edge of the reference trigger signal Ps having a constant frequency, and changes to “L” level at the rising edge of the PWM reset signal Pr. Thus, the basic PWM signal Wb is a PWM signal responsive to the result of the comparison between the current detection signal Ad and the speed command signal Ac. That is, the basic PWM signal Wb is a PWM signal that changes the duty in response to the speed command signal Ac of the command device 40. Specifically, when the actual rotation speeds of the disk 1 and the rotor 10 are lower than the target rotation speed, the speed command signal Ac of the command device 40 increases, and the on-duty of the basic PWM signal Wb increases. Conversely, when the actual rotation speeds of the disk 1 and the rotor 10 are higher than the target rotation speed, the speed command signal Ac of the command device 40 decreases, and the on-duty of the basic PWM signal Wb decreases. When the target rotation speed and the actual rotation speeds of the disk 1 and the rotor 10 are substantially equal, the speed command signal Ac of the command device 40 has a value corresponding to the target rotation speed, and the on-duty of the basic PWM signal Wb is substantially equal to the target rotation speed. Is a value corresponding to. As described above, the command device 40 detects the rotational speeds of the disk 1 and the rotor 10 from the detection pulse signal FG of the position detector 30, and outputs a speed command signal Ac corresponding to the difference from the target rotational speed. The speed of the disk 1 and the rotor 10 is controlled by changing the on-duty of the basic PWM signal Wb in response to the speed command signal Ac.
[0016]
In the disk device according to the first embodiment, the configuration has been described in which the PWM signal is generated so that the PWM frequency is constant. However, the PWM frequency does not necessarily need to be constant. For example, a PWM signal in which the PWM off period is constant may be used. It is good also as composition which creates. The basic PWM signal Wb of the PWM signal generation circuit 113 is input to the noise removal pulse generator 33 of the position detector 30 and also to the PWM pulse circuit 114.
FIG. 3 shows the relationship between the main PWM signal Wp and the auxiliary PWM signal Ws output from the PWM pulse circuit 114 together with the basic PWM signal Wb input to the PWM pulse circuit 114. The PWM pulse circuit 114 includes a main PWM signal Wp for driving the upper power transistors 21, 22, and 23 of the power supply 20 by PWM and an auxiliary PWM for driving the lower power transistors 25, 26, and 27 of the power supply 20 to perform synchronous rectification. The signal Ws is output. The rising edge of the main PWM signal Wp occurs at a timing delayed by the dead time Ta from the rising edge of the basic PWM signal Wb, and the falling edge of the main PWM signal Wp is synchronized with the falling edge of the basic PWM signal Wb. . The rising edge of the auxiliary PWM signal Ws occurs at a timing delayed by the dead time Ta from the falling edge of the basic PWM signal Wb, and the falling edge of the auxiliary PWM signal Ws is synchronized with the rising edge of the basic PWM signal Wb. ing. The main PWM signal Wp and the auxiliary PWM signal Ws of the switching controller 52 are input to the energization controller 60.
[0017]
The energization controller 60 outputs upper energization control signals N1, N2, N3 and lower energization control signals M1, M2, M3 in response to the detection pulse signal FG of the position detector 30, and outputs an upper power transistor of the power supply 20. 21, 22 and 23 and the lower power transistors 25, 26 and 27. The upper energization control signals N1, N2, and N3 include the main PWM signal Wp of the switching device 50, and the lower energization control signals M1, M2, and M3 include the auxiliary PWM signal Ws of the switching device 50. . The upper power transistors 21, 22, 23 perform a high-frequency switching operation (PWM operation) according to the upper energization control signals N1, N2, N3 (main PWM signal Wp), and the lower energization control signals M1, M2, M3 (auxiliary PWM signal Ws). ), The lower power transistors 25, 26, 27 perform a full-on operation, and the lower power transistor in the same phase as the upper power transistor performs a high-frequency switching operation (synchronous rectification operation) in a complementary manner. More specifically, when energization control from the coil 11 to the coil 12 is performed, the upper power transistor 21 performs a high-frequency switching operation (PWM operation) by the upper energization control signal N1 (main PWM signal Wp), and The power transistor 26 performs a full-on operation according to the lower energization control signal M2, and the lower power transistor 25 performs a high-frequency switching operation (synchronous rectification operation) according to the lower energization control signal M3 (auxiliary PWM signal Ws).
[0018]
When the upper power transistor 21 is turned on by the main PWM signal Wp, the upper power transistor 21 supplies a positive current from the positive terminal of the DC power supply 5 to the coil 11, and the lower power transistor 26 supplies a negative current of the DC power supply 5. The negative terminal side current is supplied to the coil 12 from the side terminal. Next, when the main PWM signal Wp is turned off, the positive current flowing through the coil 11 tends to continue to flow due to the inductance action of the coil 11. Therefore, a positive current is supplied by the lower power diode 25d of the same phase. After the dead time Ta has elapsed since the main PWM signal Wp was turned off, when the auxiliary PWM signal Ws is turned on, that is, when the lower power transistor 25 is turned on, a positive current is supplied to the coil 11 via the lower power transistor 25. . By operating in this manner, power loss due to the lower power diode 25d can be reduced (synchronous rectification operation). Thus, the energization controller 60 performs the PWM operation and the synchronous rectification operation. Further, the energization controller 60 outputs detection window signals WIN1 to WIN6 in response to the detection pulse signal FG of the position detector 30. The detection window signals WIN1 to WIN6 are input to the detection pulse generator 32 of the position detector 30. The detection window signals WIN1 to WIN6 correspond to the detection of the rising and falling zero crossings of the induced voltage of the three-phase coil. For example, the detection window signal WIN1 is a detection window for detecting the rising zero crossing of the induced voltage of the coil 11. The details of the detection operation will be described later.
[0019]
As described above, the position detector 30 detects the positions of the disk 1 and the rotor 10, and the energization controller 60 responds to the detection pulse signal FG of the position detector 30 so that the upper power transistors 21 and 22 of the power supply 20. , 23 and the lower power transistors 25, 26, 27 are output as upper power control signals N1, N2, N3 and lower power control signals M1, M2, M3. The power supply 20 is turned on and off by the upper energization control signals N1, N2, N3 and the lower energization control signals M1, M2, M3 to supply electric power to the three-phase coils 11, 12, and 13. The command device 40 detects the actual rotation speed of the disk 1 and the rotor 10 from the detection pulse signal FG of the position detector 30 and outputs a speed command signal Ac corresponding to the difference from the target rotation speed. The switching actuator 50 operates the upper power transistors 21, 22, 23 and the lower power transistors 25, 26, 27 of the power supply 20 in PWM operation (synchronous rectification operation) in response to the speed command signal Ac of the command device 40. It outputs a PWM signal Wp and an auxiliary PWM signal Ws. Thus, the speed control is performed by driving the disk 1 and the rotor 10 without the PWM sensor.
[0020]
Next, the position detection operation of the position detector 30 will be described in detail. FIG. 4 is a circuit diagram showing a specific configuration of the voltage comparator 31 in the position detector 30. The voltage comparator 31 includes input resistors 121, 122, 123, and 124 and voltage comparison circuits 125, 126, and 127. In the voltage comparator 31, the three-phase terminal voltages V1, V2, and V3 generated at one ends of the three-phase coils 11, 12, and 13, and the midpoint voltage Vc commonly connected, are input via input resistors 121, 122, 123, and 124. Are input to the voltage comparison circuits 125, 126, and 127, respectively. The voltage comparison circuits 125, 126, and 127 directly compare the three-phase terminal voltages V1, V2, and V3 with the midpoint voltage Vc, respectively, and output voltage comparison signals C1, C2, and C3 corresponding to the comparison results. As a result, zero-cross detection of the induced voltages of the three-phase coils 11, 12, and 13 is performed. Basically, the voltage comparison signals C1, C2, and C3 are pulse signals having edges at the zero crossings of the induced voltages of the three-phase coils 11, 12, and 13. The three-phase terminal voltages V1, V2, and V3 and the midpoint voltage Vc are used. Since the direct comparison is performed, switching noise accompanying the high-frequency switching operation by the PWM operation is superimposed on the comparison result in addition to the zero-cross information. The voltage comparison signals C1, C2, and C3 thus formed are input to the detection pulse generator 32.
In the disk device of the first embodiment, the voltage comparison is performed using the midpoint voltage Vc in which one ends of the three-phase coils 11, 12, and 13 are commonly connected. May be configured such that the midpoint voltage Vc is created in a simulated manner from the terminal voltages V1, V2, and V3.
[0021]
Hereinafter, a specific configuration of the noise removal pulse generator 33 in the position detector 30 will be described. FIG. 5 is a block circuit diagram showing a specific configuration of the noise removal pulse generator 33. FIG. 6 is a waveform diagram showing a relationship between signal waveforms in the noise removal pulse generator 33.
The noise removal pulse creator 33 includes a first delay pulse creator 130, a second delay pulse creator 131, a selector circuit 132, and a plurality of logic gates 133 to 139. The basic PWM signal Wb of the switching controller 52 is input to the first delay pulse generator 130 and the second delay pulse generator 131, and the first delay pulse signal Wx delayed by Tx and Ty and the second delay pulse The pulse signal Wy is output. The basic PWM signal Wb and the first delay pulse signal Wx are input to the logic gate 133 and are subjected to exclusive OR inversion and synthesis. The exclusive OR-inverted and combined signal at the logic gate 133 is combined with the inverted output signal of the basic PWM signal Wb from the logic gate 134 at the logic gate 135. The output signal of the logic gate 135 becomes the PWM on-side noise removal signal Wmon.
[0022]
Further, the basic PWM signal Wb and the second delay pulse signal Wy are input to the logic gate 136 and are subjected to exclusive OR inversion and synthesis. The signal that has been subjected to exclusive OR inversion and synthesis at the logic gate 136 is ORed at the logic gate 137 with the basic PWM signal Wb. The output signal of the logic gate 137 becomes the PWM off-side noise removal signal Wmoff. The logic gate 138 performs a logical product synthesis of the basic PWM signal Wb and the PWM on-side noise removal signal Wmon, and outputs a first noise removal signal Wm1. The logic gate 139 performs a logical product synthesis of the PWM on-side noise removal signal Wmon and the PWM off-side noise removal signal Wmoff, and outputs a second noise removal signal Wm2.
In the following description, performing position detection using the first noise removal signal Wm1 is referred to as first position detection, and performing position detection using the second noise removal signal Wm2 is referred to as second position detection. Say.
The selector circuit 132 of the noise elimination pulse generator 33 selects one of the first noise elimination signal Wm1 and the second noise elimination signal Wm2 based on the position detection switching signal DS of the position detection switch 34, and outputs the noise elimination signal. Wm is output. The noise removal signal Wm is input to the detection pulse generator 32.
[0023]
The PWM on-side noise elimination signal Wmon output from the logic gate 135 is a signal for eliminating noise generated when the PWM is on, while the PWM off-side noise elimination signal Wmoff is a signal for eliminating noise generated when the PWM is off. . The delay times Tx and Ty are times for removing switching noise generated when the PWM is on and when the PWM is off, respectively (noise removal time). In the disk device of the first embodiment, the noise removal times Tx and Ty of the PWM on-side noise removal signal Wmon and the PWM off-side noise removal signal Wmoff can be independently set. However, the time setting method in the present invention is not limited to such a setting method. However, each of the noise removal times Tx and Ty must be longer than the dead time Ta of the main PWM signal Wp and the auxiliary PWM signal Ws (Tx> Ta, Ty> Ta).
[0024]
The first noise elimination signal Wm1 output from the logic gate 138 is a logical product of the PWM on-side noise elimination signal Wmon and the basic PWM signal Wb. The “H” level section of the first noise elimination signal Wm1 is a section where the position of the rotor 10 can be detected (the “L” level section is a noise elimination section). That is, in the first position detection that performs position detection using the first noise removal signal Wm1, detection is not performed on the PWM off side, and the position is detected in a section obtained by excluding the PWM on side noise removal section Tx from the PWM on section. The detection is performed (only the PWM ON side is detected).
On the other hand, the second noise elimination signal Wm2 output from the logic gate 139 is a logical product of the PWM on-side noise elimination signal Wmon and the PWM off-side noise elimination signal Wmoff. The “H” level section of the second noise elimination signal Wm2 is a section where the position of the rotor 10 can be detected (the “L” level section is a noise elimination section). That is, in the second position detection that performs position detection using the second noise removal signal Wm2, position detection is performed in all sections except the PWM on-side noise removal section Tx and the PWM off-side noise removal section Ty (PWM ON / OFF both sides detection).
[0025]
Hereinafter, a specific configuration of the detection pulse generator 32 in the position detector 30 will be described. FIG. 7 is a block diagram showing a specific configuration of the detection pulse generator 32 of the position detector 30. As shown in FIG. 7, the detection pulse generator 32 includes an inversion circuit 140, a noise removal circuit 141, a detection circuit 142, and a synthesis circuit 143. The inversion circuit 140 receives the voltage comparison signals C1, C2, and C3 of the voltage comparator 31 of the position detector 30, and outputs inverted voltage comparison signals C1R, C2R, and C3R, respectively. The noise elimination circuit 141 converts the switching noise accompanying the high-frequency switching operation superimposed on the voltage comparison signals 1, C2, C3 and the inverted voltage comparison signals C1R, C2R, C3R from the noise elimination pulse generator 33 of the position detector 30. Is removed by the noise removal signal Wm. After removing the noise, the noise removing circuit 141 outputs the noise-removed voltage comparison signals C1A, C2A, and C3A and the noise-removed inverted voltage comparison signals C1RA, C2RA, and C3RA. The detection circuit 142 selects a detection phase based on the detection window signals WIN1 to WIN6 of the energization controller 60, performs zero-cross detection of rising and falling of induced voltages of the three-phase coils 11, 12, and 13, and detects zero-cross detection signals Dt1 to Dt6. Is output. The combining circuit 143 combines the input zero-cross detection signals Dt1 to Dt6 and outputs a detection pulse signal FG. In other words, the detection pulse signal FG is a pulse signal having edges at zero crossings of the rising and falling of the induced voltage of each phase (at intervals of 60 electrical degrees).
[0026]
Hereinafter, the noise removal and detection operations will be described in detail with reference to the waveform diagram of FIG. The waveform diagram of FIG. 8 exemplifies detection of a rising zero cross of the induced voltage Vb1 of the coil 11.
The voltage comparison signal C1 is the result of directly comparing the terminal voltage V1 of the coil 11 and the midpoint voltage Vc in the voltage comparison circuit 125 of the voltage comparator 31. In addition to the zero-cross information of the induced voltage, switching noise accompanying the high-frequency switching operation is superimposed on the voltage comparison signal C1 (in FIG. 8, for example, shown in a region surrounded by A). Therefore, in the noise removal circuit 141 of the detection pulse creator 32, removal of high-frequency switching noise superimposed on the voltage comparison signal C1 by logic synthesis with the noise elimination signal Wm of the noise elimination pulse creator 33 (for example, in FIG. (Shown in a surrounding area) to output a voltage comparison signal C1A after noise removal. The noise-removed voltage comparison signal C <b> 1 </ b> A from which the high-frequency switching noise has been removed is a signal including zero-cross information of the induced voltage of the coil 11.
[0027]
Next, in the detection circuit 142 of the detection pulse generator 32, the rising zero-crossing of the induced voltage Vb1 of the coil 11 is detected by the voltage comparison signal C1A after noise removal and the detection window signal WIN1 for detecting the rising zero-crossing of the induced voltage Vb1 of the coil 11. I do. In FIG. 8, the detection result is indicated by a zero cross detection signal Dt1. The detection circuit 142 is composed of, for example, a D flip-flop circuit. The noise-removed voltage comparison signal C1A is input to a clock terminal of the D flip-flop, and its reset terminal is used for detecting a rising zero crossing of the induced voltage Vb1 of the coil 11. The detection window signal WIN1 is input. By detecting the rising edge of the noise-removed voltage comparison signal C1A in the detection window, the rising zero-cross of the induced voltage Vb1 of the coil 11 is detected (the position indicated by the arrow C in FIG. 8). Thus, the detection circuit 142 outputs the zero cross detection signals Dt1 to Dt6 corresponding to the detection window signals WIN1 to WIN6. A signal obtained by synthesizing the zero-cross detection signals Dt1 to Dt6 in the synthesizing circuit 143 becomes a detection pulse signal FG.
[0028]
However, in the disk device of the first embodiment, the detection result includes a quantization error due to the noise removal signal Wm, as described below. This differs depending on whether the zero crossing of the induced voltage Vb1 of the coil 11 is in the “H” level section (the section where the position of the rotor 10 can be detected) or the “L” level section (the noise removal section) of the noise removal signal Wm. . In the former case, since the zero crossing of the induced voltage Vb1 of the coil 11 is not within the noise removal section, the zero crossing can be detected almost accurately as described above. However, in the latter case, since the rising zero cross of the induced voltage Vb1 of the coil 11 is within the noise removal section, the noise removal operation is performed in that section (see the waveform diagram of FIG. 9). In this case, since the original zero-crossing of the induced voltage Vb1 of the coil 11 is noise-removed by the noise-removal signal Wm, it is not the position actually generated by the arrow C in FIG. 9 but the position shown by the arrow D in FIG. Is detected as a rising zero cross of the induced voltage Vb1 of the coil 11. That is, when the rising zero cross is within the noise elimination section of the noise elimination signal Wm, there is a problem that the zero cross detection result includes a quantization error due to the noise elimination signal Wm.
[0029]
Hereinafter, the first position detection and the second position detection in the position detector 30 will be described.
The first position detection and the second position detection are switched by the position detection switching signal DS of the position detection switch 34. In the disk device of the first embodiment that performs the PWM operation (synchronous rectification operation), the terminal voltages V1, V2, and V3 of the three-phase coils 11, 12, and 13 are directly compared with the midpoint voltage Vc to determine the induced voltage of the coil. Zero cross detection is performed. Therefore, the terminal voltages V1, V2, V3 and the midpoint voltage Vc of the three-phase coils 11, 12, 13 perform the high-frequency switching operation, and the operation of the terminal voltage on the PWM off side becomes unstable. Therefore, when the second position detection is performed so that the zero-cross detection can be detected on the PWM on side and the PWM off side, the second noise generated from the PWM on side noise removal signal Wmon and the PWM off side noise removal signal Wmoff Position detection is performed using the removal signal Wm2. Therefore, the substantially detectable section is a section obtained by removing the PWM on-side noise removal section Tx from the PWM on section, and a section obtained by removing the PWM off side noise removal section Ty from the PWM off section. That is, the detectable section exists on both the PWM-on side and the PWM-off side, and in the disk device of the first embodiment which performs the PWM operation (synchronous rectification operation), the PWM-off side (during the synchronous rectification operation). Is more likely to be erroneously detected in zero cross detection. As described above, in the disk device according to the first embodiment, the detection includes a quantization error, but the erroneous detection of the zero-cross detection is more dominant in the fluctuation of the detection pulse signal FG. Therefore, in the disk device of the first embodiment in which the speed control is performed using the detection pulse signal FG, the fluctuation of the detection pulse signal FG causes the speed fluctuation. That is, when the disk device according to the first embodiment is used in, for example, a hard disk device or the like, it has an adverse effect on jitter in steady rotation, which is an important item. Deterioration of jitter has a high possibility of causing an error at the time of read / write, and deterioration of jitter should be suppressed.
[0030]
On the other hand, when performing the first position detection in which the zero-cross detection on the PWM off side is prohibited in order to eliminate the erroneous detection on the PWM off side, the first position generated from the PWM on side noise removal signal Wmon and the basic PWM signal Wb is generated. Position detection is performed using the noise removal signal Wm1. Therefore, the detection operation is not performed on the PWM off side, and the substantially detectable section is only the section obtained by excluding the PWM on side noise removal section Tx from the PWM on section. Therefore, in the first position detection, erroneous detection in zero cross detection on the PWM off side (synchronous rectification operation) is eliminated. However, since the PWM off side is entirely used as the noise removal section, an increase in the quantization error due to the noise removal section being longer than the second position detection cannot be avoided. However, when compared with the erroneous detection in the zero-cross detection on the PWM off side by the PWM operation (synchronous rectification operation), the fluctuation of the detection pulse signal FG due to the erroneous detection is larger than the fluctuation of the detection pulse signal FG due to the quantization error. . Therefore, in the case of a hard disk device or the like in which jitter is regarded as a problem, erroneous detection on the PWM off side is eliminated by performing the first position detection during steady rotation, and the fluctuation of the detection pulse signal FG is small and the speed fluctuation is also small. , And low-jitter rotational drive.
In the disk device 1 according to the embodiment, the detection of only the PWM on side where the zero cross detection on the PWM off side is prohibited is set as the first position detection, and the PWM on / off for performing the zero cross detection on both the PWM on side and the PWM off side. The two-sided detection is used as the second position detection, and the switching between the two position detections is performed by the position detection switching signal DS of the position detection switch 34.
[0031]
As described above, by performing the position detection by switching to the first position detection by the position detection switching signal DS of the position detection switch 34, erroneous detection on the PWM off side is eliminated, and deterioration of jitter is suppressed. However, when sensorless driving is performed in the first position detection, there is a problem that speed control is not stable. This is a problem that occurs in a transitional state from start-up to a steady rotation, and cannot be pulled into a sensorless state due to detection failure.
FIG. 10 is a graph showing the relationship between the time from the start of startup to the steady rotation and the number of rotations. After the start of the start, it is an acceleration section and the number of rotations increases with time (the area indicated by A in FIG. 10). Near the steady number of rotations, overshoot occurs due to the servo constant of the speed control system and the like (FIG. 10). Then, constant-speed rotation is performed at a steady rotation speed (region indicated by C in FIG. 10). In the disk device of the first embodiment, as described above, the on-duty of the basic PWM signal Wb of the switching operation device 50 is changed by the speed command signal Ac of the command device 40, and the speed control is performed on the disk 1 and the rotor 10. Is going.
[0032]
FIG. 11 is a waveform diagram showing the relationship between the on-duty of the basic PWM signal Wb and the first noise elimination signal Wm1 and the second noise elimination signal Wm2 in the regions A to C in FIG. FIG. 11A shows a waveform during the acceleration period immediately after the start of the start (region A in FIG. 10), and the on-duty of the PWM is 100% or a value close to 100%. FIG. 11B shows a waveform at the time of overshoot (region B in FIG. 10), and the on-duty of PWM becomes very small. FIG. 11C shows a waveform at the time of steady rotation (region C in FIG. 10), and the PWM on-duty has a substantially constant value.
[0033]
In each state, when the first noise elimination signal Wm1 and the second noise elimination signal Wm2 are compared, the “H” level section of both signals is a detectable section, and when the second position detection is used, In any situation of the areas A to C in FIG. 10, detectable sections exist on the PWM on side and the PWM off side from FIGS. 11A to 11C. However, when the first position detection is used, only the PWM-on side is detected, so that there is a case where there is no detectable section as shown in FIG. 11B. That is, when the first position detection is used, zero-cross detection cannot be performed during the overshoot (the area B in FIG. 10) (the operation becomes sensorless), and the sensor cannot be drawn into the sensorless state. This is determined by the relationship between the PWM ON section during overshoot and the PWM ON side noise removal section Tx, and is a phenomenon that occurs when the PWM ON section during overshoot becomes smaller than the PWM ON side noise removal section Tx. . As described above, the first position detection is a detection method which is effective for eliminating the erroneous detection on the PWM off side and performing the low-rotation rotational drive. However, this detection method has a disadvantage that it cannot be used at all times from the viewpoint of speed control.
[0034]
Therefore, as shown in FIG. 10, the second position detection is used from the start to the time of steady rotation during the steady rotation, and if the first position detection is used during the steady rotation, the sensorless pull-in failure from the start to the steady rotation is failed. As a result, there is no step-out due to the above, stable speed control is possible, and erroneous detection on the PWM off side during normal rotation is eliminated, thereby enabling low jitter rotation drive.
[0035]
The switching between the first position detection and the second position detection is performed by the position detection switching signal DS of the position detection switch 34, and the position detection switching signal DS is set as in the disk device of the first embodiment. The signal is not limited to a signal that changes in response to the speed command signal Ac of the command device 40, but may be a configuration that is externally provided by a serial input from, for example, a personal computer or a DSP. As an example of the position detection switching timing, when the disk device according to the first embodiment is used in, for example, a ramp load type hard disk device, stable speed control is performed using the second position detection at the time of startup, and the read / write operation is performed ( If the timing of deviating from the lamp at the time of steady rotation) is taken as the position detection switching timing, low jitter rotation can be performed by the first position detection during the read / write operation (at steady rotation).
[0036]
Further, the position detection switching signal DS may be a signal that switches after a lapse of a predetermined time from the start of start or the start of acceleration / deceleration. In this case, the time setting must be determined from the relationship between the load condition, the set rotation speed, the servo constants of the speed control system, and the like. Stable speed control becomes possible by setting the transitional state up to the second position detection to the second position detection, and low jitter can be achieved by switching to the first position detection during steady rotation at a set number of rotations after a certain time has elapsed. Rotational drive becomes possible.
Further, even when the disk device of the first embodiment is used not only in a hard disk device but also in a DVD-RAM device or the like, stable speed control can be performed by setting a transient state other than the time of steady rotation as the second position detection. By switching to the first position detection at the time of steady rotation, rotation drive with little speed fluctuation and low jitter can be performed.
[0037]
As described above, in the disk device of the first embodiment, the position detection is performed by switching between the first position detection and the second position detection based on the position detection switching signal DS of the position detection switch 34. By performing the first position detection at the time of steady rotation, zero crossing due to unstable operation of the terminal voltages V1, V2, V3 and the midpoint voltage Vc on the PWM off side due to the PWM operation (synchronous rectification operation) of the position detector 30 is performed. Erroneous detection is eliminated. That is, the fluctuation of the detection pulse signal FG is reduced and the fluctuation of the speed is reduced, so that the rotation drive with low jitter can be realized. Further, by setting the transitional state from the start to the steady rotation as the second position detection, it is possible to realize a disk device capable of performing stable speed control from the start to the steady rotation.
[0038]
Various modifications can be made to the specific configuration of the first embodiment. For example, the number of phases of the coil is not limited to three, but may be plural, and the number of magnetic poles of the rotor is not limited to two but may be multi. Further, each phase coil is not limited to the star connection but may be a delta connection. The energization angle of the motor may be a wide-angle energization such as 120 degrees or 150 degrees. Further, the high-frequency switching operation may not be performed only by the upper power transistor, may be performed only by the lower power transistor, or may be performed by both the upper and lower power transistors. Further, the switching timing of the detection switching signal DS is not limited to the above, and the usage status of the first position detection and the second position detection is not limited to the above.
In addition, various changes can be made without changing the spirit of the present invention, and it goes without saying that such a configuration is included in the present invention.
[0039]
【The invention's effect】
As will be apparent from the detailed description of the embodiments, the present invention has the following effects.
The present invention can provide a motor that can eliminate erroneous detection on the PWM off side and can perform stable speed control from startup to steady rotation, and a disk device using the same.
According to the disk device of the present invention, by using the first position detection, the fluctuation of the detection pulse signal FG due to erroneous detection can be reduced. Therefore, when the speed control is performed using the detection pulse signal FG, the speed fluctuation can be reduced and the rotation drive with low jitter can be realized. Further, according to the present invention, by performing the position detection by switching the first position detection and the second position detection by the position detection switching signal DS, it is possible to perform stable speed control from the start to the steady rotation. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration according to Embodiment 1 of the present invention.
FIG. 2 is a block diagram showing a basic configuration of a switching operation device 50 according to Embodiment 1 of the present invention.
FIG. 3 is a waveform chart showing operation timing of each unit of the switching operation device 50 of FIG. 2 according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing a basic configuration of a voltage comparator 31 of the position detector 30 according to Embodiment 1 of the present invention.
FIG. 5 is a block diagram showing a basic configuration of a noise removal pulse generator 33 of the position detector 30 according to Embodiment 1 of the present invention.
FIG. 6 is a waveform chart showing operation timing of each unit of the noise removal pulse generator 33 of FIG. 5 according to the first embodiment of the present invention.
FIG. 7 is a block diagram showing a basic configuration of a detection pulse generator 32 of the position detector 30 according to Embodiment 1 of the present invention.
FIG. 8 is a waveform chart showing operation timing of each unit of the detection pulse generator 32 of the position detector 30 according to Embodiment 1 of the present invention.
FIG. 9 is a waveform chart showing another operation timing of each unit of the detection pulse generator 32 of the position detector 30 according to Embodiment 1 of the present invention.
FIG. 10 is a diagram illustrating a relationship between a time from a start to a steady rotation and a rotation speed according to the first embodiment of the present invention.
11 is a waveform chart showing a relationship between a basic PWM signal Wb, a first noise elimination signal Wm1, and a second noise elimination signal Wm2 in the states A to C of FIG. 10 according to the first embodiment of the present invention. is there.
FIG. 12 is a block diagram showing an overall configuration of a conventional motor.
[Explanation of symbols]
1 disk
2 head
3 Information processor
5 DC power supply
10 rotor
11, 12, 13 coils
20 Power supply
21,22,23 Upper power transistor
25,26,27 Lower power transistor
30 Position detector
31 Voltage comparator
32 Detector pulse generator
33 Noise removal pulse generator
34 Position detection switch
40 commander
50 Switching actuator
51 Current detector
52 Switching controller
60 Current controller

Claims (16)

A rotor having a permanent magnet;
A multi-phase coil arranged on the stator,
DC power supply means serving as a power supply source,
First switching means for supplying power from one terminal side of the DC power supply means to one end of the multi-phase coil, and power supply from the other terminal side of the DC power supply means to one end of the multi-phase coil. Power supply means including second switching means for performing
Command means for outputting a speed command signal;
Switching operation means for outputting a switching pulse signal for causing at least one of the first switching means and the second switching means of the power supply means to perform a high-frequency switching operation in response to the speed command signal;
Position detection switching means for outputting a position detection switching signal in response to a speed command signal of the command means, and detecting a rotation position of the rotor from terminal voltages of the coils of the plurality of phases to output a detection signal Means,
An energization control unit that controls energization of the power supply unit in response to a detection signal of the position detection unit,
The position detection means performs first position detection for detecting the position of the rotor in an ON period of the switching pulse signal, and second position detection for detecting the position of the rotor in both ON and OFF periods of the switching pulse signal. 2. The motor according to claim 2, wherein the position detection is switched by the position detection switching signal and executed. The motor according to claim 1, wherein the command unit is configured to output the speed command signal in response to a detection signal of the position detection unit. In response to the switching pulse signal, the power supply means causes the first switching means to perform an on / off high-frequency switching operation, and complements the second switching means in the same phase as the first switching means. The motor according to claim 1, wherein the motor is configured to perform an off-on high-frequency switching operation. The position detection means includes a voltage comparison means for substantially comparing a terminal voltage of the multi-phase coil with a common voltage of the multi-phase coil to output a comparison signal, and a noise removal responsive to the switching pulse signal. A noise removal signal generating means for outputting a signal; and a detection signal generating means for outputting a detection signal by performing a logic gate process on a comparison signal of the voltage comparison means with the noise removal signal, wherein the first position The detection is performed by disabling a comparison signal of the voltage comparison means during a first predetermined time including a time point when the switching pulse signal changes from off to on and an off section of the switching pulse, and performing the second position detection. The detection includes the first predetermined time including a time point when the switching pulse signal changes from off to on and a second point including a time point when the switching pulse signal changes from on to off. Motor according to any one of claims 1 to 3, characterized in that configured to detect the position by disabling a comparison signal of said voltage comparison means at a time. 5. The position detection switching unit according to claim 1, wherein the position detection switching unit is configured to output a position detection switching signal so as to perform a first position detection when the rotor rotates at a constant speed. 6. Motor according to one of the preceding claims. 5. The position detection switching unit according to claim 1, wherein the position detection switching unit is configured to output a position detection switching signal to cause the second position detection to be performed from a start to a constant speed rotation. 6. A motor according to any one of the preceding claims. The position detection switching means is configured to perform a second position detection from a start to a constant speed rotation, and to output a position detection switching signal to perform the first position detection at the constant speed rotation. The motor according to any one of claims 1 to 4, wherein: Head means for reproducing a signal from a disk or for recording a signal on a disk;
An information processing means for processing the output signal of the head means to output a reproduction information signal, or for processing the recording information signal to output to the head means;
A rotor having a permanent magnet that directly drives the disk to rotate,
A multi-phase coil arranged on the stator,
DC power supply means serving as a power supply source,
First switching means for supplying power from one terminal side of the DC power supply means to one end of the multi-phase coil, and power supply from the other terminal side of the DC power supply means to one end of the multi-phase coil. Power supply means including second switching means for performing
Command means for outputting a speed command signal;
Switching operation means for outputting a switching pulse signal for causing at least one of the first switching means and the second switching means of the power supply means to perform a high-frequency switching operation in response to the speed command signal;
Position detection switching means for outputting a position detection switching signal in response to a speed command signal of the command means, and detecting a rotation position of the rotor from terminal voltages of the coils of the plurality of phases to output a detection signal Means,
A power supply control means for controlling power supply of the power supply means in response to a detection signal of the position detection means,
The position detection means performs first position detection for detecting the position of the rotor in an ON period of the switching pulse signal, and second position detection for detecting the position of the rotor in both ON and OFF periods of the switching pulse signal. 2. The disk device according to claim 1, wherein the position detection is switched by the position detection switching signal and executed. 9. The disk device according to claim 8, wherein the command unit is configured to output the speed command signal in response to a detection signal of the position detection unit. In response to the switching pulse signal, the power supply means causes the first switching means to perform an on / off high-frequency switching operation, and complements the second switching means in the same phase as the first switching means. The disk device according to claim 8, wherein the disk device is configured to perform an off-on high-frequency switching operation. The position detection means includes: a voltage comparison means for substantially comparing a terminal voltage of the multi-phase coil with a common voltage of the multi-phase coil to output a comparison signal; and a noise removal responsive to the switching pulse signal. A noise removal signal generating unit that outputs a signal, and a detection signal generating unit that outputs a detection signal by performing a logic gate process on the comparison signal of the voltage comparison unit with the noise removal signal,
The first position detection performs a position detection by invalidating a comparison signal of the voltage comparison means in a first predetermined time including a time point when the switching pulse signal changes from off to on and an off section of the switching pulse, The second position detection is performed by comparing the comparison signal of the voltage comparison means during a first predetermined time including a time when the switching pulse signal changes from off to on and a second predetermined time including a time when the switching pulse signal changes from on to off. The disk device according to any one of claims 8 to 10, wherein the disk device is configured to perform position detection with invalidation. 12. The apparatus according to claim 8, wherein the position detection switching means is configured to output a position detection switching signal so as to perform a first position detection when the rotor rotates at a constant speed. The disk device according to claim 1. 12. The position detection switching device according to claim 8, wherein the position detection switching unit is configured to output a position detection switching signal so as to perform the second position detection from a start to a constant speed rotation. The disk device according to claim 1. The position detection switching means is configured to perform a second position detection from a start to a constant speed rotation, and to output a position detection switching signal to perform the first position detection at the constant speed rotation. The disk device according to any one of claims 8 to 11, characterized in that: The position detection switching means is configured to output a position detection switching signal so as to perform signal reproduction from the disk or perform first position detection when performing signal recording on the disk. The disk device according to any one of claims 8 to 11, wherein: The position detection switching means performs a second position detection at the time of startup and reproduces a signal from the disk, or performs a first position detection when performing a signal recording on the disk. The disk device according to any one of claims 8 to 11, wherein the disk device is configured to output the disk drive.

Images