JP2002374690A - Motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motor that has small electric power consumption and is high in reliability. SOLUTION: In a PWM-driven motor of a drive current peak detecting type, a switching control means includes a means which controls the turn on/off of a power transistor includes a trigger means, which generates timing to turn on either one or both of first and second power amplifying means at each specified time, a comparison means which generates the timing to turn off either one or both of the power amplifying means, by comparing the output signal of a current detecting means with a command signal, and a forcible turn-on means which decides the timing to forcibly turn on either one or both of the power amplifying means for a fixed period of time in response to the output signal of the trigger means. The forcible turn-on means switches the forcible turn-on time, in response to the output signal of a time switching means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor for supplying a current supplied to a multi-phase coil load by electronically switching the current through a plurality of transistors.

[0002]

2. Description of the Related Art In recent years, a brushless motor has been used as a spindle motor for a hard disk drive or the like, which uses a plurality of transistors to switch a current path and supply power to a motor coil.

FIG. 25 shows a conventional motor, and its operation will be briefly described. The rotor 1001 has a field portion made of a permanent magnet, and coils 1002, 1003, and 1004
Generates rotational force by interaction with Position detector 10
05 detects a terminal voltage of the motor coils 1002, 1003, and 1004, and detects a position detection pulse F corresponding to the detection result.
Output g. The commutation controller 1006 outputs the position detection pulse F
g, upper-side energization control signals EU1, EU2, and
It generates EU3 and lower energization control signals EL1, EL2, EL3.

The commander 1011 compares the position detection pulse Fg with the target rotation speed, and determines whether the coils 1002, 1003, 10
A command signal Ad for controlling the power supplied to the power supply circuit 04 is output. The power controller 1012 receives the command signal Ad and the coil 100
For controlling the gates of the upper power transistors 1018, 1019, and 1020 and the lower power transistors 1015, 1016, and 1017 in an analog manner based on the output signal Ag from the current detector 1013 that detects the current flowing through 2,1003 and 1004. The gate control signal As is output.

[0005] The drive controller 1007 receives an upper energization control signal E
U1, EU2, EU3 and lower energization control signals EL1, EL
, EL3, the upper drive signals EU1, EU2, EU3 responsive to the gate control signal As, and the lower drive signal EL
1, EL2 and EL3 are output. The upper power transistors 1018, 1019 and 1020 and the lower power transistors 1015, 1016 and 1017 are connected to the upper drive signal EU.
1, EU2, EU3 and lower drive signals EL1, EL2,
Coil 1002, 1003, 1004 in response to EL3
Open / close the current path.

[0006]

However, the conventional configuration has the following problems. In the conventional configuration, the power transistor has a large power loss, and the power efficiency of the motor is extremely poor. Upper power transistor 10
18, 1019, 1020 and lower power transistor 1
Since the voltage between the gate and the source of 015, 1016, and 1017 is controlled in an analog manner, the residual voltage of each power transistor is large, and a power loss indicated by the product of the residual voltage and the current supplied to the coil has occurred. .

In order to solve such a problem, it is conceivable to operate the power transistor by PWM. However, when the power transistor performs the PWM operation, a large switching noise generated at the time of switching makes it impossible to accurately detect a position and lowers a rotation jitter. Therefore, the power transistor is used for a hard disk device which requires high-precision signal recording and reproduction. It was difficult.

An object of the present invention is to solve the above problems and to provide a highly reliable motor with low power consumption.

[0009]

In order to achieve the above object, a motor according to the present invention comprises a rotor having permanent magnets, a plurality of phase coils, a DC power supply as a power supply source, and the DC power supply. Each including a first power transistor forming a current path between one terminal side of the
Q (Q is a positive number of 3 or more) including first power amplifying means and second power transistors each forming a current path between the other terminal of the DC power supply means and the coil.
Second power amplifying means, energization control means for controlling energization of the first power amplifying means and the second power amplifying means, position detecting means for detecting a rotational position of the rotor, Command means for outputting a command signal for controlling power supply to the coil based on the output pulse signal of the detection means; current detection means for outputting a signal in response to a current supplied by the DC power supply means; Switching control means for turning on or off one or both of the first power amplifying means and the Q second power amplifying means; and one of the first power amplifying means and the second power amplifying means; Time switching means for switching a time for forcibly turning on both of them for a predetermined period, wherein the switching control means is configured to switch the first power amplification means or the first power amplification means every predetermined time. A trigger for generating a timing for turning on one or both of the second power amplifying means, an output signal of the current detecting means and the command signal are compared, and the first power amplifying means and the second power amplifying means are compared. Comparing means for generating a timing for turning off one or both of the power amplifying means, and keeping one or both of the first power amplifying means and the second power amplifying means constant in response to the output signal of the trigger means And a forced-on generating means for determining a timing of forcibly turning on the power supply for a period, wherein the forced-on generating means switches the time of the forced on in response to an output signal of the time switching means.

Accordingly, at least one of the first power transistor and the second power transistor performs a high-frequency switching operation, so that the power loss of the power transistor is extremely small. In addition, since stable high-frequency switching can be realized even when various conditions such as the number of revolutions are changed by the forced ON generation unit and the time switching unit, position detection in sensorless driving is also stabilized. Therefore, a motor suitable for a hard disk drive that requires high-precision jitter performance can be realized.

According to another aspect of the present invention, there is provided a motor including a rotor having permanent magnets, a coil having a plurality of phases, a DC power supply serving as a power supply source, and a terminal connected to one terminal of the DC power supply and the coil. Q (where Q is a positive number of 3 or more) first power amplifying means each including a first power transistor forming a current path, and a current path between the other terminal side of the DC power supply means and the coil. Q second power amplifying means each including a second power transistor to be formed, energization control means for controlling energization of the first power amplifying means and the second power amplifying means, and rotation of the rotor Position detecting means for detecting a position; command means for outputting a command signal for controlling power supply to the coil based on an output pulse signal from the position detecting means; Current detecting means for outputting a signal; switching control means for turning on or off one or both of the Q first power amplifying means and the Q second power amplifying means; Time switching means for switching a time for forcibly turning off one or both of the amplifying means and the second power amplifying means for a predetermined period, wherein the switching control means comprises a first power amplifying means for every predetermined time. Alternatively, a trigger means for generating a timing for turning on one or both of the second power amplifying means, an output signal of the current detecting means and the command signal are compared, and the first power amplifying means and the second Comparing means for generating a timing for turning off one or both of the two power amplifying means, and the first means in response to an output signal of the trigger means. And a forced-off generating means for determining a timing for forcibly turning off one or both of the power amplifying means and the second power amplifying means for a certain period of time. Switches the time to forcibly turn off in response to a signal.

Accordingly, since at least one of the first power transistor and the second power transistor performs the high-frequency switching operation, the power loss of the power transistor is extremely small. Further, since stable high-frequency switching can be realized even when various conditions such as the number of revolutions are changed by the forced off generating means and the time switching means, the position detection in sensorless driving is also stabilized. Therefore, a motor suitable for a hard disk drive that requires high-precision jitter performance can be realized.

A motor according to yet another aspect of the present invention includes a rotor having permanent magnets, a coil having a plurality of phases, DC power supply means serving as a power supply source, one terminal side of the DC power supply means and the coil. Q (Q is a positive number equal to or more than 3) first power amplifying means each including a first power transistor forming a current path, and a current path between the other terminal side of the DC power supply means and the coil Q second power amplifying means each including a second power transistor forming the first power amplifying means, energization controlling means for controlling energization of the first power amplifying means and the second power amplifying means, Position detecting means for detecting a rotational position, command means for outputting a command signal for controlling power supply to the coil based on an output pulse signal of the position detecting means, and an energizing current supplied by the DC power supply means Current detecting means for outputting a driven signal; switching control means for turning on or off one or both of the Q first power amplifying means and the Q second power amplifying means; And a time switching means for switching between a time for forcibly turning on one or both of the Q second power amplifying means for a certain period of time and a time for forcibly turning off the power for a certain period of time. Means for generating a timing for turning on one or both of the first power amplifying means and the second power amplifying means at predetermined time intervals; an output signal of the current detecting means and the command signal; Comparing means for generating a timing for turning off one or both of the first power amplifying means and the second power amplifying means; Forcibly turning on one or both of the first power amplifying means and the second power amplifying means for a fixed period in response to an output signal of the power means; A forced-off generating means for determining a timing of turning off, wherein the forced-on generating means and the forced-off generating means determine a time for forcibly turning on and a time for forcibly turning off in response to an output signal of the time switching means. Switch.

Thus, at least one of the first power transistor and the second power transistor performs a high-frequency switching operation, so that the power loss of the power transistor is extremely small. Further, even if various conditions such as the number of revolutions are changed by the forcible on creating means, the forcibly off creating means and the time switching means, stable high-frequency switching can be realized, so that the position detection in sensorless driving is also stabilized. Therefore, a motor suitable for a hard disk drive that requires high-precision jitter performance can be realized. These and other configurations and operations will be described in detail in the description of the embodiments.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 14 show a motor according to Embodiment 1 of the present invention. FIG. 1 shows the overall configuration of the motor. The motor is for driving the hard disk,
The rotor 1 is provided with a field portion for generating a field magnetic flux of a plurality of poles by a magnetic flux generated by a permanent magnet,
3 and 4 are arranged on a stator which is a fixed body,
Are electrically displaced from each other by 120 degrees. The three-phase coils 2, 3, and 4 generate a three-phase magnetic flux by the three-phase drive currents I1, I2, and I3, generate a driving force by interaction with the rotor 1, and are attached to the rotor 1 and the rotor 1 to be digital. The disk 25 on which information is recorded rotates.

The DC power supply 30, which is a power supply source, has a negative terminal (-) at ground potential and supplies a required DC voltage to the positive terminal (+). The drive current outflow terminals of the three first power transistors 5, 6, and 7 are commonly connected to the negative terminal side of the DC power supply 30 via the current detector 11, and the drive current inflow of the first power transistor is performed. The terminal side is connected to the power supply terminal side of the coils 2, 3, and 4, respectively. The drive current inflow terminals of the three second power transistors 8, 9, and 10 are commonly connected to the positive terminal of the DC power supply 30, and the drive current outflow terminals of the second power transistors are connected to the coils 2, 3 respectively. , 4 are connected to the power supply terminals.

The first power transistors 5, 6, 7 respond to the first drive control signals HL1, HL2, HL3,
The power supply path between the negative terminal side of the DC power supply 30 and the power supply terminals of the coils 2, 3, and 4 is opened and closed. The first drive control signals HL1, HL2, HL3 are signals responsive to the commutation control switching signals ELs1, ELs2, ELs3. Commutation control switching signals ELs1, ELs
2, ELs3 are first commutation control signals EL1, EL2, E
A switching control signal Wb which is an output signal of the switching controller 14 is combined with L3. That is, the first power transistors 5, 6, and 7 perform a high-frequency switching operation. Details of the switching control signal Wb and the switching operation will be described later.

The second power transistor responds to the second drive control signals HU1, HU2, HU3, and supplies a DC power
The power supply path between the positive electrode terminal side of 0 and the power supply terminals of the coils 2, 3, and 4 is opened and closed. Second drive control signal HU
1, HU2, HU3 are the second commutation control signals EU1, EU
2, the signal corresponding to EU3. In addition, the first power transistor and the second power transistor use N-channel type field effect power transistors,
Parasitic diodes formed by being reversely connected to each field-effect power transistor are used as a first commutation power diode and a second commutation power diode, respectively.

The position detector 16 detects the rotational position of the rotor 1, and outputs a position detection pulse Fg corresponding to the detected position. FIG. 2 shows a specific configuration of the position detector 16. The position detector 16 includes a voltage detector 100 and a detection pulse generator 101. The voltage detector 100 is 3
It is composed of comparators 110, 111 and 112. Comparators 110, 111, and 112 are coils 2,
3, 4 terminal voltages V1, V2, V3 and common voltage V
n and a three-phase comparison signal b responsive to the comparison result.
1, b2 and b3 are output.

The detection pulse generating unit 101 includes a signal selector 1
13, a noise mask generator 114 and a noise remover 115
It is composed of The signal selector 113 selects one of the comparison pulse signals b1, b2, and b3 in accordance with the energization state of the coil by the first commutation control signals EL1, EL2, and EL3 and the second commutation control signals EU1, EU2, and EU3. Any one
The rising edge or the falling edge is selectively detected, and a synthesized pulse signal bs obtained by synthesizing the detected signals is output.

The noise mask generator 114 receives the switching control signal Wb and outputs a noise removal mask signal wm indicating a period in which the switching noise accompanying the high-frequency switching operation of the first power transistors 5, 6, 7 is ignored. To produce The noise remover 115 removes noise from the combined pulse signal bs including the switching noise using the noise removal mask signal wm, and outputs an accurate combined pulse signal Fg.

FIGS. 3A to 3E show waveforms for explaining the operation of the position detector 16. FIG. FIG. 3 (a), (b), (c)
Shows waveforms of three-phase comparison signals b1, b2, and b3 output from the comparators 110, 111, and 112, respectively. FIG. 3D shows a detection pulse signal bs obtained by selecting and combining the comparison pulse signals b1, b2, and b3 by the signal selector 113. FIG. 3E shows three-phase comparison signals b1, b2,
This is a detection pulse signal Fg obtained by synthesizing each edge of b3. The switching noise accompanying the high-frequency switching operation of turning on / off the first power transistors 5, 6, 7 is not shown.

FIGS. 4A to 4D show waveform examples for explaining the noise removing operation. FIG. 4A shows a waveform of a switching control signal Wb for causing the first power transistors 5, 6, 7 to perform a high-frequency switching operation. FIG. 4 (b)
Shows the waveform of the noise removal mask signal wm. The noise removal mask signal wm is a signal that becomes H level for a certain time tm each time the switching control signal Wb switches. FIG. 4C shows a partial waveform of the comparison pulse signal b1 including noise. FIG. 4D shows the waveform of the detection pulse signal Fg. As described above, the detection pulse signal Fg is a signal obtained by removing noise in a section where the noise removal mask signal wm is at the H level and detecting a switching edge of the signal of the comparison pulse signal b1. If the switching edge overlaps the noise removal mask period, the switching edge is detected immediately after the end of the noise removal mask period.

The commutation controller 17 shown in FIG. 1 measures the arrival interval of the rising edge of the detection pulse signal Fg output from the position detector 16, and provides the first commutation for giving a timing for applying a driving force to the rotor 1. Flow control signals EL1, EL2
It outputs EL3 and a second commutation control signal EU1, EU2, EU3. Further, the first commutation control signals EL1, EL2,
A switching control signal Wb, which is an output signal from the switching controller 14, is combined with EL3 to output commutation control switching signals ELs1, ELs2, and ELs3.

FIG. 5 shows a specific configuration of the commutation controller 17. The commutation controller 17 includes the time measuring device 130 and the delay circuit 1
31, a commutation signal generator 132, and a switching signal synthesizer 133. Time measuring instrument 130
Is configured to include an up counter and a state holding circuit. Each time the detection pulse signal Fg arrives, the count value is held in the state holding circuit and output as time measurement data Dt. Thereafter, the counter is reset and starts counting up from the count value 0. The delay circuit 131 includes a down counter. Each time the detection pulse signal Fg arrives, the time measurement data signal Dt obtained by shifting the time measurement value of the time measurement device 130 by 1 bit is input, and the countdown is started. When the down counter becomes zero, the delay pulse signal Fd is output. The clock pulses of the counters of the time measuring device 130 and the delay circuit 131 have the same frequency. That is, the delay pulse signal Fd is equal to the detection pulse signal Fg.
Becomes a signal delayed by a half of the output interval.

FIGS. 6A to 6E show operation waveforms of the time measuring device 130 and the delay circuit 131. FIG. FIG. 6A shows three-phase induced voltages Vb1, Vb2 generated in coils 2, 3, and 4.
Vb3 is shown. FIG. 6B shows the detection pulse signal Fg.
It is a waveform of. As described above, the detection pulse signal Fg generates a pulse at a point where the three-phase induced voltages Vb1, Vb2, and Vb3 become zero. FIG. 6C shows the waveform of the up counter of the time measuring device 130. FIG. 6D shows the delay circuit 13.
1 is a waveform of a down counter of 1. FIG. 6E shows a waveform of the delay pulse signal Fd which is an output signal of the delay circuit 131.

The commutation signal generator 132 shown in FIG. 5 changes the internal state every time the delayed pulse signal Fd arrives, and the first commutation control signals EL1, EL2, EL3 and the second commutation control signal correspond to the internal state. It outputs commutation control signals EU1, EU2 and EU3.
7A to 7E show operation waveforms of the commutation signal generator 132. FIG. 7A shows three-phase induced voltages Vb1, Vb2, and Vb3 generated in the coils 2, 3, and 4. FIG.
(B) is a waveform of the detection pulse signal Fg. FIG. 7 (c)
Is the waveform of the delayed pulse signal Fd. FIG. 7D shows the second
Of the commutation control signals EU1, EU2 and EU3 of FIG.
(E) is a waveform of the first commutation control signals EL1, EL2, EL3. Thus, the first commutation signal EL1 and the second
Is in phase with the induced voltage Vb1. Similarly, the first commutation signal EL2 and the second commutation signal EU2 have the same phase as the induced voltage Vb2. Similarly, the first commutation signal EL3 and the second commutation signal EU3 have the same phase as the induced voltage Vb3. This is a phase in which the driving force is applied to the rotor 1 with high efficiency.

The switching signal combiner 133 in FIG. 5 combines the first commutation control signals EL1, EL2, EL3 and the switching control signal Wb to generate commutation control switching signals ELs1, ELs2, ELs3. The first power transistors 5, 6, and 7 perform on / off operations including high-frequency switching operations in response to the commutation control switching signal signals ELs1, ELs2, ELs3. The second power transistors 8, 9, and 10 perform on / off operations in response to the second commutation control signals EU1, EU2, and EU3.

FIGS. 8A to 8C show commutation control switching signals ELs1, ELs2, ELs3, second commutation control signals EU1, EU2, EU3, and drive currents I1, I2, The waveform of I3 is shown.

FIG. 8A shows the relationship between the second commutation control signal EU1, the commutation control switching signal EL1, and the drive current I1. When the second commutation control signal EU1 is at the H level, the second power transistor 8 is turned on, and supplies a driving current on the positive electrode side to the coil 2. When the commutation control switching signal ELs1 is at the H level, the first power transistor 5 is turned on, and supplies a driving current on the negative electrode side to the coil 2.
However, since the switching control signal Wb is combined with the commutation control switching signal ELs1, the first power transistor 5 performs an on / off high-frequency switching operation. Therefore, the drive current I2 of the coil 2 has a current waveform including a high-frequency ripple. Details of the switching operation will be described later.

FIG. 8B shows the relationship between the second commutation control signal EU2, the commutation control switching signal EL2, and the drive current I2. FIG. 8C shows the second commutation control signal EU.
3 shows the relationship between the drive current I3 and the drive current I3.

The drive controller 18 shown in FIG. 1 includes first power transistors 5, 6, 7 and second power transistors 8,
Commutation control switching signal signals ELs1, ELs2, E for giving timings to turn on and off the gates of the switches 9 and 10
Ls3 and the second commutation control signals EU1, EU2, EU3 are input, and the first power transistors 5, 6, 7 and the second
Of the power transistors 8, 9, 10 are turned on and off, and the first drive control signal HL
1, HL2, HL3 and the second drive control signals HU1, HU
2 and HU3 are output. The charge pump 21 outputs a high potential Vu for operating the second power transistors 8, 9, 10 at a sufficiently low voltage.

The command device 15 includes a speed controller for controlling the rotation speed of the rotor 1 to a predetermined value. The command device 15 detects the rotation speed of the rotor 1 based on the detection pulse signal Fg of the position detector 16, and detects the detected rotation speed. And a command signal Ad corresponding to the difference between the rotation speed and the target rotation speed given by the rotation command signal Fc. Here, the command signal Ad is a voltage signal.

The switching controller 14 includes the current detector 11
Is compared with the command signal Ad of the command device 15, and a switching control signal Wb corresponding to the comparison result is output. As described above, the switching control signal Wb is the first commutation control signal EL1, EL2,
EL3 and the first power transistors 5, 6,
7 is operated for high frequency switching. The switching controller 14 includes a switching signal generator 12 and a forced on / off generator 13.

FIG. 9 shows a specific configuration of the current detector 11 and the switching signal generator 12. The current detector 11 includes a current detection resistor 140 inserted in a current supply path on the negative electrode side of the DC power supply 30, and detects an energization current pulse Ig of the DC power supply 30 based on a voltage drop generated in the resistance 140 to detect the current. The pulse signal Ag is output.

Comparison circuit 1 of switching signal generator 12
Reference numeral 41 compares the command signal Ad with the current detection pulse signal Ag to obtain a comparison output signal Cr. Reference trigger generation circuit 1
42 outputs a high-frequency trigger pulse signal Dp of 60 kHz and repeats the state holding circuit 143 at predetermined time intervals.
Trigger. The state holding circuit 143 outputs the switching signal W at the rising edge of the trigger pulse signal Dp.
a is changed to H level, and the switching signal Wa is changed to L level at the rising edge of the comparison output signal Cr.

FIG. 10A shows a switching signal generator 1.
2 shows operation waveforms of FIG. 2 and waveforms of drive currents I1, I2, and I3. However, the operation of the forced on / off generator 13 in FIG. 1 is omitted. The forcible on / off operation will be described later. FIG. 10A-1 shows the waveform of the trigger pulse signal Dp,
(A-2) is the waveform of the comparison output signal Cr, (a-3) is the waveform of the switching signal Wa, and (a-4) is the command signal Ad.
And the waveform of the current detection pulse signal Ag, and (a-5) shows the state of the high-frequency switching operation. When the trigger pulse signal Dp arrives, the switching signal Wa has changed to the H level. At this time, the first power transistors 5, 6, and 7 in FIG.
, The drive currents I1, I2, and I3 gradually increase.

The drive currents I1, I2 and I3 are supplied to the current detector 1
1 and output as a current detection pulse signal Ad. When the current detection pulse signal Ad becomes larger than the command signal Ad, the comparison output signal Cr becomes H level, and at that moment, the switching signal Wa changes to L level. At this time, the first power transistors 5, 6, and 7 are turned off, and the drive current flowing through the coils 2, 3, and 4 gradually decreases. When the first power transistors 5, 6, 7 are off, the power transistors 5, 6, 7 are off, so that no current flows through the current detector 11, and the value of the current detection pulse signal Ad becomes zero. . By repeating this operation, the total current of the drive currents I1, I2, and I3 is controlled to a value corresponding to the command signal Ad.

FIG. 11 shows a specific configuration of the forced on / off generator 13. The forced on / off creator 13 includes a forced on creator 160, a forced off creator 161, and a mode holding circuit 154 that holds a state of a combination of a forced on time and a forced off time. The compulsory-on creation section 160 includes a compulsory-on timing composer 152 and a compulsory-on combiner 150. The forced off creation unit 161 includes a forced off timing creation unit 153 and a forced off synthesis unit 151. The mode holding circuit 154 includes a mode storage register 155 and a selection circuit 156.

The mode storage register 155 stores a plurality of forced on / off modes which are combinations of information on the time when the first power transistors 5, 6, 7 are forcibly turned on and information on the time when the first power transistors 5, 6, 7 are forcibly turned off. . Selection circuit 156
Is the forced ON / OFF state stored in the mode storage register section 155 by the mode selection signal Bz from the time switch 23 of FIG.
The off mode is selected, and the forced on time data Da and the forced off time data Db are output to the forced on creation unit 160 and the forced off creation unit 161 respectively.

FIG. 10B shows waveforms for explaining the reason why forced on and forced off are necessary. FIG. 10 (b-1) shows the waveform of the trigger pulse signal Dp, (b-2) shows the waveform of the comparison output signal Cr, (b-3) shows the waveform of the switching signal Wa, and (b-4) shows the command signal Ad. Current detection pulse signal A
The waveform g, (b-5) shows the state of the switching operation. These waveforms perform the same operation as that of FIG. However, FIG. 10B shows the waveform of the switching loss phenomenon when the on-duty of the high-frequency switching operation exceeds 50%.

The point X1 in FIG. 10 (b-4) corresponds to the current detection pulse signal Ag immediately before the arrival of the trigger pulse signal Dp.
Is larger than the command signal Ad. In this case, the trigger pulse signal Dp arrives immediately after the first power transistor turns off, and the first power transistors 5, 6, and 7 turn on. That is, the off time of the first power transistor becomes very short. The first power transistors 5, 6, and 7 are turned off again in a short time (point X2). Since the next arrival of the trigger pulse signal Dp becomes relatively slow, the reduction width of the drive currents I1, I2, I3 becomes large (point X3).

After the trigger pulse signal Dp arrives, the drive currents I1, I2, I3 increase when the first power transistors 5, 6, 7 are turned on. At this time, consider the case where the on-duty exceeds 50%. In this case, the current decrease rate Δf and the current increase rate Δr are larger in the current decrease rate Δf. That is, when the current increase becomes slower with respect to the current decrease, and the sum of the driving currents I1, I2, and I3 does not reach the current value corresponding to the command signal Ad by the arrival point (point X4) of the next trigger pulse signal. Occurs. This is the switching loss phenomenon.

As described above, the switching loss occurs after the switching off timing occurs immediately after the arrival of the trigger pulse signal Dp. When this phenomenon occurs, even if the trigger pulse signal Dp is, for example, 60 kHz, the actual switching frequency is 60 kHz and 30 kHz.
The z portion is mixed, and the switching frequency becomes unstable. The problem in this case will be described below.

When the switching frequency becomes unstable, the drive currents I1, I2, I
3, the current ripple becomes large. Further, since the switching frequency is unstable, there is a problem that the disturbance of the driving current is large and the control performance of the rotational speed is reduced. Another problem when the switching frequency becomes unstable occurs because many switching timings shorter than the noise mask of the position detector 16 occur. This means that the switching mask sections are continuously combined, and during this period, position detection cannot be performed, which causes a reduction in jitter performance.

Still another problem when the switching frequency becomes unstable is caused by a long switching off. Generally, it is difficult to accurately detect the position when the switching is off, and it is often the case that the position detection is not accurate when the switching is not performed. In this case, if a long switching-off period occurs due to switching omission, a period during which position detection is not possible is lengthened, which also leads to a reduction in jitter performance. In the present embodiment, switching is stabilized by a forced on / off generator. The operation will be described below.

The forced ON timing generator 152 of the forced ON generator 160 shown in FIG. 11 receives the forced ON time data Da, the trigger pulse signal Dp, and the forced OFF timing signal output from the forced OFF timing signal generator. In synchronization with the trigger pulse signal Dp, it outputs a forced ON timing signal Cx which becomes H level for a time determined by the forced ON time data Da. Force-on synthesizer 150
Is the switching signal Wa and the forced ON timing signal Cx
And outputs a switching signal wx to which the forced ON timing is added.

FIGS. 12A to 12G are waveform diagrams showing the operation of the forced ON operation. However, this figure shows a case where there is no forced off section. The timing when the forced ON section and the forced OFF section are present at the same time will be described later. 12A shows the waveform of the trigger pulse signal Dp, FIG. 12B shows the waveform of the comparison output signal Cr shown in FIG. 9, FIG. 12C shows the waveform of the switching signal Wa, and FIG. 12D shows the waveform of the forced on-timing signal Cx. ,
(E) shows the waveform of the switching signal wx to which the forced ON timing is added, (f) shows the waveform of the command signal Ad and the current detection pulse signal Ag shown in FIG. 9, and (g) shows the on / off state of the switching operation. ing. As described above, the switching signal Wa has a waveform corresponding to the trigger pulse signal Dp and the comparison output signal Cr.

Here, the first power transistor 5,
6 and 7 are assumed to be performing on / off operations in accordance with the switching signal wm in which the forcible on-timing signal Cx is added to the switching signal Wa (the forced off operation described later is ignored for the sake of explanation). Forced ON timing signal C
x functions to always turn on the first power transistors 5, 6, and 7 when the signal is at the H level. Ta in FIG. 12 indicates a section in which the switching-on state is continued by the forced on-timing signal Cx even though the comparison output signal Cr is at the H level. As described above, the phenomenon of switching omission occurs after the switching off timing occurs immediately after the arrival of the trigger pulse Dp. However, by providing the forced on section,
Since the switching-on timing and the switching-off timing do not approach each other, switching omission can be prevented or establishment of switching omission is greatly reduced. Therefore, the switching operation is stabilized.

The forced off timing generator 153 of the forced off generator 161 in FIG. 11 receives the forced off time data Db and the trigger pulse signal Dp, and receives the trigger pulse signal Dp.
In synchronization with the forced off time data Db, a forced off timing signal Cy which becomes H level for a time determined by the forced off time data Db is output. The forced off combiner 151 combines the switching signal wx and the forced off timing signal Cy and outputs a switching control signal Wb to which a forced off timing is added.

FIGS. 13A to 13H are waveform diagrams showing the operation of the forced ON operation. FIG. 13A shows the trigger pulse signal D.
The waveform of p, (b) is the waveform of the comparison output signal Cr shown in FIG. 9, (c) is the waveform of the switching signal Wa, (d) is the waveform of the forced off timing signal Cy, and (e) is the forced on timing signal. The waveform of Cx, (f) is the waveform of the switching control signal Wb to which the forced off timing is added, (g) is the waveform of the command signal Ad and the current detection pulse signal Ag shown in FIG. 9, and (h) is the ON of the switching operation. -Indicates an off state. The switching signal wx is the switching signal described with reference to FIG. The relation between the forced ON timing signal and the forced OFF timing signal is such that the forced OFF section starts at the moment when the trigger pulse signal Dp is output, and the forced ON section starts at the moment when the forced OFF section ends.

The first power transistors 5, 6, 7
An on / off operation is performed according to a switching control signal Wb in which a forced off timing signal Cy is added to the switching signal wx. The forced off timing signal Cy is H
The level section is always the first power transistor 5, 6,
7 functions to turn off. Tb1 and Tb2 in FIG.
Indicates a section in which the switching-off state is caused by the forced off timing signal Cx even though the comparison output signal Cr is not at the H level.

As described above, the switching loss phenomenon occurs after the switching off timing occurs immediately after the arrival of the trigger pulse Dp. However, by providing the forced off section, the switching on timing and the switching off timing approach each other. Because of this, switching loss can be prevented or the probability of switching loss is significantly reduced. Therefore, the switching operation is stabilized. Generally, the forced off time for stabilizing the switching operation is shorter than the forced on time. This is because when the forced on / off is required, the on-duty is large.

Forcibly on and forcibly off are used alone or in combination, and the forcible on / off time is switched by the time switch 23 of FIG. The reason will be described.
Although the forced ON operation and the forced OFF operation stabilize the switching operation as described above, the operation range of the motor is limited.

For example, if the forced ON period is 6 μs at a frequency of 100 kHz, the forced ON period must be 6 μs during one cycle of 10 μs.
Since μs is forcibly switched on, the on-duty does not become less than 60% and cannot be used during low-speed rotation where the on-duty becomes small. Similarly,
If the forced off period is 2 μs at the frequency of 100 kHz, the switching off state is forced for 2 μs in one cycle of 10 μs, so that the on duty is 80%.
It cannot be used at the time of high-speed rotation or startup when the on-duty becomes large. Therefore, the forced ON time and the forced OFF time are switched and used according to the rotation state of the motor.

The time switch 23 shown in FIG. 1 includes a mode selector such as a one-chip microcomputer for determining an appropriate forced on / off time according to the rotation state of the motor, and outputs a mode switch signal Bz. Forced on / off generator 13
Output to The mode holding circuit 154 of the forced on / off generator 13 in FIG. 11 receives the mode switching signal Bz and selects a desired mode from the forced on / off modes stored in the storage register 155 in advance by the selection circuit 156. Are output to the forced on creation unit 160 and the forced off creation unit 161.

The switching of the forced on / off mode by the time switch 23 will be specifically described with reference to the flowchart of FIG. As described above, in the present description, the switching frequency determined by the trigger pulse signal Dp is 60 kHz. When a motor rotation command is issued, the time switch 23 outputs a rotation command signal Fc and sets a target rotation speed in the command device 15 according to the rotation command. Further, the mode selection signal B is applied to the forcible on / off generator.
Output z to select the forced on / off mode for startup. In the forced on / off mode for startup, the time for forced on is 1 μs, and the time for forced off is 0 μs. In this mode, at the time of start-up when high-precision jitter performance is not required, the time of forced on / off is minimized so as not to limit the operating range of the motor.

After the speed setting and the forced ON / OFF mode setting are completed, the motor starts to be started. Until the motor reaches the target rotation speed, the forced on / off mode for starting is maintained. The determination as to whether the motor has reached the target rotational speed is made based on the voltage value of the command signal Ad, which is a speed control signal. After the motor reaches the target rotation speed, the forced on / off mode is set according to the target rotation speed. As described above, the motor according to the present embodiment is a motor for a hard disk, and the rotation speed of the motor is 2,000 rpm, 4,000 rpm, and 55 rpm.
00 rpm.

The rotation speed of 2000 rpm is a low rotation mode at the time of power saving of the hard disk, and does not involve access to the disk 25. The rotation speed of 4000 rpm is a low-speed operation mode, and is used when low power consumption is required.
Accompanying disk access. The rotation speed of 5400 rpm is the normal operation mode. When the number of revolutions is 2000 rpm, the forced on / off mode uses the same mode as at startup.

When the number of revolutions is 400 rpm, a mode in which the forced on time is 1 μs and the forced off time is 3 μs is used. This is because the forced on operation for realizing low jitter may not be able to cope with a decrease in on-duty at low load and high power supply voltage, and thus low jitter of the motor is realized by forced off. In this case, since the number of rotations is low, there is room for an increase in on-duty. Also,
In the present embodiment, a noise removal mask signal w that determines a section in which noise due to switching described in FIG.
The output section of m is set to 2.5 μsec. At the time of switching operation, an off period of at least 3 μs is guaranteed by forcible off, so that a position detectable section always exists in the switching off section. Therefore, the position detection operation becomes stable, and a motor with lower jitter can be realized.

When the rotational speed is 5500 rpm, a mode in which the forced on time is 8 μs and the forced off time is 0 μs is used. This is because the forced off operation for realizing low jitter may not be able to cope with an increase in on-duty at a high load and a low power supply voltage. In this case, since the number of rotations is high, there is room for a decrease in on-duty. In the present embodiment, the output section of the noise removal mask signal wm that determines the section in which the noise associated with the switching described in FIG. 4 is ignored is set to 2.5 μs. At the time of the switching operation, since the ON period of at least 6 μs is guaranteed by the forced ON, a position detectable section is always formed in the switching ON section. Therefore, the position detection operation becomes stable, and a motor with lower jitter can be realized.

In the following, the mode is switched every time the rotational speed changes. By performing the above operation, low jitter can be realized when disk access is involved due to the forced on operation or the forced off operation. Further, by switching the combination of the forced ON time and the forced OFF time, the normal operation of the motor is guaranteed even if various conditions such as the number of revolutions, load, and power supply voltage change.

In this embodiment, since the first power transistors 5, 6, and 7 are operated at high speed switching, the power loss of the motor is small. Therefore, the motor has high power efficiency.

Further, in this embodiment, the switching operation is stabilized by the forced ON operation or the forced OFF operation. Therefore, disturbance of the drive current is reduced, and the current control performance is improved. Further, since the switching operation is stabilized, the position detection operation is also stabilized, and the jitter performance is improved.

In the present embodiment, the combination of the forced on time and the forced off time is stored in the mode storage register 1.
55, and is forcibly turned on when the motor is started, at low speed rotation, or at high speed rotation by the mode selector of the time switcher 15.
Switching off mode. Therefore, normal operation of the motor and low jitter are guaranteed even when various conditions such as the number of revolutions, load, and power supply voltage change.

In the present embodiment, a mode in which the forced ON time is longer than the output section of the noise removal mask signal wm in position detection is prepared. Therefore, the jitter performance at the time of the forced ON operation is further improved.

In the present embodiment, a mode is prepared in which the forced off time is longer than the output section of the noise removal mask signal wm in position detection. Therefore, the jitter performance during the forced off operation is further improved.

(Embodiment 2) FIGS. 15 to 24 show a motor according to Embodiment 2 of the present invention. FIG. 15 shows the overall configuration. This embodiment is different from the first embodiment in the configuration of the switching controller 14x and the time switch 23x. The combination of the forced ON time and the forced OFF time (forced ON / OFF mode) is different from that of the first embodiment. And the method of switching the forced on / off mode is different. In the description of the present embodiment, the configuration and operation of the switching controller 14x and the time switch 23x will be mainly described. In other configurations, the same components as those in the first embodiment will be assigned the same reference numerals. ,
Detailed description is omitted.

FIG. 15 shows an overall view of the present embodiment. The switching controller 14x includes the switching signal generator 1
2x and a forced on / off generator 13x. The switching signal generator 12x receives the detection signal Ag of the current detector 11 and the command signal Ad, and switches the switching signal Wa, the trigger pulse signal Dp, and the comparison output signal Cr.
Is output. These signal waveforms correspond to those of the first embodiment.
, Except that the comparison output signal Cr is output. However, the waveform of the comparison output signal Cr is the same as that of the first embodiment. Forced on / off generator 13x
Is a switching control signal W obtained by adding a forced ON period and a forced OFF period to the switching signal Wa based on the forced ON / OFF time signal Bx output from the time switch 23x.
b is output. Further, it outputs a determination signal Wf for determining the forced off period and a determination signal Wg for determining the forced on period. These specific operations will be described below.

FIG. 16 shows a specific configuration of the current detector 11 and the switching signal generator 12x. This configuration is different from the first embodiment only in that the comparison output signal Cr is output to the compulsory on / off generator 13x. Other configurations, signal waveforms, and the like are the same as those in the first embodiment, and thus detailed description is omitted.

FIG. 17 shows a specific configuration of the compulsory on / off generator 13x. The forced-on creation unit 160 and the forced-off creation unit 161 are the same as those in the first embodiment, and a description thereof will be omitted. The mode holding circuit 154x includes a forced on-time storage register 155x and a forced off-time storage register 155x.
5y. The forced ON time storage register 155x and the forced OFF time storage register 155y store the forced ON time and the forced OFF time, respectively. The forced ON time and the forced OFF time are rewritten by the forced ON / OFF time signal Bx from the time switch 23x in FIG.
The data is output as forced ON time data Da and forced OFF time data Db. The forced on / off time signal Bx is a signal composed of a forced on time signal Bxa and a forced off time signal Bxb.

The off-state detection circuit 162 includes a state holding circuit 163 having a clear terminal, and outputs an off-state signal Wf. The off-state signal Wf is a signal for determining whether the first power amplifying means 5, 6, 7 has been turned off at the output timing of the comparison output signal Cr or turned off at the start of the forced off period. This signal is output to the time switch 23
x is used to determine the forced off time. The on-state detection circuit 164 is a signal composed of, for example, a counter, and outputs an on-state signal Wg. ON state signal Wg
Means that the first power amplifying means 5, 6, 7 has the comparison output signal C
This signal is used to determine whether the switch has been turned off at the output timing of r or turned off at the end timing of the forced on period. This signal is used when the time switch 23x determines the forced ON time.

The operation of the off-state detection circuit 162 will be described with reference to FIGS. 18A to 18G show operation waveforms of the off-state signal Wf. 18A shows the waveform of the trigger pulse signal Dp, FIG. 18B shows the waveform of the comparison output signal Cr, FIG. 18C shows the waveform of the switching signal Wa, FIG. 18D shows the waveform of the forced off timing signal Cy, and FIG. The waveform of the switching control signal Wb, (f) is the waveform of the command signal Ad and the current detection pulse signal Ag, and (g) is the off-state signal Wf. Since the signals (a) to (f) have the same waveforms as in the first embodiment described with reference to FIG. 13, detailed description will be omitted.

Ty1, Ty2, Ty3, Ty4 of FIG.
Is a section divided for each output of the trigger pulse signal Dp. The trigger pulse signal Dp is input to the clear terminal CLR of the state holding circuit 163 in FIG. 17, and the output is cleared to the L level each time the trigger pulse signal Dp goes to the H level. The comparison output signal input Cr is input to the clock terminal CK of the state holding circuit 163, and the data input terminal D is pulled up to the H level. The state holding circuit 163 detects the rising edge of the comparison output signal Cr and sets the data output terminal Q to H level. The output of the data output terminal Q becomes the off-state signal Wf.

The off-state signal Wf is determined when the comparison output signal Cr is at the H level during the period in which the trigger pulse Dp is at the L level (when the switching is turned off due to the current detection pulse signal Ag reaching the command signal Ad). At the moment when the trigger pulse signal Dp goes to the H level, it changes to the L level, and maintains the L level as long as the trigger pulse signal Dp is at the H level. When the comparison output signal Cr does not change within the L level section of the trigger pulse Dp (when the switching is turned off by the forced off signal), it remains at the L level. As described above, the off-state signal Wf is a signal that distinguishes whether the first power transistors 5, 6, and 7 have been turned off by the comparison output signal Cr or the forced off timing signal Cy.

FIG. 19 shows waveform examples of the drive current waveform I1 and the off-state signal Wf. FIG. 19A shows the waveforms of the drive current I1 and the off-state signal Wf in the normal state. The frequency of pulse output omission of the off-state signal Wf is very low. That is, the power amplifiers 5, 6, and 7 have a very high probability of switching off at the output timing of the comparison output signal Cr, and have a low probability of switching off at the start timing of the forced off period. FIG. 19B shows the waveforms of the drive current I1 and the off-state signal Wf when the maximum rotation speed of the motor approaches. In this case, the power amplifiers 5, 6, and 7 have a high probability of switching off at the start timing of the forced off period, and a large number of missing pulses of the off state signal Wf occur.

The shorter the forcible off time, the higher the maximum rotational speed of the motor. For example, if the forced off time is 3 μs at a switching frequency of 100 kHz (the cycle is 10 μs), the on-duty does not become 70% or more because an off period of 3 μs always exists in one cycle of switching. If the forced off time is set to 2 μs, the on-duty can be obtained up to 80%. When the rotation speed of the motor is used near the limit maximum rotation speed, the probability that the first power transistor turns off the switching becomes extremely low based on the comparison result with the command signal Ad which is the speed control signal, so that the control performance of the motor also increases. descend.

The operation of the on-state detection circuit 164 will be described with reference to FIGS. FIGS. 20A to 20G show operation waveforms of the on-state signal Wg. 20A shows the waveform of the trigger pulse signal Dp, FIG. 20B shows the waveform of the comparison output signal Cr, FIG. 20C shows the waveform of the switching signal Wa, FIG. 20D shows the waveform of the forced on-timing signal Cx, and FIG. The waveform of the switching control signal Wb, (f) is the waveform of the command signal Ad and the current detection pulse signal Ag, and (g) is the on-state signal Wg. Since the signals (a) to (f) have the same waveforms as in the first embodiment described with reference to FIG. 13, detailed description will be omitted.

A section Tx in FIG. 20 is a section in which switching is forcibly turned on by forcible on. The comparison output signal Cr is input to the ON state detection circuit 164, and the ON state detection circuit 164 measures the H level time of the comparison output signal Cr. Section T in which switching is forcibly turned on
x is greater than the current value corresponding to the sum of the drive currents corresponding to the command signal Ad level, and the comparison output signal Cr is at the H level. The on-state detection circuit 164 outputs a pulse once when the comparison output signal continues longer than the predetermined time Tr. As described above, the on-state signal Wg is a signal for distinguishing whether the first power transistors 5, 6, 7 are turned off by the comparison output signal Cr or turned off at the end of the forced on-timing signal Cx. .

FIG. 21 shows a waveform example of the drive current waveform I1 and the ON state signal Wg. FIG. 21A shows the waveforms of the drive current I1 and the ON-state signal Wg in the normal state. The frequency of the pulse output of the ON state signal Wg is very low. That is, the power amplifiers 5, 6, and 7 have a very high probability of switching off at the output timing of the comparison output signal Cr, and have a low probability of switching off at the end timing of the forced on period. FIG. 21B shows the waveforms of the drive current I1 and the on-state signal Wg when the minimum rotation speed of the motor approaches. In this case, the power amplifiers 5, 6, and 7 have a high probability of switching off at the end timing of the forced ON period, and many pulses of the ON state signal Wg are generated.

The shorter the forcible on-time, the lower the minimum rotational speed of the motor. For example, if the forced ON time is 6 μs at a switching frequency of 100 kHz (the cycle is 10 μs), the ON period does not become 60% or less because an OFF period of 6 μs always exists in one cycle of switching. If the forcible on-time is set to 4 μs, the on-duty can be reduced to at least 40%. When the rotation speed of the motor is used near the minimum rotation speed, the probability of switching off based on the result of comparison with the command signal Ad, which is a speed control signal, is significantly reduced, so that the control performance of the motor is greatly reduced.

The time switch 23x shown in FIG. 15 includes a mode selector, such as a one-chip microcomputer, for determining an appropriate forced on / off time according to the rotation state of the motor. The signal Bx is output to the forced on / off generator 13x. The switching of the forced on / off mode by the time switch 23x will be specifically described with reference to the flowchart of FIG. In the present embodiment, the switching frequency determined by the trigger pulse signal Dp is 60 kHz as in the first embodiment.
And When a motor rotation command is generated, the time switch 23x outputs a rotation command signal Fc and sets a target rotation speed according to the rotation command in the command device 15. Further, a forced on / off time signal Bx is output to the forced on / off creator 13x to set a forced on / off mode for starting.

In the forced on / off mode for starting, the forced on time is 1 μs and the forced off time is 0 μs. In this mode, at the time of start-up when high-precision jitter performance is not required, the time of forced on / off is minimized so as not to limit the operating range of the motor. After the speed setting and forced ON / OFF mode setting are completed, the motor starts to be started. Until the motor reaches the target rotation speed, the forced on / off mode for starting is maintained. The determination as to whether the motor has reached the target rotational speed is made based on the voltage value of the command signal Ad, which is a speed control signal. After the motor reaches the target rotation speed, the initial forced ON / OFF mode is set. In the initial forced on / off mode, the forced on time is 1 μs, and the forced off time is 4 μs. After the initial forced on / off mode is set, the flow differs depending on whether the normal rotation speed is 2000 rpm, 4000 rpm, or 5500 rpm.

Here, the motor of the present embodiment is a motor for a hard disk as in the first embodiment. When the number of rotations of the motor is 2000 rpm, the mode is the low rotation mode at the time of power saving of the hard disk, and no access to the disk 25 is involved. Rotation speed 4000rpm
Is a low-speed operation mode, which is used when low power consumption is required, and involves disk access. 5,500 rpm
In the case of m, the normal operation mode is set. The rotation speed is 2000r
At pm, the on-duty is small, so that if the forced off time is about 4 μs, the motor control performance is not affected. Therefore, the forced on / off mode is not changed. When the number of rotations is 5500 rpm, a forced off time adjustment routine is executed, and after setting an appropriate forcible on / off time, the process shifts to a normal rotation operation. Details of the forced off time adjustment routine will be described later.

When the rotation speed is 4000 rpm, 400
After setting the initial on / off time for 0 rpm, the forced on time adjustment routine is executed to set an appropriate forced on / off time. The details of the forced ON time adjustment routine will be described later. The initial on / off times for 4000 rpm are strong 7 μs and 0 μs, respectively. In the following, the mode is switched every time the rotational speed changes.

FIG. 23 shows a flowchart of the forced off time adjustment routine. As described above, the forced on time in the initial forced on / off mode is 1 μs, and the forced off time is 4 μs.
Seconds. The time switch 23x outputs from the OFF state signal Wf
It is determined whether or not the rotation speed of the motor is close to the maximum rotation speed limit. According to this method, the number of pulses of the off-state signal Wf is counted within a predetermined time, and it is determined whether or not the number is equal to or more than a predetermined number. If the number of pulses is equal to or greater than the predetermined number, it is determined that the motor rotational speed has a margin with respect to the limit maximum rotational speed, and the forced off time adjustment routine ends.

If the number of pulses is equal to or less than the predetermined number, the forcible off time is changed to 3 μs, and it is determined again from the off state signal whether the motor speed is close to the maximum speed limit.
If the number of pulses is equal to or greater than the predetermined number, it is determined that the motor rotational speed has a margin with respect to the limit maximum rotational speed, and the forced off time adjustment routine ends. If the number of pulses is equal to or less than the predetermined number, the forcible off time is changed to 2 μs, and the forcible off adjustment routine ends.

As described above, an appropriate forced off time can be set. The appropriate forced off time at the time of high-speed rotation, such as 5500 rpm, is as long as possible within a range that does not approach the limit maximum rotation speed of the motor too much. Although the forced off time has a large effect of reducing jitter, it is not possible to set an excessively long forced off in consideration of motor variation, motor additional fluctuation, and power supply voltage fluctuation. By carrying out, the margin for the above-mentioned variation and fluctuation can be reduced. Therefore, it is possible to set a more appropriate forced off time as compared with the first embodiment.

FIG. 24 shows a flowchart of the forced on-time adjustment routine. As described above, the forced on time in the initial forced on / off mode for 4000 rpm is 7 μs,
The forced off time is 0 μsec. The time switch 23x determines from the ON state signal Wg whether or not the rotational speed of the motor is close to the minimum speed limit. In this method, the number of pulses of the ON state signal Wf is counted within a predetermined time, and it is determined whether or not the number is equal to or more than a predetermined number.

If the number of pulses is equal to or less than the predetermined number, it is determined that the rotational speed of the motor has a margin relative to the minimum rotational speed, and the forced on-time adjusting routine is terminated. If the number of pulses is equal to or greater than the predetermined number, the forced ON time is changed to 6 μs, and it is again determined from the OFF state signal whether the motor speed is close to the limit maximum speed. The above operation is performed with a forced ON time of 4
Repeat until the time reaches μs.

By executing the above routine, an appropriate forced ON time can be set. The appropriate forcible on-time at a medium speed rotation of about 4000 rpm is as long as possible within a range not too close to the minimum rotation speed of the motor. Although the forced ON time has a large effect of reducing jitter, too long forced ON cannot be set in consideration of motor variation, motor additional variation, and power supply voltage variation. However, by executing this routine every time the motor is started and every time the speed is changed, a margin for the above-mentioned variation and fluctuation can be reduced. Therefore, it is possible to more appropriately set the forced on-time as compared with the first embodiment.

In the present embodiment, the same effect as in the first embodiment can be obtained.

In this embodiment, since the first power transistors 5, 6, and 7 are operated at high speed switching, the power loss of the motor is small. Therefore, the motor has high power efficiency.

In this embodiment, the switching operation is stabilized by the forced ON operation or the forced OFF operation. Therefore, disturbance of the drive current is reduced, and the current control performance is improved. Further, since the switching operation is stabilized, the position detection operation is also stabilized, and the jitter performance is improved.

Further, in this embodiment, by executing the forced off time adjustment routine and the forced on time adjustment routine at the time of startup and at the time of rotation speed fluctuation, various conditions such as the rotation speed, load, and power supply voltage change. This also makes it possible to set an appropriate forced on / off time. That is, since a margin for fluctuation of various conditions is small, a lower jitter can be realized.

Note that the first embodiment and the second embodiment are described above.
Various modifications can be made to the specific configuration of.
For example, the coils of each phase are not limited to the star connection, but may be the delta connection. Further, the number of phases of the coil is not limited to three. Further, the number of magnetic poles of the rotor is not limited to two, but may be multi-pole.

Further, the energization angle of the motor is not limited to 120 degrees. Wide-angle energization such as 150 degrees may be used. Further, the drive current waveform is not limited to a rectangular waveform. A trapezoidal waveform may be provided with a current slope.

The high-frequency switching need not be performed only by the lower power transistor. Switching may be performed by only the upper power transistor, or switching may be performed by both the upper and lower sides.

In addition, various changes can be made without changing the gist of the present invention, and it goes without saying that the present invention is included in the present invention.

[0101]

As is apparent from the above description, in the motor of the present invention, the forced on / off time is provided in the high frequency switching operation, and the forced on / off time is switched according to the rotation state of the motor. The switching operation reduces the loss of the power transistor, and the proper forced on / off time setting also reduces the motor jitter. As a result, a high-performance motor that realizes a low-power-consumption, low-jitter motor optimal for a hard disk device or the like is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a motor according to a first embodiment of the present invention.

FIG. 2 shows a position detector 16 according to Embodiment 1 of the present invention.
Diagram showing the configuration of

FIG. 3 shows a position detector 16 according to the first embodiment of the present invention.
Waveform diagram for explaining the operation of

FIG. 4 is a diagram illustrating a position detector 16 according to the first embodiment of the present invention.
Waveform diagram for explaining the operation of

FIG. 5 shows a commutation controller 17 according to the first embodiment of the present invention.
Diagram showing the configuration of

FIG. 6 shows a commutation controller 17 according to the first embodiment of the present invention.
Waveform diagram for explaining the operation of

FIG. 7 shows a commutation controller 17 according to the first embodiment of the present invention.
Waveform diagram for explaining the operation of

FIG. 8 shows a commutation controller 17 according to the first embodiment of the present invention.
Waveform diagram for explaining the operation of the device and the drive currents I1, I2, I3

FIG. 9 is a current detector 11 according to the first embodiment of the present invention.
Showing the configuration of the switching signal generator 12 and the switching signal generator 12

FIG. 10 is a waveform chart for explaining a switching operation and a switching omission phenomenon according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a forced on / off generator 13 according to the first embodiment of the present invention.

FIG. 12 is a waveform chart for explaining a forced on operation according to the first embodiment of the present invention;

FIG. 13 is a waveform chart for explaining a forced off operation in the first embodiment of the present invention.

FIG. 14 is a time switch 2 according to the first embodiment of the present invention.
Flowchart for explaining the operation 3

FIG. 15 is a diagram showing an overall configuration of a motor according to a second embodiment of the present invention.

FIG. 16 shows a current detector 1 according to the second embodiment of the present invention.
1 and the configuration of the switching signal generator 12x

FIG. 17 is a diagram showing a configuration of a forced on / off generator 13x according to the second embodiment of the present invention.

FIG. 18 is a waveform chart illustrating the operation of the off-state detection circuit 162 of the forced on / off generator 13x according to the second embodiment of the present invention.

FIG. 19 is a waveform chart illustrating an operation of an off-state signal Wf that is an output signal of the off-state detection circuit 162 according to the second embodiment of the present invention.

FIG. 20 is a waveform chart illustrating the operation of the on-state detection circuit 164 of the forced on / off generator 13x according to the second embodiment of the present invention.

FIG. 21 is a waveform chart illustrating an operation of an on-state signal Wg which is an output signal of the on-state detection circuit 164 according to the second embodiment of the present invention.

FIG. 22 is a time switcher 2 according to the second embodiment of the present invention.
Flowchart for explaining 3x operation

FIG. 23 is a time switch 2 according to the second embodiment of the present invention.
Flowchart for explaining a forced off adjustment routine included in the operation of 3x

FIG. 24 is a time switch 2 according to the second embodiment of the present invention.
Flowchart for explaining a forced ON adjustment routine included in the operation of 3x

FIG. 25 is a diagram showing a configuration of a conventional motor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 rotor 2, 3, 4 coil 5, 6, 7 first power amplifier 8.9, 10 second power amplifier 11 current detector 12 switching signal generator 13 forcible on / off generator 14 switching controller 15 command Device 16 position detector 17 commutation controller 18 drive controller 23 time switcher 25 disk

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideaki Mori 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Tetsuya Hirotsu 1006 Odaka Kadoma Kadoma, Osaka Pref. Terms (reference) 5H560 AA04 BB04 BB12 DA13 DB20 DC12 EB01 EC10 GG04 JJ02 JJ13 RR04 SS01 TT01 TT02 TT07 UA06 XA12 XA15

Claims (17)

[Claims] 1. A rotor having a permanent magnet, a multi-phase coil, a DC power supply serving as a power supply source, and a first path forming a current path between one terminal of the DC power supply and the coil. Q (Q is a positive number of 3 or more) first power amplifying units each including a power transistor; and a second power transistor forming a current path between the other terminal side of the DC power supply unit and the coil. Q second power amplifying means, respectively, energizing control means for controlling energization of the first power amplifying means and the second power amplifying means, position detecting means for detecting a rotational position of the rotor, Command means for outputting a command signal for controlling power supply to the coil based on the output pulse signal of the position detecting means; and a current detecting means for outputting a signal corresponding to a current supplied by the DC power supply means. Means; switching control means for turning on or off one or both of the Q first power amplifying means and the Q second power amplifying means; and the first power amplifying means or the second power amplifying means. And a time switching means for switching a time for forcibly turning on one or both of the power amplifying means for a predetermined period, wherein the switching control means comprises: the first power amplifying means or the second power Trigger means for generating a timing for turning on one or both of the amplifying means; and comparing the output signal of the current detecting means and the command signal to the first power amplifying means and the second power amplifying means. Comparing means for generating a timing for turning off one or both of the first power amplifying means in response to an output signal of the trigger means; Forcibly turning on one or both of the second power amplifying means for a predetermined period of time. The forcible on making means responds to an output signal of the time switching means. A motor characterized by switching the time for forcibly turning on. 2. A rotor having a permanent magnet, a multi-phase coil, a DC power supply serving as a power supply source, and a first path forming a current path between one terminal of the DC power supply and the coil. Q (Q is a positive number of 3 or more) first power amplifying units each including a power transistor; and a second power transistor forming a current path between the other terminal side of the DC power supply unit and the coil. Q second power amplifying means respectively including: power energizing control means for controlling energization of the first power amplifying means and the second power amplifying means; position detecting means for detecting a rotational position of the rotor; Command means for outputting a command signal for controlling power supply to the coil based on an output pulse signal of the position detecting means; and a current detecting means for outputting a signal corresponding to a current supplied by the DC power supply means. Means; switching control means for turning on or off one or both of the Q first power amplifying means and the Q second power amplifying means; and the first power amplifying means or the second power amplifying means. Time switching means for switching the time for forcibly turning off one or both of the power amplifying means for a predetermined period, wherein the switching control means comprises: the first power amplifying means or the second power Trigger means for generating a timing for turning on one or both of the amplifying means; and comparing the output signal of the current detecting means and the command signal to the first power amplifying means and the second power amplifying means. Comparing means for generating a timing for turning off one or both of the first power amplifying means in response to an output signal of the trigger means; Forcibly turning off one or both of the second power amplifying means for a certain period of time. The forcible off making means responds to an output signal of the time switching means. A motor characterized by switching the time for forcibly turning off. 3. A rotor having a permanent magnet, a multi-phase coil, a DC power supply serving as a power supply source, and a first path forming a current path between one terminal of the DC power supply and the coil. Q (Q is a positive number of 3 or more) first power amplifying units each including a power transistor; and a second power transistor forming a current path between the other terminal side of the DC power supply unit and the coil. Q second power amplifying means respectively including: power energizing control means for controlling energization of the first power amplifying means and the second power amplifying means; position detecting means for detecting a rotational position of the rotor; Command means for outputting a command signal for controlling power supply to the coil based on an output pulse signal of the position detecting means; and a current detecting means for outputting a signal corresponding to a current supplied by the DC power supply means. Means, switching control means for turning on or off one or both of the Q first power amplifying means and the Q second power amplifying means, and the first power amplifying means and the Q power amplifying means. Time switching means for switching between a time for forcibly turning on one or both of the second power amplifying means for a certain period of time and a time for forcibly turning off one of the second power amplifying means for a certain period, wherein the switching control means comprises: Trigger means for generating a timing for turning on one or both of the first power amplifying means and the second power amplifying means; and comparing the output signal of the current detecting means with the command signal to obtain the first Comparing means for generating a timing for turning off one or both of the power amplifying means and the second power amplifying means; and responding to an output signal of the trigger means. Forcible on-creating means for determining a timing for forcibly turning on one or both of the first power amplifying means and / or the second power amplifying means for a certain period, and forcible off for determining a timing for forcibly turning off for a certain period A motor comprising: a forcing means; and the forcible on creating means and the forcible off creating means switching between a forced on time and a forced off time in response to an output signal of the time switching means. 4. The motor according to claim 1, wherein the time for forcibly turning on the motor is set to 20% or more of a switching cycle by the time switching means. 5. The motor according to claim 2, wherein said time switching means can set the time for forcibly turning off to 10% or more of a switching cycle. 6. The forcible on creating means or the forcibly off creating means includes a time storage register for storing a set value of a forcibly on time or a forcibly off time, and the time switching means includes a forcibly on time. And a mode selection unit for determining a combination of a time to be forcibly turned off and a time to be forcibly turned off. The information on the time for forcibly turning on and the time for forcibly turning off determined by the mode selection unit are output to the time storage register. Claims 1 to 5 characterized in that:
The motor according to any one of the above. 7. The forced on creation means or the forced off creation means includes a mode storage register for storing a plurality of combinations of time setting values of one or both of a forced on time and a forced off time. The time switching means includes a mode selection means for outputting a mode selection signal for determining which of the combinations of time setting values stored in the mode storage register is to be used. The motor according to any one of claims 1 to 5, wherein one of a plurality of time setting values stored in the mode storage register is selected. 8. The apparatus according to claim 1, wherein said time switching means switches a time for forcibly turning on or a time for forcibly turning off in response to a rotation speed of said rotor.
The motor according to any one of the above. 9. The motor according to claim 1, wherein said time switching means switches between a time for forcibly turning on and a time for forcibly turning off in response to the command signal. 10. The motor according to claim 1, wherein said time switching means switches between a time for forcibly turning on and a time for forcibly turning off which are different between the time of starting and the time of steady rotation. . 11. The forcible off generating means is turned off at an output timing of the comparing means when one or both of the Q first power amplifying means and the Q second power amplifying means are turned off. Or a function for outputting an off-state signal for discriminating whether the power is turned off at the start timing of the forcible off period, and the time switching means forcibly turns off or forcibly turns on in response to the output state of the off-state signal. The motor according to any one of claims 2 to 10, wherein a time for performing the operation is switched. 12. The off-state signal is output only when one or both of the Q first power amplifying means and the Q second power amplifying means are turned off by the output signal of the comparing means. The time switching means, which is output, detects that the output of the off-state signal has become equal to or less than a predetermined number within a predetermined time, and switches a time for forcibly turning on or a time for forcibly turning off. Motor as described. 13. The forcible on-generating means is turned off at the output start timing of the comparing means when one or both of the Q first power amplifying means and the Q second power amplifying means are turned off. Or a function for outputting an off-state signal for discriminating whether the signal has been turned off at the end timing of the forcible on-period. The motor according to any one of claims 2 to 12, wherein a time period for switching is changed. 14. The off-state signal is output only when one or both of the Q first power amplifiers and the Q second power amplifiers are turned off at the end timing of the forced on period. The time switching means, which is output, detects that the output of the OFF state signal has been output a predetermined number of times or more within a predetermined time and switches to a time for forcibly turning on or a time for forcibly turning off. Motor as described. 15. The motor drives the hard disk to rotate, and the time switching means sets a different time for forced on or forced off between normal rotation and power saving rotation for reducing power by reducing the number of rotations. The motor according to claim 1, wherein the motor is switched. 16. A sensorless drive motor for rotating a hard disk and estimating a position by detecting a zero-cross point where an induced voltage generated by the coil becomes zero, wherein the position detecting means estimates a position. Detecting the Q first power amplifying means and the Q second power amplifying means
A power amplifying means having a switching mask period which is a period for removing noise at the time of on / off switching operation of the power amplifying means, wherein the time switching means is more than the switching mask period at the time of steady rotation with hard disk read / write. The motor according to any one of claims 1 to 15, wherein the motor is switched to a longer forced on time. 17. A motor of a sensorless drive for estimating a position by detecting a zero-cross point at which an induced voltage generated by the coil becomes zero, wherein the motor rotationally drives a hard disk. Detecting the Q first power amplifying means and the Q second power amplifying means
The power amplification means has a switching mask period which is a period for removing noise at the time of on / off switching operation of one or both of the power amplification means, and the time switching means is more than the switching mask period at the time of steady rotation with read / write of the hard disk. 17. The motor according to claim 1, wherein the motor is switched to a longer forced off time.