JP2004047946A - Forming method of metal wiring and manufacture of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a forming method of metal wiring for selectively forming the wiring which has low resistivity and improved migration resistance without using reducing gases of hydrogen or the like. <P>SOLUTION: When the electronegativity of a material for a wiring pattern 31 composed of TiN composing a selected area to form a Cu wiring pattern 32 on a substrate 51 is defined as Xs, the electronegativity of a material composing an interlayer insulating film 29 composed of SiO<SB>2</SB>which is a non-selected area not to form the Cu wiring pattern 32 is defined as Xn and the electronegativity of an organic metal material for forming the Cu wiring pattern 32 is defined as Xm, a material which satisfies a relational expression of Xs<Xn<Xm is selected and the Cu wiring pattern 32 is formed by the dismutation of the organic metal material. <P>COPYRIGHT: (C)2004,JPO

Description

【００７４】
本実施の形態１においては、上述の有機銅材料５であるＣｕ（ｈｆａｃ）ＴＭＶＳを約４０℃に加熱することにより、このＣｕ（ｈｆａｃ）ＴＭＶＳの蒸気圧を高めてガス化する。その後に、有機銅ガス（ガス化された有機銅材料５）を、窒素ガス１０をキャリアガスとして、図１に示した反応チャンバ１内に導入する。このとき、有機銅ガスの通過する配管経路および反応チャンバ１の内壁は、有機銅ガスの吸着・凝集によるＣｕの析出を抑制するために、４０〜６０℃程度に温度が保たれている。
【００７５】
成膜条件を、有機銅材料５の供給流量０．１ｇ／ｍｉｎ、キャリア窒素ガス流量２８０ＳＣＣＭ、反応チャンバ１内の圧力１３３Ｐａ（１Ｔｏｒｒ）、反応チャンバ１内の基板２の温度を１６０℃として、８分間の成膜を行った。この結果、基板２上のＡｌからなる配線パターン上には、膜厚１６０ｎｍのＣｕ薄膜が形成された。また、酸化ケイ素（ＳｉＯ_２）膜からなる基板２の表面上にはＣｕ薄膜の堆積はなく、それぞれ独立に形成されたＣｕ配線パターン間での電気的なリーク（ｌｅａｋ）は確認されなかった。
【００７６】
なお、本実施の形態１では、反応チャンバ１内の基板２の温度を１６０℃としたが、反応チャンバ１内の基板２の温度は１２０℃〜１９０℃とするのが好ましい。
【００７７】
これは、前記温度が１２０℃よりも低い場合には、前記の成膜反応に必要とされる、反応のための活性化エネルギー（ａｃｔｉｖａｔｉｏｎ　ｅｎｅｒｇｙ）が高く、選択領域における上記反応が良好に進まないためである。一方、前記１９０℃を越える場合には、前記の成膜反応に必要とされる、反応のための活性化エネルギーが低くなり、選択領域だけでなく非選択領域でも上記反応が起こるようになって、成膜の選択性が低下するためである。
【００７８】
以上のように、基板５１上のＣｕ配線パターン３２を形成する選択領域（Ａｌ）の電気陰性度Ｘｓは１．５である。Ｃｕ配線パターン（３２）を形成しない非選択領域（ＳｉＯ_２）の電気陰性度Ｘｎは約２．９３である。Ｃｕ配線パターン（３２）を形成するための有機銅材料５の電気陰性度Ｘｍは３．２４である。このように、Ｘｓ＜Ｘｎ＜Ｘｍなる関係式を満たす材料を選択しているので、有機金属材料の不均化反応によりＣｕ配線パターン３２を形成することができる。
【００７９】
実施の形態２
本発明の実施の形態２では、Ｃｕ薄膜による金属配線の形成方法の好ましい例として、薄膜トランジスタ５５を備えた表示装置、例えばアクティブマトリックス型の液晶表示装置５０の素子側基板５１の作製について説明する。
【００８０】
図３及び図４は、液晶表示装置５０を示している。なお、図３及び図４では、補助容量を省略して示している。
【００８１】
液晶表示装置５０は、図３及び図４に示すように、前後一対の透明基板５１，５２、液晶層（図示せず）、画素電極５４、薄膜トランジスタ（ＴＦＴ：Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ）５５、走査配線５６、信号配線５７、走査配線端子５８、信号配線端子５９、及び対向電極６２等を備えている。
【００８２】
一対の透明基板５１，５２としては、例えば一対のガラス基板を用いることができる。以下、透明基板５１，５２をガラス基板という。これらガラス基板５１，５２は、図示しない枠状のシール材を介して接合されている。液晶層は、一対のガラス基板５１，５２の間のシール材により囲まれた領域に設けられている。
【００８３】
図４に示すように、一対のガラス基板５１，５２のうちの一方のガラス基板、例えば後側のガラス基板（素子側基板）５１の内面には、複数の透明な画素電極５４と、複数の薄膜トランジスタ５５と、走査配線５６と、信号配線５７と、複数の走査配線端子５８と、複数の信号配線端子５９とが設けられている。
【００８４】
画素電極５４は、行方向および列方向にマトリックス状に設けられている。薄膜トランジスタ５５は、複数の画素電極５４とそれぞれ電気的に接続されている。走査配線５６及び信号配線５７は、複数の薄膜トランジスタ５５と電気的に接続されている。複数の走査配線端子５８及び複数の信号配線端子５９は、基体５１の一端縁部および一側縁部にそれぞれ形成されている。
【００８５】
走査配線５６は、画素電極５４の行にそれぞれ沿わせて設けられている。これら走査配線５６の一端は、後側基体５１の一側縁部に設けられた複数の走査配線端子５８にそれぞれ接続されている。複数の走査配線端子５８はそれぞれ信号駆動回路６０に接続されている。
【００８６】
一方、信号配線５７は、画素電極５４の列にそれぞれ沿わせて設けられている。これら信号配線５７の一端は、後側基体５１の一端縁部に設けられた複数の信号配線端子５９にそれぞれ接続されている。複数の信号配線端子５９はそれぞれ画像信号回路６１に接続されている。
【００８７】
他方のガラス基板である前側のガラス基板（対向基板）５２の内面には、複数の画素電極５４に対向する一枚膜状の透明な対向電極６２が設けられている。また、前側のガラス基板５２の内面には、複数の画素電極５４と対向電極６２とが互いに対向する複数の画素部に対応させてカラーフィルタを設けてもよい。また、前側のガラス基板５２の内面には、前記画素部の間の領域に対応させて遮光膜を設けてもよい。
【００８８】
一対のガラス基板５１，５２の外側には、図示しない偏光板が設けられている。また、透過型の液晶表示装置５０では、後側のガラス基板５１の後側に図示しない面光源が設けられている。なお、液晶表示装置５０は、反射型或いは半透過反射型としてもよい。
【００８９】
図４は、本実施の形態２の液晶表示装置の薄膜トランジスタ５５付近の断面図を示している。
【００９０】
２２はＳｉＯ_２からなるバッファ層、２３は多結晶Ｓｉ（Ｐｏｌｙ−Ｓｉ：ｐｏｌｙｓｉｌｉｃｏｎ）膜、２６はソース領域、２７はドレイン領域、２８はチャネル領域、２４はＳｉＯ_２からなるゲート絶縁膜、２５はＡｌからなるゲート電極、２９はＳｉＯ_２からなる層間絶縁膜、４０は薄膜トランジスタ５５のソース領域２６と画素電極５４とを接続させる電気配線、３１はＴｉＮからなる配線パターン、３２はＣｕ配線パターンである。
【００９１】
以下、本実施の形態２の薄膜トランジスタの製造工程を説明する。本実施の形態２の薄膜トランジスタは、図５（ａ）〜（ｅ）に示すような工程によって作製される。
【００９２】
まず、図５（ａ）に示すように、絶縁性基板であるガラス基板５１上にバッファ層２２として酸化ケイ素（ＳｉＯ_２）膜を形成する。バッファ層２２の膜厚は、例えば膜厚１５０ｎｍである。このバッファ層２２上に、基板温度４３０℃で減圧ＣＶＤ法により、膜厚８０ｎｍのアモルファスシリコン（α−Ｓｉ）膜を形成する。続いて、形成されたα−Ｓｉ膜に対してエキシマレーザーを用いたレーザーアニール（ｌａｓｅｒ　ａｎｎｅａｌｉｎｇ）による結晶化を行う。これにより、多結晶シリコン（Ｐｏｌｙ−Ｓｉ）膜が形成される。多結晶シリコン膜を得るための結晶化工程としては、６００℃程度の熱アニールによる固相成長工程を用いて行ってもよい。次に、得られた多結晶シリコン膜に対して、スピンコート法等により感光性樹脂であるレジスト膜を塗布する。そして、フォトリソグラフィー工程によって所定の島状の形状となるようにレジスト膜（ｒｅｓｉｓｔ−ｆｉｌｍ）の露光・現像を行う。ＣＦ_４ガスを用いたドライエッチング（ｄｒｙ　ｅｔｃｈｉｎｇ）法によって、図５（ａ）に示すような島状の多結晶Ｓｉ膜２３を形成する。
【００９３】
次に、島状の多結晶Ｓｉ膜２３を含むガラス基板５１上の全面に対して、ＳｉＯ_２膜からなるゲート絶縁膜２４を膜厚１００ｎｍで形成する。この成膜は、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌ　Ｏｒｔｈｏｓｉｌｉｃａｔｅ）を原料としたプラズマＣＶＤ法によって行う。なお、ゲート絶縁膜２４のパターニングは行わない（図示省略）。
【００９４】
続いて、ゲート電極を形成するために、Ａｌ膜をスパッタ法により成膜する。フォトリソグラフィー法およびエッチング法を用いてＡｌ膜を加工し、図５（ｂ）に示すようなゲート電極２５を形成する。このゲート電極２５をマスクとして、多結晶Ｓｉ膜２３に対して、例えばリン（Ｐ）のような不純物３３をドーピング（ｄｏｐｉｎｇ）する。ゲート電極２５をマスクとすることによって、不純物はゲート電極２５下部以外の多結晶Ｓｉ膜２３中に注入されることとなる。これにより、自己整合型のソース領域２６およびドレイン領域２７が形成される。また、不純物注入後、活性化処理を行う。このことによって、図５（ｂ）に示すようなｎ^＋型のソース・ドレイン領域２６、２７および不純物が導入されていないチャネル領域２８が形成される。
【００９５】
次に、膜厚３００ｎｍのＳｉＯ_２膜をプラズマＣＶＤ法により堆積し、図５（ｃ）に示すように、層間絶縁膜２９を形成する。続いて、フォトリソグラフィー法およびエッチング法を用いて、前記ソース・ドレイン領域２６、２７上部の層間絶縁膜２９およびゲート絶縁膜２４を除去する。これにより、図５（ｃ）に示すようなソース・ドレイン領域２６、２７に達するコンタクトホール（ｃｏｎｔａｃｔ−ｈｏｌｅ）３０を形成する。続いて、コンタクトホール３０内および層間絶縁膜２９上部に窒化チタン（ＴｉＮ）膜を膜厚２００ｎｍで成膜する。そして、コンタクトホール３０内および所望の配線部分を覆うように、フォトリソグラフィー法を用いてレジスト膜を形成する。その後に、エッチング法によって図５（ｄ）に示すように、ＴｉＮ膜からなる配線パターン３１を形成する。
【００９６】
次に、図１に示したＣｕ−ＣＶＤ装置を用いて、図５（ｄ）に示した薄膜トランジスタ５５を備えた基板２１上にＣｕの選択成膜を行う。
【００９７】
このとき、コンタクトホール３０およびその周辺に形成されたＴｉＮ膜からなる配線パターン３１の電気陰性度は２．５である。また、ＳｉＯ_２膜からなる層間絶縁膜２９および有機銅材料５であるＣｕ（ｈｆａｃ）ＴＭＶＳとの電気陰性度の関係は、
ＴｉＮ＜ＳｉＯ_２＜Ｃｕ（ｈｆａｃ）＝２．５＜２．９３＜３．２４
となる。
【００９８】
そのため、基板２１上に導入された有機銅分子は、配線パターン３１上に優先的に吸着する。そして、基板２１上に導入された有機銅分子は、前述の不均化反応による分解反応を起こす。これによって、図５（ｅ）に示すように、配線パターン３１上に選択的にＣｕ配線パターン３２が形成される。
【００９９】
成膜条件を、有機銅材料５の供給流量を０．００８ｇ／ｍｉｎ、キャリアガス流量５０ＳＣＣＭ、成膜圧力２６６Ｐａ（２Ｔｏｒｒ）、基板温度１７０℃として、１５分間の成膜を行った。このとき、得られたＣｕ配線パターン３２の膜厚は約２００ｎｍであった。また、層間絶縁膜２９上にはＣｕ薄膜の堆積は見られず、形成されたＣｕ配線パターン３２間でのリークも確認されなかった。
【０１００】
以上のように、基板５１上のＣｕ配線パターン３２を形成する選択領域を構成するＴＩＮからなる配線パターン３１の材料の電気陰性度Ｘｓは２．５である。Ｃｕ配線パターン３２を形成しない非選択領域であるＳｉＯ_２の電気陰性度Ｘｎは約２．９３である。Ｃｕ配線パターン３２を形成するための有機銅材料５の電気陰性度Ｘｍは３．２４である。このように、Ｘｓ＜Ｘｎ＜Ｘｍなる関係式を満たす材料を選択しているので、有機金属材料の不均化反応によりＣｕ配線パターン３２を形成することができる。
【０１０１】
したがって、本実施の形態２の方法によれば、信号配線５７及び薄膜トランジスタ５５と画素電極５４とを接続させる電気配線４０を素子側基板５１の一方の面に選択的に形成することができる。
【０１０２】
なお、実施の形態２では、信号配線５７及び薄膜トランジスタ５５と画素電極５４とを接続させる電気配線４０を実施の形態１のようにしてＣｕ薄膜によって選択的に形成したが、走査電極５６も同様にしてＣｕ薄膜によって選択的に形成してもよい。
【０１０３】
上記のように、本実施の形態１、２の金属配線の形成方法は、選択領域に金属配線を選択的に形成する金属配線の形成方法であって、前記選択領域を構成する材料の持つ電気陰性度をＸｓ、少なくとも前記選択領域の近傍であって前記金属配線を形成しない非選択領域を構成する材料の持つ電気陰性度をＸｎ、前記金属配線を形成するための有機金属材料の持つ電気陰性度をＸｍとした場合に、それぞれの電気陰性度が、Ｘｓ＜Ｘｎ＜Ｘｍの関係を有することを特徴とする（請求項１）。また、前記有機金属材料の不均化反応により前記金属配線を形成することを特徴とする（請求項２）。さらに、前記金属配線を、前記有機金属材料を用いた化学気相成長法によるＣｕ薄膜により形成することを特徴とする（請求項３）。
【０１０４】
すなわち、それぞれの材料の電気陰性度が、Ｘｓ＜Ｘｎ＜Ｘｍの関係を満たすように、これらの材料を選択することによって、成膜種である有機金属材料を選択領域に対して優先的に吸着させることができる（請求項１）。また、有機金属材料を選択領域に対して優先的に吸着させることによって、Ｃｕの有機金属材料の不均化反応を選択領域で優先的に進行させることができる（請求項２）。さらに、選択性が良好な化学気相成膜法によるＣｕ薄膜の選択成膜が実現できる（請求項３）。また、金属配線を構成する金属膜を化学気相成長法（ＣＶＤ法）を用いて形成することにより、上記電気陰性度の違いによる有機金属材料の吸着の差異を利用した選択成膜を行うことができる。また、低抵抗、かつ、耐マイグレーション性に優れたＣｕからなる配線を、困難なエッチング法を用いることなく、選択的に形成することが可能となる（請求項３）。
【０１０５】
したがって、本実施の形態１、２の金属配線の形成方法によれば、水素等の還元性ガスを用いることなく、有機金属材料の不均化反応により、ガラス基板上にＣｕ薄膜からなる金属配線を選択的に形成することが可能となる。
【０１０６】
さらに、上記選択領域は、Ａｌ、Ｔｉ、Ｔａ、Ｗ、Ｓｉのうちの少なくとも１つの元素を含む導電性材料で構成されていることを特徴とする（請求項４）。非選択領域は、ＳｉＯ_２、Ｓｉ_３Ｎ_４、Ａｌ_２Ｏ_３等の酸化物、窒化物という絶縁性材料により構成されていることを特徴とする（請求項５、６）。このようにすることによって、選択領域の表面でのＣｕの有機金属材料のマイグレーションによる不均化反応を促進することができる。したがって、選択性を高めたＣｕ薄膜からなる金属配線の選択形成方法を提供することが可能となる。
【０１０７】
また、これらのことから、エッチング法を用いることなく、低抵抗かつ耐マイグレーション性に優れたＣｕからなる配線の選択形成が可能となる。したがって、ＬＳＩ、ＵＬＳＩに代表される半導体素子や液晶表示装置等の表示装置に対して、特性の優れたＣｕからなる配線を提供することが可能となる。さらには、必要部分にのみ選択的にＣｕ配線の形成が可能となることにより、成膜に必要とされるＣｕの成膜材料の利用効率が改善される。このことによって、材料コストの削減やプロセス工程の簡略化が可能なＣｕ配線の形成方法を提供できる。
【０１０８】
上記第２の実施形態によれば、マトリックス状に設けられた複数の画素電極と、前記複数の画素電極にそれぞれ接続された複数の薄膜トランジスタと、前記薄膜トランジスタを駆動するための複数の走査配線及び複数の信号配線と、を具備する表示装置を形成する方法であって、前記走査配線及び前記信号配線のうちの少なくとも一方の配線を形成する選択領域を構成する材料の持つ電気陰性度をＸｓ、前記配線を形成しない非選択領域を構成する材料の持つ電気陰性度をＸｎ、前記配線を形成するための有機金属材料の持つ電気陰性度をＸｍとした場合に、それぞれ電気陰性度が、Ｘｓ＜Ｘｎ＜Ｘｍの関係を有することを特徴とする（請求項７）。
【０１０９】
さらに、前記薄膜トランジスタと前記画素電極とは電気配線を介して接続されており、かつ、前記電気配線を形成する選択領域を構成する材料の持つ電気陰性度をＸｓ、前記電気配線を形成しない非選択領域を構成する材料の持つ電気陰性度をＸｎ、前記電気配線を形成するための有機金属材料の持つ電気陰性度をＸｍとした場合に、それぞれ電気陰性度が、Ｘｓ＜Ｘｎ＜Ｘｍの関係を有することを特徴とする（請求項８）。
【０１１０】
したがって、成膜種である有機金属材料を、走査配線、信号配線、及び電気配線等の配線が形成される選択領域に対して優先的に吸着させることができる。
【０１１１】
さらに、前記有機金属材料はＣｕもしくはＣｕを含む合金を有する有機金属材料であり、前記走査配線、前記信号配線、及び電気配線のうちの少なくとも１つの配線を前記有機金属材料の不均化反応により形成することを特徴とする（請求項９）。
【０１１２】
これにより、水素等の還元性ガスを用いることなく、Ｃｕにより、低抵抗性、耐マイグレーション性に優れた走査配線或いは信号配線を選択的に形成することができる。
【０１１３】
また、ダマシン法やスパッタ法を用いる必要がないので製造工程が簡単である。しかも、Ｃｕ薄膜を基板全面に成膜する必要がない、つまり、不要部分を除去する必要がない。したがって、低抵抗性、耐マイグレーション性に優れた走査配線或いは信号配線を備えた表示装置を簡単且つ安価に製造できる。
【０１１４】
さらに、Ｃｕ薄膜は、１Ｔｏｒｒ〜２Ｔｏｒｒといった成膜圧力下で形成することができる、したがって、特開平５−９４９７０号公報で公開されている技術と比べて減圧設備等のコストを抑制でき、表示装置を簡単且つ安価に製造できる。
【０１１５】
以上のように、本発明によれば、水素等の還元性ガスを用いることなく、低抵抗かつ耐マイグレーション性に優れた配線を選択に形成する金属配線の形成方法を提供することができる。
【０１１６】
なお、本発明を実施の形態に基づいて具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
【０１１７】
【発明の効果】
以上に説明したように、この発明によれば、水素等の還元性ガスを用いることなく、低抵抗性、耐マイグレーション性に優れた配線を選択に形成する金属配線の形成方法及び表示装置の製造方法が得られる。
【図面の簡単な説明】
【図１】本発明の実施の形態１に係るＣｕの化学気相成膜装置の概略構成図。
【図２】本発明に係るＣｕの有機金属材料による堆積反応を示す概略図。
【図３】本発明の実施の形態２に係る液晶表示装置の一部分を示す平面図。
【図４】図３の液晶表示装置の薄膜トランジスタ付近を示す断面図。
【図５】図４の薄膜トランジスタの製造方法を示す工程断面図。
【符号の説明】
２，５１…基板、５…有機金属材料、２９…層間絶縁膜、３１…配線パターン、３２…Ｃｕ配線パターン、４０…電気配線、５０…液晶表示装置（表示装置）、５４…画素電極、５５…薄膜トランジスタ、５６…走査配線、５７…信号配線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique for forming an electric wiring used for a display device represented by a liquid crystal display device or a semiconductor device such as an ULSI, and selectively forms a metal wiring made of copper or an alloy containing copper on a substrate. The present invention relates to a method for forming a metal wiring and a method for manufacturing a display device, which are suitable for the above.
[0002]
[Prior art]
In recent years, in the field of semiconductors represented by LSIs and ULSIs, studies on wiring using copper (Cu) as a wiring material have been advanced. This is because progress in miniaturization, improvement in operation speed, and the like due to improvement in the degree of integration of semiconductor devices have been progressing. That is, there is a demand for a wiring having a lower wiring resistance and a higher resistance to electro-migration, stress-migration, and the like than a wiring using aluminum (Al) conventionally used. Because it is.
[0003]
Also, in the field of display devices represented by liquid crystal display devices and the like, it is required to cope with an increase in the wiring length due to an increase in the display area and a monolithic peripheral circuit portion by incorporating additional functions. I have. As additional functions, the incorporation of a driver circuit for driving, a memory in a pixel, etc., and various processors in the future are being studied. For this reason, in the field of display devices, there is an increasing demand for low-resistance wiring as in the semiconductor field.
[0004]
As described above, Cu as the wiring material has lower resistance and better migration resistance than Al as the conventional wiring material. For this reason, Cu is expected as a next-generation wiring material, and active development is being promoted.
[0005]
However, in a combination of masking by photo-lithography and reactive ion etching (reactive ion etching) which has been used for forming a conventional fine wiring, a fine wiring using Cu is not used. Difficult to form.
[0006]
That is, the halide of Cu (halogenide) has a low vapor pressure. (Cu halides are unlikely to evaporate.) Therefore, in order to volatilize and remove Cu halides formed by the above-described etching, an etching treatment at a process temperature of 200 to 300 ° C. is required. It becomes. Therefore, it is difficult to perform fine processing by etching the Cu wiring.
[0007]
As a method of forming a fine wiring using Cu, there is a so-called damascene method. In this method, first, a wiring groove having a desired wiring pattern shape is formed in advance on an insulating film laminated on a substrate. A Cu thin film is formed all over the inside of the groove and on the insulating film so as to fill the groove. At this time, as a method of filling the groove with Cu, there are various methods such as PVD (Physical Vapor Deposition) such as sputtering, a plating method, and a CVD method using an organic metal material. Thereafter, the Cu thin film on the substrate surface is removed up to the upper end surface of the buried groove. As a method of removing the Cu thin film on the substrate surface, there are a polishing method such as a chemical mechanical polishing (CMP) and an etch-back. By doing so, the Cu thin film is left only inside the groove. In this manner, a buried Cu wiring pattern is formed (for example, see Patent Document 1).
[0008]
As another method, a method of arranging a catalyst such as Pd on a substrate in a desired wiring pattern has been attempted. In this method, a Cu wiring pattern is formed by performing electroless plating of Cu using Pd or the like formed in a pattern as a nucleus (for example, see Non-Patent Document 1).
[0009]
Further, a method of forming a desired pattern shape with a conductive substance on an insulating substrate and forming a Cu wiring by electrolytic plating using the conductive substance as an electrode has been attempted.
[0010]
[Patent Document 1]
JP-A-11-135504 (paragraphs 0014 to 0029, FIGS. 1 and 2)
[0011]
[Non-patent document 1]
H. Niino, A .; Yabe, Appl. Phys. Lett. , 63, 3527-3529 (1993).
[0012]
[Problems to be solved by the invention]
However, the above-mentioned various methods for forming fine wirings using Cu have the following problems.
[0013]
First, the above damascene method, which has been actively studied in LSI, ULSI, and the like, has the following problems.
[0014]
First, the damascene method requires a film forming step, a photolithography step, and an etching step for forming a groove-shaped wiring pattern and a via connecting the upper and lower electrodes, and the manufacturing step is complicated. .
[0015]
Second, it is necessary to increase the wiring film thickness in order to reduce the wiring resistance. However, when a groove or a via hole having a high aspect ratio is used, there is a problem in that the burying property of Cu is deteriorated.
[0016]
Third, the above-described CMP process or the like for removing unnecessary portions after forming a Cu thin film over the entire surface of the substrate has a problem that the throughput (through-put) of the process is poor.
[0017]
Fourth, a large CMP apparatus has been conventionally developed for a wafer size of about 12 inches (inch) in diameter for manufacturing LSI and ULSI. However, with respect to application to a display device, a substrate used for manufacturing a liquid crystal display device or the like is a large substrate having a size of about 1 to 1.5 m square, and has a larger area than a manufacturing application such as LSl. A polishing step with good accuracy such as flatness is required. Therefore, it is difficult to put the damascene method to practical use for a display device.
[0018]
In addition, in the case of using a large-sized substrate such as a liquid crystal display device, there is a problem that the price of a product is increased even if the entire surface can be polished by the above-mentioned CMP or removed by an etching method. That is, the Cu thin film portion used as the wiring in the liquid crystal display device is very small as compared with the area of the glass substrate. Therefore, most of the formed Cu thin film is removed. As a result, the efficiency of using Cu, which is expensive as a material, becomes very poor.
[0019]
In addition, the selective film forming method using plating has the following problems.
[0020]
First, a selective film formation method using plating has a track record for a relatively large pattern size such as a printed circuit board. However, when a wiring pattern having a line width on the order of several μm required for LSl, ULSl or a display device is formed, the composition of the plating solution, the instability of the process due to aging, the film quality due to the incorporation of impurities, and the like. There is a problem in terms of the decrease in the amount of the solution and the effect of the chemical solution on the environment.
[0021]
Secondly, the method of depositing a Cu thin film on a conductive portion by plating after formation of a base wire is excellent in selectivity, but requires a step of covering a conductive surface of an unnecessary part and a step of forming a base conductive pattern for energization. It becomes. Therefore, there is a problem that the process steps are complicated and the cost is high.
[0022]
Third, the Cu thin film formed by the plating method tends to take in impurities and the like, and the electric resistance of the Cu thin film immediately after the film formation tends to increase. Therefore, the plating method requires annealing at a relatively high temperature after film formation. Because of this annealing treatment, it is difficult to apply the plating method to a large-area display device or the like from the viewpoint of heat resistance of the substrate.
[0023]
Fourth, unlike a conventional wafer substrate for manufacturing an LSI or the like, a substrate used for manufacturing a display device is a large substrate of 1 to 1.5 m square as described above. The plating apparatus for uniformly treating the wastewater uses a very large and large amount of chemicals, and there is a concern about the burden on the environment.
[0024]
In recent years, attempts have been made to selectively form a Cu thin film by a Cu-CVD method using an organic metal material in order to solve the above problem. For example, JP-A-6-236879 discloses the following method. First, metal particles made of a Vll group metal having a high hydrogen dissociation ability, such as Pd, are selectively deposited on a base metal film having a desired wiring shape. On the other hand, an organic metal material of Cu is introduced using hydrogen gas (hydrogen gas) as a carrier gas to form a film by thermal decomposition.
[0025]
According to this method, hydrogen of the carrier gas introduced together with the Cu organometallic material is dissociated on the Vll group metal having high hydrogen dissociation ability. This hydrogen causes a preferential reduction reaction of the organometallic material of Cu on the Group VIII metal. As a result, Cu nucleation and film growth selectively proceed on the Vll group metal, and a Cu thin film is selectively formed on the substrate.
[0026]
However, in this method, it is necessary to use hydrogen gas as a carrier gas in order to promote a reduction action on the Vll group metal on the substrate surface. In this case, the reduction reaction of the organometallic material proceeds by the hydrogen gas present in the gas phase. Then, nucleation of Cu occurs on the surface other than the selected region due to the reactant generated in the gas phase. For this reason, there is a problem that the selectivity of the Cu film is deteriorated.
[0027]
Further, since a step of selectively depositing a Vll group metal on the underlying metal is required, the number of process steps increases. Furthermore, since hydrogen gas is required for the process, there is also a problem that costs for abatement equipment after the film forming process are required to secure the safety of the process.
[0028]
Further, as a method of selectively forming a thin film, the following technique is disclosed in Japanese Patent Application Laid-Open No. 5-94970. A semiconductor substrate in which a first material having high electronegativity and a second material having low electronegativity are mixed on the surface is used. WF ₆ Or MoF ₆ Metal halide or a source gas comprising a halide gas of the metal and H ₂ , CO, SiH ₄ To produce a mixed gas containing a reducing gas. When an electric field is applied to the semiconductor substrate in the mixed gas atmosphere, the source gas is excited by the discharge. Thereby, a metal film of W or Mo is selectively and directionally deposited on the second material.
[0029]
According to this technique, it is described that a selectivity of a metal film can be obtained by a correlation between a source gas and a material constituting a substrate surface. However, since plasma by discharge is used to decompose the raw material gas, a metal nucleus (seed), which is a decomposition product of the raw material gas, is formed in the gas phase, and this is non-selectively deposited on the substrate. It's easy to do. Therefore, there is a problem that the selective deposition of the metal film is easily hindered.
[0030]
Further, in the film formation using a reducing gas, the film formation rate can be improved, but the decomposition and deposition of the source gas progresses by the reaction in the gas phase. From this, similarly, improvement in the selectivity of film formation is likely to be hindered.
[0031]
Furthermore, in this technology, H ₂ And SiH ₄ It is necessary to use a reducing gas that has a danger of flammability or ignition. For this reason, there is a problem that the abatement equipment for ensuring the safety of the process is reflected in the total process cost.
[0032]
It is known that W and Mo have a higher specific resistance than Cu and Al (W: 5.6 × 10 ^-6 Ωcm (300K), Mo: 5.2 × 10 ^-6 Ωcm (0 ° C.), Cu: 1.7 × 10 ^-6 Ωcm (20 ° C.), Al: 2.6 × 10 ^-6 Ωcm (20 ° C.)). Such a film made of W or Mo having a large specific resistance is generally applicable to a wiring that connects layers vertically stacked in an LSI or IC. However, a wiring made of W or Mo is not suitable as a scanning wiring or a signal wiring provided in a display device typified by a liquid crystal display device.
[0033]
That is, in a display device such as a liquid crystal display device, the larger the specific resistance of the scanning wiring and the signal wiring, the longer the delay time. Therefore, when a wiring made of W or Mo is used as a scanning wiring or a signal wiring, a favorable switching operation cannot be performed.
[0034]
Further, in the present technology, the WF ₆ 5 × 10 gas ^-4 There is an inconvenience that the pressure must be reduced to a low pressure such as Torr and introduced into the vacuum vessel.
[0035]
The present invention has been made in view of the above problems, and without using a reducing gas such as hydrogen, a low resistance, a method of forming a metal wiring for selectively forming a wiring excellent in migration resistance and a display device. It is intended to provide a manufacturing method.
[0036]
[Means for Solving the Problems]
The method for forming a metal wiring in the present invention is a method for forming a metal wiring for selectively forming a metal wiring in a selected region,
Xs is the electronegativity of the material forming the selected region, Xn is the electronegativity of the material forming the non-selected region that is at least near the selected region and does not form the metal wiring, and is used to form a metal wiring. When the electronegativity of the organic metal material is Xm, each electronegativity is
Xs <Xn <Xm, that is, (Xm−Xn) <(Xm−Xs)
This is achieved by selecting these materials so as to satisfy the following relational expression (claim 1).
[0037]
The electronegativity is a physical property value indicating electron donating property, and refers to the ability of an atom to attract electrons when forming a chemical bond. That is, in the present invention, the electronegativity of a material is a physical property value indicating the electron donating property of the material, and indicates the ability to attract electrons when the material undergoes a chemical reaction. In the present invention, the electronegativity of each material may be an arithmetic mean of the electronegativities of constituent elements for convenience. Then, between the two materials having different electronegativities, a material having a small electronegativity provides an electron donation to a material having a high electronegativity.
[0038]
Here, for example, a case where an organic metal material (organic Cu material) for forming a Cu thin film is introduced to the substrate surface will be described.
[0039]
The organometallic material dissociates and adsorbs on the substrate surface by exchanging charges with the substrate surface. Then, the two organometallic molecules (organic Cu molecules) in the organometallic material adsorbed on the substrate surface migrate on the substrate surface. This causes a so-called disproportionation reaction, which is an oxidation-reduction reaction between two organometallic molecules. Then, metal atoms (Cu) in the organic gold material precipitate. It is known that a metal film is deposited by this reaction (JATT Norman, et. Al., Thin Solid Films, Vol. 262 (1995), pp 46-51).
[0040]
The disproportionation reaction (also referred to as unequal change) means that two or more molecules of a single substance undergo mutual oxidation and reduction reactions to produce two or more substances. Here, as described below, between two organometallic molecules (organic Cu molecules in the above example), a metal atom reduced by the occurrence of an oxidation / reduction reaction and an oxidized organometallic compound are generated, A metal thin film is formed.
[0041]
From this, according to the present invention, when an organometallic material is introduced into a region including a selected region and a non-selected region, the surface of the selected region has a large difference in magnitude relationship from the surface of the organic metal due to the electronegativity relationship. Electrons are exchanged with the material. That is, the organometallic material attracts electrons from the surface of the selected area. Therefore, the dissociative adsorption of the organometallic material by the transfer of electrons can be preferentially and selectively performed in the selected area.
[0042]
The method for forming a metal wiring in the present invention may be achieved by forming a metal wiring by a disproportionation reaction of an organometallic material (claim 2).
[0043]
In the method for forming a metal wiring of the present invention, as described above, there are many organometallic molecules that contribute to a disproportionation reaction for forming a thin film in a selected region where organometallic molecules are preferentially adsorbed. . Therefore, the reaction proceeds preferentially in the selected area. This makes it possible to selectively perform nucleation of atoms and deposition of a thin film in a selected region.
[0044]
On the other hand, on the surface of the non-selected region, the difference in electronegativity with the organometallic material is small due to the above relationship. Therefore, when compared with the surface of the selected region, the adsorption of the organometallic material to the surface of the non-selected region is less likely to occur. Therefore, the amount of organometallic molecules contributing to the disproportionation reaction for forming a thin film is small, and the result is that deposition is unlikely to occur.
[0045]
As a result, on the surface of the selected region and the surface of the non-selected region, a difference in time until the deposition of a thin film of Cu or the like due to the above-described disproportionation reaction is started, that is, a so-called latency period occurs. By increasing the incubation period, selectivity for depositing a thin film of Cu or the like is improved.
[0046]
Therefore, each material is selected so that the electronegativity of each of the selected region, the non-selected region, and the organometallic material satisfies the above relationship, and metal wiring is formed by a disproportionation reaction of the organometallic material. Thereby, the organometallic material can be preferentially deposited on the selected region. Therefore, it is possible to form a metal wiring having good selectivity (claim 2).
[0047]
In the method of forming a metal wiring according to the present invention, the metal film forming the metal wiring may be formed by a chemical vapor deposition (CVD) method.
[0048]
By doing so, it is possible to selectively form metal wiring by utilizing the difference in the adsorption of the organometallic material due to the difference in the electronegativity. Further, it is possible to selectively obtain a wiring made of Cu or the like having low resistance and excellent migration resistance without using difficult etching (claim 3).
[0049]
In the method for forming a metal wiring according to the present invention, the selected region can be made of a conductive material containing at least one element of Al, Ti, Ta, W, and Si (claim 4). In addition, the non-selected area is made of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ It can be made of an insulating material such as oxide / nitride.
[0050]
By doing so, the organometallic molecules adsorbed on the surface of the selected region made of the conductive material are bonded to the electrons in the conductive material on the surface of the selected region. Therefore, migration of the organometallic molecules on the surface of the conductive material, which is the selected region, is facilitated, so that a disproportionation reaction or the like for forming a thin film of Cu or the like easily occurs.
[0051]
On the other hand, on the surface of the insulating material which is a non-selected region, adsorption of organometallic molecules necessary for forming metal wiring is smaller than in the selected region. In addition, charge transfer on the surface is difficult due to the insulating property. Therefore, the above-described movement of the organometallic molecule is unlikely to occur. Therefore, even if the organometallic molecules are adsorbed, the progress of the disproportionation reaction or the like hardly proceeds.
[0052]
As a result, the difference (the difference in the incubation period) until the start of the thin film formation in the selected / non-selected region becomes larger. From this, it is possible to form the metal wiring with high selectivity (claims 4, 5, and 6).
[0053]
The method for manufacturing a display device according to the present invention includes a plurality of pixel electrodes provided in a matrix, a plurality of thin film transistors respectively connected to the plurality of pixel electrodes, a plurality of scanning wirings for driving the thin film transistors, and a plurality of signals. A method of manufacturing a display device comprising:
Xs is the electronegativity of the material forming the selected region forming at least one of the scanning wiring and the signal wiring, and Xn is the electronegativity of the material forming the non-selected region not forming the wiring. When the electronegativity of the organometallic material for forming the wiring is Xm, each electronegativity is
Xs <Xn <Xm, that is, (Xm−Xn) <(Xm−Xs)
This is achieved by selecting these materials so as to satisfy the following relational expression (claim 7).
[0054]
Further, when the present invention is applied to a method for manufacturing a display device in which a thin film transistor and a pixel electrode are connected via an electric wiring, the electronegativity of a material forming a selected region where an electric wiring is formed is represented by Xs, When the electronegativity of the material constituting the non-selection region where the wiring is not formed is Xn and the electronegativity of the organometallic material for forming the electric wiring is Xm, each electronegativity is
Xs <Xn <Xm, that is, (Xm−Xn) <(Xm−Xs)
These materials may be selected so as to satisfy the following relationship.
[0055]
With this configuration, the dissociation and adsorption of the organometallic material can be preferentially and selectively formed in the selected area where the scanning wiring, the signal wiring, the electric wiring, and the like are formed (claims 7 and 8).
[0056]
Further, the organic metal material may be an organic metal material having Cu or an alloy containing Cu, and at least one of the scanning wiring, the signal wiring, and the electric wiring may be formed by a disproportionation reaction of the organic metal material. Good. (Claim 9).
[0057]
By doing so, the wiring such as the scanning wiring, the signal wiring, and the electric wiring can be selectively formed of Cu having high migration resistance (claim 9).
[0058]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0059]
Embodiment 1
First Embodiment As a first embodiment of the present invention, a method for forming a metal wiring made of Cu on an insulating substrate such as glass will be described below.
[0060]
First, silicon oxide (SiO 2) serving as a buffer layer is formed on an alkali-free glass substrate used for a liquid crystal display device or the like. ₂ ) A film is formed to a thickness of 150 nm by a plasma CVD method. As a substrate to be used, a thermal oxide film (SiO 2) may be formed on a substrate made of single crystal silicon. ₂ A substrate provided with an insulating film such as a film may be used.
[0061]
Next, an aluminum (Al) film having a thickness of 100 nm is formed over the entire surface of the insulating substrate by a sputtering method. Thereafter, the Al film is processed into a wiring pattern having a predetermined shape by using a photolithography process and an etching process. By this step, the surface of the selected region made of Al and the SiO 2 ₂ The surface of the non-selection region made of the film is formed.
[0062]
In this embodiment, the electronegativity of a material composed of two or more elements is defined as the arithmetic average of the constituent elements. Therefore, the electronegativity of the surface of the selected region made of Al is 1.5, and SiO ₂ The electronegativity of a material composed of two elements is about 2.93.
[0063]
Subsequently, the insulating substrate 2 on which the wiring pattern made of Al is formed is introduced into the reaction chamber (chamber) 1 of the chemical vapor deposition apparatus (CVD apparatus) shown in FIG.
[0064]
Here, the CVD apparatus shown in FIG. 1 will be described. A substrate 2 for forming a Cu thin film is placed on a stage 3 in a reaction chamber 1 which is a vacuum vessel shown in FIG. The interior of the reaction chamber 1 is evacuated by a vacuum exhaust system (not shown) using a turbo-molecular-pump or the like until a predetermined ultimate vacuum degree is reached. Subsequently, the substrate 2 introduced into the reaction chamber 1 is heated to a predetermined reaction temperature by a heater (not shown) provided in the stage 3. The heating of the substrate 2 at this time is not limited to the heater, and may be performed by lamp annealing or the like.
[0065]
An organometallic material 5 made of a liquid organometallic compound of Cu is extruded by a nitrogen gas 10 from a raw-materials-tank 4. The introduction amount of the organic metal material 5 is controlled by the liquid flow meter 6. Thereafter, the organic metal material 5 is heated by the vaporizer 7 to increase the vapor pressure of the organic metal material 5. Thereby, the organometallic material 5 becomes an organometallic gas composed of vaporized organometallic molecules. The organometallic gas is introduced into the reaction chamber 1 through the gas introducing section 8 together with the nitrogen gas 10 as a carrier gas. In addition, 9 is a gas discharge part.
[0066]
Examples of the Cu organometallic material 5 include trimethylvinylsilylhexafluoroacetylacetonate copper (Cu (hfac) TMVS: hfac = Hexafluoroacetic acid acetate (CF), which is a monovalent complex of Cu. ₃ COCHCOCF ₃ ), TMVS = Trimethylvinylsilane (CO ₅ H ₁₂ Si)).
[0067]
FIG. 2 schematically shows the decomposition / deposition reaction of the Cu organometallic material 5.
[0068]
An organic metal material (hereinafter referred to as an organic copper material) 5 introduced into the reaction chamber 1 in FIG. 1 comes into contact with the substrate 2 disposed in the reaction chamber 1 and dissociates and adsorbs on the surface of the substrate 2. Then, the organic copper material 5 forms a Cu thin film by the following reaction due to the thermal energy of the heated substrate 2.
[0069]
Step 1: In a gas phase (g), TMVS in an organic copper molecule is decomposed and desorbed to form an intermediate product (Cu (hfac) (g)) having a monovalent copper oxide atom. Is adsorbed on the surface of the substrate 2 (a).
[0070]
2Cu ⁺¹ (Hfac) TMVS (g) → 2Cu ⁺¹ (Hfac) (g) + TMVS (g) ↑ → 2Cu ⁺¹ (Hfac) (a)
Step 2: The two organic copper molecules adsorbed on the surface of the substrate 2 are brought into contact with the surface of the substrate 2 by migration. Thereby, the disproportionation reaction by two organic copper molecules progresses. One reduced copper atom Cu (s) is deposited and deposited to form a Cu thin film. The bivalently oxidized reaction products formed at the same time are removed by desorbing from the surface of the substrate 2 into the gas phase.
[0071]
2Cu ⁺¹ (Hfac) (a) → Cu ^(O) (S) + Cu ⁺² (Hfac) ₂ (G)
In the above reaction, the electronegativity of Cu (hfac), which is an organic copper molecule adsorbed on the surface of the substrate 2, is 3.24 when defined as the arithmetic mean of the constituent elements, similarly to the above. From this, Al constituting the selected region on the surface of the substrate 2 and SiO constituting the non-selected region ₂ The relationship between electronegativity and
Al <SiO ₂ <Cu (hfac) = 1.5 <2.93 <3.24
It becomes. As a result, electrons are donated from the Al surface between Al, which is the selected region, and the organic copper molecules according to the magnitude relationship of electronegativity. Therefore, the adsorption of the organic copper molecules Cu (hfac) on the surface of the substrate 2 proceeds efficiently.
[0072]
Table 1 is a table showing the electronegativities of the elements.
[0073]
[Table 1]

[0074]
In the first embodiment, Cu (hfac) TMVS, which is the above-mentioned organic copper material 5, is heated to about 40 ° C., thereby increasing the vapor pressure of Cu (hfac) TMVS to gasify it. Thereafter, an organic copper gas (a gasified organic copper material 5) is introduced into the reaction chamber 1 shown in FIG. 1 using the nitrogen gas 10 as a carrier gas. At this time, the temperature of the piping route through which the organic copper gas passes and the inner wall of the reaction chamber 1 is maintained at about 40 to 60 ° C. in order to suppress the deposition of Cu due to the adsorption and aggregation of the organic copper gas.
[0075]
The film formation conditions are as follows: the supply flow rate of the organic copper material 5 is 0.1 g / min, the carrier nitrogen gas flow rate is 280 SCCM, the pressure in the reaction chamber 1 is 133 Pa (1 Torr), and the temperature of the substrate 2 in the reaction chamber 1 is 160 ° C. A minute was formed. As a result, a 160 nm thick Cu thin film was formed on the wiring pattern made of Al on the substrate 2. In addition, silicon oxide (SiO ₂ ) No Cu thin film was deposited on the surface of the substrate 2 made of a film, and no electric leak (leak) between independently formed Cu wiring patterns was observed.
[0076]
In the first embodiment, the temperature of the substrate 2 in the reaction chamber 1 is set to 160 ° C., but the temperature of the substrate 2 in the reaction chamber 1 is preferably set to 120 ° C. to 190 ° C.
[0077]
This is because when the temperature is lower than 120 ° C., the activation energy required for the film formation reaction is high, and the reaction in the selected region does not proceed well. That's why. On the other hand, when the temperature exceeds 190 ° C., the activation energy for the reaction required for the film forming reaction is reduced, and the reaction occurs not only in the selected region but also in the non-selected region. This is because the selectivity of film formation is reduced.
[0078]
As described above, the electronegativity Xs of the selected region (Al) where the Cu wiring pattern 32 is formed on the substrate 51 is 1.5. Non-selection area (SiO 2) where the Cu wiring pattern (32) is not formed ₂ ) Has an electronegativity Xn of about 2.93. The electronegativity Xm of the organic copper material 5 for forming the Cu wiring pattern (32) is 3.24. As described above, since the material satisfying the relational expression of Xs <Xn <Xm is selected, the Cu wiring pattern 32 can be formed by the disproportionation reaction of the organometallic material.
[0079]
Embodiment 2
In the second embodiment of the present invention, as a preferred example of a method for forming a metal wiring using a Cu thin film, a description will be given of the production of a display device including a thin film transistor 55, for example, an element-side substrate 51 of an active matrix liquid crystal display device 50.
[0080]
3 and 4 show the liquid crystal display device 50. FIG. 3 and 4, the auxiliary capacitance is omitted.
[0081]
As shown in FIGS. 3 and 4, the liquid crystal display device 50 includes a pair of front and rear transparent substrates 51 and 52, a liquid crystal layer (not shown), a pixel electrode 54, a thin film transistor (TFT: Thin Film Transistor) 55, and scanning wiring 56. , Signal wiring 57, scanning wiring terminal 58, signal wiring terminal 59, counter electrode 62, and the like.
[0082]
As the pair of transparent substrates 51 and 52, for example, a pair of glass substrates can be used. Hereinafter, the transparent substrates 51 and 52 are referred to as glass substrates. These glass substrates 51 and 52 are joined via a frame-shaped sealing material (not shown). The liquid crystal layer is provided in a region surrounded by a sealing material between the pair of glass substrates 51 and 52.
[0083]
As shown in FIG. 4, a plurality of transparent pixel electrodes 54 and a plurality of transparent pixel electrodes 54 are provided on the inner surface of one of the pair of glass substrates 51 and 52, for example, the rear glass substrate (element-side substrate) 51. A thin film transistor 55, a scanning wiring 56, a signal wiring 57, a plurality of scanning wiring terminals 58, and a plurality of signal wiring terminals 59 are provided.
[0084]
The pixel electrodes 54 are provided in a matrix in the row direction and the column direction. The thin film transistor 55 is electrically connected to each of the plurality of pixel electrodes 54. The scanning wiring 56 and the signal wiring 57 are electrically connected to the plurality of thin film transistors 55. The plurality of scanning wiring terminals 58 and the plurality of signal wiring terminals 59 are formed on one end and one side of the base 51, respectively.
[0085]
The scanning lines 56 are provided along the rows of the pixel electrodes 54, respectively. One end of each of the scanning wirings 56 is connected to a plurality of scanning wiring terminals 58 provided on one side edge of the rear substrate 51. The plurality of scanning wiring terminals 58 are connected to the signal driving circuit 60, respectively.
[0086]
On the other hand, the signal lines 57 are provided along the columns of the pixel electrodes 54, respectively. One end of each of the signal wirings 57 is connected to a plurality of signal wiring terminals 59 provided on one edge of the rear substrate 51. The plurality of signal wiring terminals 59 are connected to the image signal circuit 61, respectively.
[0087]
On the inner surface of the front glass substrate (counter substrate) 52, which is the other glass substrate, a single film-shaped transparent counter electrode 62 facing the plurality of pixel electrodes 54 is provided. Further, a color filter may be provided on the inner surface of the front glass substrate 52 so as to correspond to a plurality of pixel portions where the plurality of pixel electrodes 54 and the counter electrode 62 face each other. Further, a light shielding film may be provided on the inner surface of the front glass substrate 52 so as to correspond to the region between the pixel portions.
[0088]
A polarizing plate (not shown) is provided outside the pair of glass substrates 51 and 52. In the transmissive liquid crystal display device 50, a surface light source (not shown) is provided behind the rear glass substrate 51. The liquid crystal display device 50 may be of a reflective type or a transflective type.
[0089]
FIG. 4 is a sectional view showing the vicinity of the thin film transistor 55 of the liquid crystal display device according to the second embodiment.
[0090]
22 is SiO ₂ Buffer layer 23, a polycrystalline Si (Poly-Si: polysilicon) film, 26 a source region, 27 a drain region, 28 a channel region, and 24 a SiO ₂ , A gate electrode 25 made of Al, and 29 a SiO ₂ The reference numeral 40 denotes an electric wiring for connecting the source region 26 of the thin film transistor 55 and the pixel electrode 54; 31 denotes a wiring pattern of TiN; and 32 denotes a Cu wiring pattern.
[0091]
Hereinafter, the manufacturing process of the thin film transistor according to the second embodiment will be described. The thin film transistor according to the second embodiment is manufactured by the steps shown in FIGS.
[0092]
First, as shown in FIG. 5A, silicon oxide (SiO 2) is formed as a buffer layer 22 on a glass substrate 51 which is an insulating substrate. ₂ ) Form a film. The thickness of the buffer layer 22 is, for example, 150 nm. An amorphous silicon (α-Si) film having a thickness of 80 nm is formed on the buffer layer 22 at a substrate temperature of 430 ° C. by a low pressure CVD method. Subsequently, crystallization is performed on the formed α-Si film by laser annealing using an excimer laser. Thereby, a polycrystalline silicon (Poly-Si) film is formed. As a crystallization step for obtaining a polycrystalline silicon film, a solid phase growth step by thermal annealing at about 600 ° C. may be used. Next, a resist film which is a photosensitive resin is applied to the obtained polycrystalline silicon film by spin coating or the like. Then, the resist film (resist-film) is exposed and developed so as to have a predetermined island shape by a photolithography process. CF ₄ An island-shaped polycrystalline Si film 23 as shown in FIG. 5A is formed by a dry etching method using a gas.
[0093]
Next, the entire surface of the glass substrate 51 including the island-shaped polycrystalline Si film 23 is ₂ A gate insulating film 24 made of a film is formed with a thickness of 100 nm. This film formation is performed by a plasma CVD method using TEOS (Tetraethyl Orthosilicate) as a raw material. Note that the gate insulating film 24 is not patterned (not shown).
[0094]
Subsequently, an Al film is formed by a sputtering method in order to form a gate electrode. The Al film is processed by photolithography and etching to form a gate electrode 25 as shown in FIG. Using the gate electrode 25 as a mask, the polycrystalline Si film 23 is doped with an impurity 33 such as, for example, phosphorus (P). By using the gate electrode 25 as a mask, impurities are implanted into the polycrystalline Si film 23 other than below the gate electrode 25. Thus, a self-aligned source region 26 and a drain region 27 are formed. After the impurity implantation, an activation process is performed. As a result, n as shown in FIG. ⁺ The source / drain regions 26 and 27 of the mold and the channel region 28 into which impurities are not introduced are formed.
[0095]
Next, a 300 nm thick SiO ₂ A film is deposited by a plasma CVD method, and an interlayer insulating film 29 is formed as shown in FIG. Subsequently, the interlayer insulating film 29 and the gate insulating film 24 on the source / drain regions 26 and 27 are removed by photolithography and etching. Thus, a contact-hole 30 reaching the source / drain regions 26 and 27 as shown in FIG. 5C is formed. Subsequently, a 200 nm-thick titanium nitride (TiN) film is formed in the contact hole 30 and on the interlayer insulating film 29. Then, a resist film is formed by photolithography so as to cover the inside of the contact hole 30 and a desired wiring portion. Thereafter, as shown in FIG. 5D, a wiring pattern 31 made of a TiN film is formed by an etching method.
[0096]
Next, using the Cu-CVD apparatus shown in FIG. 1, selective Cu film formation is performed on the substrate 21 provided with the thin film transistor 55 shown in FIG. 5D.
[0097]
At this time, the electronegativity of the contact hole 30 and the wiring pattern 31 formed of a TiN film formed around the contact hole 30 is 2.5. In addition, SiO ₂ The electronegative relationship between the interlayer insulating film 29 made of a film and Cu (hfac) TMVS as the organic copper material 5 is as follows.
TiN <SiO ₂ <Cu (hfac) = 2.5 <2.93 <3.24
It becomes.
[0098]
Therefore, the organic copper molecules introduced on the substrate 21 are preferentially adsorbed on the wiring pattern 31. Then, the organic copper molecules introduced onto the substrate 21 undergo a decomposition reaction due to the disproportionation reaction described above. As a result, as shown in FIG. 5E, the Cu wiring pattern 32 is selectively formed on the wiring pattern 31.
[0099]
Film formation was performed for 15 minutes at a supply flow rate of the organic copper material 5 of 0.008 g / min, a carrier gas flow rate of 50 SCCM, a film formation pressure of 266 Pa (2 Torr), and a substrate temperature of 170 ° C. At this time, the thickness of the obtained Cu wiring pattern 32 was about 200 nm. Further, no Cu thin film was deposited on the interlayer insulating film 29, and no leak was observed between the formed Cu wiring patterns 32.
[0100]
As described above, the electronegativity Xs of the material of the wiring pattern 31 made of TIN that forms the selected region for forming the Cu wiring pattern 32 on the substrate 51 is 2.5. SiO which is a non-selection area where the Cu wiring pattern 32 is not formed ₂ Has an electronegativity Xn of about 2.93. The electronegativity Xm of the organic copper material 5 for forming the Cu wiring pattern 32 is 3.24. As described above, since the material satisfying the relational expression of Xs <Xn <Xm is selected, the Cu wiring pattern 32 can be formed by the disproportionation reaction of the organometallic material.
[0101]
Therefore, according to the method of the second embodiment, the signal wiring 57 and the electric wiring 40 for connecting the thin film transistor 55 to the pixel electrode 54 can be selectively formed on one surface of the element-side substrate 51.
[0102]
In the second embodiment, the signal wiring 57 and the electric wiring 40 for connecting the thin film transistor 55 to the pixel electrode 54 are selectively formed of the Cu thin film as in the first embodiment, but the scanning electrode 56 is similarly formed. May be selectively formed by a Cu thin film.
[0103]
As described above, the method for forming a metal wiring according to the first and second embodiments is a method for forming a metal wiring for selectively forming a metal wiring in a selected region. Xs is the negativity, Xn is the electronegativity of a material constituting a non-selection region which is at least near the selected region and does not form the metal wiring, and X is the electronegativity of an organometallic material for forming the metal wiring. When the degree is Xm, each electronegativity has a relation of Xs <Xn <Xm (claim 1). Further, the metal wiring is formed by a disproportionation reaction of the organometallic material (claim 2). Further, the metal wiring is formed by a Cu thin film by a chemical vapor deposition method using the organometallic material (claim 3).
[0104]
That is, by selecting these materials so that the electronegativity of each material satisfies the relationship of Xs <Xn <Xm, the organometallic material as a film-forming species is preferentially adsorbed to the selected region. (Claim 1). Further, by causing the organometallic material to be preferentially adsorbed to the selected region, the disproportionation reaction of the organometallic material of Cu can be preferentially advanced in the selected region. Furthermore, selective deposition of a Cu thin film by a chemical vapor deposition method having good selectivity can be realized. In addition, by forming a metal film constituting a metal wiring by using a chemical vapor deposition method (CVD method), a selective film formation utilizing a difference in adsorption of an organic metal material due to the difference in electronegativity is performed. Can be. Further, it is possible to selectively form a wiring made of Cu having low resistance and excellent migration resistance without using a difficult etching method.
[0105]
Therefore, according to the method of forming the metal wiring of the first and second embodiments, the metal wiring formed of the Cu thin film on the glass substrate by the disproportionation reaction of the organometallic material without using a reducing gas such as hydrogen. Can be selectively formed.
[0106]
Further, the selection region is made of a conductive material containing at least one element of Al, Ti, Ta, W, and Si (claim 4). The non-selected area is SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ It is characterized by being made of an insulating material such as oxide or nitride such as (Claims 5 and 6). By doing so, the disproportionation reaction due to the migration of the Cu organometallic material on the surface of the selected region can be promoted. Therefore, it is possible to provide a method for selectively forming a metal wiring made of a Cu thin film with enhanced selectivity.
[0107]
From these facts, it is possible to selectively form a wiring made of Cu having low resistance and excellent migration resistance without using an etching method. Therefore, it is possible to provide a wiring made of Cu with excellent characteristics for a semiconductor device typified by LSI and ULSI and a display device such as a liquid crystal display device. Further, since the Cu wiring can be selectively formed only in the necessary portions, the utilization efficiency of the Cu film forming material required for the film formation is improved. As a result, it is possible to provide a method for forming a Cu wiring that can reduce material costs and simplify a process step.
[0108]
According to the second embodiment, a plurality of pixel electrodes provided in a matrix, a plurality of thin film transistors respectively connected to the plurality of pixel electrodes, a plurality of scanning wirings for driving the thin film transistors, and a plurality of And a signal wiring, wherein the electronegativity of a material constituting a selected region forming at least one of the scanning wiring and the signal wiring is Xs, When the electronegativity of the material forming the non-selection region where the wiring is not formed is Xn and the electronegativity of the organometallic material for forming the wiring is Xm, the electronegativity is Xs <Xn. <Xm. (Claim 7)
[0109]
Further, the thin film transistor and the pixel electrode are connected via an electric wiring, and the electronegativity of a material forming a selected region for forming the electric wiring is Xs, and the non-selection without forming the electric wiring is performed. Assuming that the electronegativity of the material constituting the region is Xn and the electronegativity of the organometallic material for forming the electric wiring is Xm, the electronegativity has a relationship of Xs <Xn <Xm. (Claim 8).
[0110]
Therefore, the organometallic material, which is a film-forming species, can be preferentially adsorbed to a selected region where a wiring such as a scanning wiring, a signal wiring, and an electric wiring is formed.
[0111]
Further, the organometallic material is an organometallic material having Cu or an alloy containing Cu, and at least one of the scanning wiring, the signal wiring, and the electrical wiring is formed by a disproportionation reaction of the organometallic material. It is characterized by being formed (claim 9).
[0112]
This makes it possible to selectively form a scan wiring or a signal wiring excellent in low resistance and migration resistance by using Cu without using a reducing gas such as hydrogen.
[0113]
Further, the manufacturing process is simple because there is no need to use a damascene method or a sputtering method. Moreover, it is not necessary to form a Cu thin film on the entire surface of the substrate, that is, it is not necessary to remove unnecessary portions. Therefore, it is possible to easily and inexpensively manufacture a display device having a scanning wiring or a signal wiring excellent in low resistance and migration resistance.
[0114]
Further, the Cu thin film can be formed under a film forming pressure of 1 Torr to 2 Torr. Therefore, the cost of the decompression equipment and the like can be suppressed as compared with the technology disclosed in Japanese Patent Application Laid-Open No. 5-94970, and the display device Can be easily and inexpensively manufactured.
[0115]
As described above, according to the present invention, it is possible to provide a method for forming a metal wiring for selectively forming a wiring having low resistance and excellent migration resistance without using a reducing gas such as hydrogen.
[0116]
Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various changes can be made without departing from the spirit of the present invention. .
[0117]
【The invention's effect】
As described above, according to the present invention, without using a reducing gas such as hydrogen, a method of forming a metal wiring for selectively forming a wiring having low resistance and excellent migration resistance and manufacturing of a display device A method is obtained.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a Cu chemical vapor deposition apparatus according to a first embodiment of the present invention.
FIG. 2 is a schematic diagram showing a deposition reaction of an organometallic material of Cu according to the present invention.
FIG. 3 is a plan view showing a part of the liquid crystal display device according to Embodiment 2 of the present invention.
FIG. 4 is a sectional view showing the vicinity of a thin film transistor of the liquid crystal display device of FIG. 3;
FIG. 5 is a process sectional view illustrating the method for manufacturing the thin film transistor of FIG.
[Explanation of symbols]
2, 51: substrate, 5: organometallic material, 29: interlayer insulating film, 31: wiring pattern, 32: Cu wiring pattern, 40: electric wiring, 50: liquid crystal display device (display device), 54: pixel electrode, 55 ... thin film transistor, 56 ... scanning wiring, 57 ... signal wiring

Claims (9)

A method of forming a metal wiring for selectively forming a metal wiring in a selection region,
Xs represents the electronegativity of the material constituting the selected region,
The electronegativity of a material constituting at least a non-selection region near the selection region and not forming the metal wiring is Xn,
When the electronegativity of the organometallic material for forming the metal wiring is Xm,
A method for forming a metal wiring (30, 57), wherein the electronegativity has a relationship of Xs <Xn <Xm. 2. The method for forming a metal wiring according to claim 1, wherein the metal wiring is formed by a disproportionation reaction of the organometallic material. 2. The method for forming a metal wiring according to claim 1, wherein the metal wiring is formed by a Cu film formed by a chemical vapor deposition method using the organic metal material. 4. The method according to claim 1, wherein the material forming the selected region includes at least one of Al, Ti, Ta, W, and Si. It is made of a material. 4. The method according to claim 1, wherein the material forming the non-selected region is an insulating material made of an oxide or a nitride. 6. The method for forming a metal wiring according to claim 5, wherein the insulating material made of oxide or nitride is SiO ₂ , Si ₃ N ₄ , or Al ₂ O ₃ . A display device comprising: a plurality of pixel electrodes provided in a matrix; a plurality of thin film transistors respectively connected to the plurality of pixel electrodes; a plurality of scanning wirings and a plurality of signal wirings for driving the thin film transistors. The method of manufacturing
Xs represents the electronegativity of a material forming a selected region for forming at least one of the scanning wiring and the signal wiring.
The electronegativity of the material forming the non-selection area where the wiring is not formed is Xn
When the electronegativity of the organometallic material for forming the wiring is Xm,
A method for manufacturing a display device, wherein each electronegativity has a relationship of Xs <Xn <Xm. A method for manufacturing a display device according to claim 7,
The thin film transistor and the pixel electrode are connected via an electric wiring, and the electronegativity of a material constituting a selected region forming the electric wiring is Xs, and a non-selected region not forming the electric wiring is Xs. When the electronegativity of the constituent material is Xn and the electronegativity of the organometallic material for forming the electric wiring is Xm, the electronegativity has a relationship of Xs <Xn <Xm. It is characterized. The method for manufacturing a display device according to claim 8, wherein the organometallic material is an organometallic material having Cu or an alloy containing Cu, and the scan wiring, the signal wiring, and the electric wiring are included. At least one wiring is formed by a disproportionation reaction of the organometallic material.

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