JP2004047533A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor devices in which the number of steps and the manufacturing cost can be reduced even if a plurality of devices having different structures and functions are formed as a single chip. <P>SOLUTION: The memthod for manufacturing a semiconductor devices comprises a first step for forming a first layer polysilicon film and then forming the polysilicon electrodes 202a and 204a of a first device and the polysilicon electrodes 201a and 203a of a third device; a second step for forming an insulating film 6 composed of a silicon oxide film and a silicon nitride film; a third step for exposing a semiconductor substrate by removing the insulating film 6 except for regions for forming the first and third devices; and a fourth step for forming a second layer polysilicon film on the semiconductor substrate from which the insulating film 6 is removed and then forming the polysilicon electrodes 201b and 203b of the third device and the polysilicon electrodes 205b-208b of the second devices 205-208 on the semiconductor substrate from which the insulating film 6 is removed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a plurality of devices having different structures and functions, such as memory and logic devices, are formed on a single chip.
[0002]
[Prior art]
When a plurality of devices having different structures and functions such as a memory device and a logic device are formed on a single chip in order to increase the functionality of a semiconductor device, the components of each device are greatly different. They cannot be formed at the same time.
[0003]
Therefore, for example, a manufacturing method is conceivable in which a memory device is formed first, a protective film is formed to protect the previously formed memory device, and then a logic device is formed.
[0004]
[Problems to be solved by the invention]
However, if a protective film is formed to protect a previously formed device from destruction or the like, the number of steps for manufacturing a semiconductor device increases, which leads to an increase in manufacturing cost.
[0005]
Therefore, an object of the present invention is to provide a semiconductor device which can reduce the number of steps and therefore the manufacturing cost even when a plurality of devices having different structures and functions, such as memory and logic devices, are formed on one chip. It is to provide a manufacturing method.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1, wherein a first and a second device having one polysilicon electrode, and two layers of a first polysilicon electrode and a second polysilicon electrode are provided. A method of manufacturing a semiconductor device, comprising: forming a third device having a single layer on one semiconductor substrate, wherein a first-layer polysilicon film is formed on the entire surface of the semiconductor substrate, and the first-layer polysilicon film is patterned. Forming a first device polysilicon electrode comprising a first-layer polysilicon film and a third device first polysilicon electrode; and forming a first device polysilicon electrode and a third device first electrode. A second step of forming an insulating film serving as a protective film over the entire surface of the semiconductor substrate on which the polysilicon electrode is formed, and the first device and the third device on the semiconductor substrate; A third step of exposing the semiconductor substrate by removing the insulating film other than the region where the chair is formed, and forming silicon oxide on the semiconductor substrate where the insulating film other than the region where the first and third devices are formed is removed. After that, a second polysilicon film is formed on the entire surface of the semiconductor substrate, and the second polysilicon film is patterned to form a second polysilicon film of the third device comprising the second polysilicon film. And a fourth step of forming a polysilicon electrode of the second device on the semiconductor substrate from which the insulating film has been removed.
[0007]
According to this, the insulating film serving as a protective film formed in the middle of the process serves as a component of the third device, and serves as a protective film of the first device using the previously formed first-layer polysilicon film as an electrode. Can be used for the subsequent steps. Therefore, a new protective film is not required in the present invention, so that even when a plurality of devices as described above are formed on one semiconductor substrate, the number of steps is not increased and the manufacturing cost can be reduced. .
[0008]
The invention according to claim 2 and claim 3, wherein the insulating film serving as the protective film is a two-layer film of a silicon oxide film / a silicon nitride film and a three-layer film of a silicon oxide film / a silicon nitride film / a silicon oxide film. Which is one of the following.
[0009]
These insulating films are used as a component of the third device and as a protective film of the first device using the previously formed first-layer polysilicon film as an electrode, and as an oxidation prevention and an etching stopper in a later step. Thus, it can function effectively.
[0010]
The invention according to claim 4 is characterized in that the insulating film serving as the protective film is formed by thermal oxidation or CVD. The insulating film formed by thermal oxidation or CVD is used as a protective film for the components of the third device and the first device using the previously formed first-layer polysilicon film as an electrode. By using it as an etching stopper, it can function effectively.
[0011]
The method according to claim 5, wherein, in patterning the second-layer polysilicon film in the fourth step, when etching the second-layer polysilicon film, the polysilicon around the first device formed in the first step is etched. Is characterized by removing the etching residue.
[0012]
According to this, since the first device formed earlier is protected by the insulating film formed in the second step, the second-layer polysilicon film can be excessively etched, and the periphery of the first device can be etched. The etching residue of the polysilicon can be removed. Therefore, a special step of removing the etching residue is not required, so that the number of steps and the manufacturing cost can be reduced.
[0013]
According to a sixth aspect of the present invention, there is provided a fifth step of forming an oxide film on the semiconductor substrate before the first step, and a sixth step of forming an interlayer insulating film on the semiconductor substrate after the fourth step. A seventh step of forming a contact hole in the interlayer insulating film by etching for wiring to the first device and the third device, and a fifth step around a formation site of the contact hole before forming the interlayer insulating film. An eighth step of removing the formed oxide film and the insulating film formed in the second step to expose the semiconductor substrate is provided.
[0014]
According to this, when the interlayer insulating film is etched to form the contact hole, the oxide film and the insulating film around the contact hole forming portion are removed in advance. Therefore, it is possible to suppress the formation of cavities in the oxide film due to a difference in etching rate between the insulating film and the oxide film, which is considered when a contact hole is formed by simultaneously etching three layers of the interlayer insulating film, the insulating film, and the oxide film. it can. For this reason, at the time of forming the contact, it is possible to prevent the coverage of the wiring barrier metal from being reduced due to the presence of the cavity, and it is possible to suppress the occurrence of alloy spikes.
[0015]
The invention according to claims 7 and 8 is characterized in that the first device and the second device are either a MOS transistor having a polysilicon gate electrode or a polysilicon resistor element.
[0016]
The invention according to claim 9 is characterized in that the third device is one of a double-layer gate transistor having a double-layer polysilicon gate electrode and a capacitor having a double-layer polysilicon electrode. I have.
[0017]
By combining the devices according to claims 7 to 9 and forming a plurality of devices having different structures and functions on a single semiconductor substrate by the manufacturing method of the present invention, different functions such as memory and logic can be combined into one semiconductor device. It can be demonstrated in.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
[0019]
FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 in which a plurality of devices 201 to 208 having different functions such as a memory device and a logic device are formed on one semiconductor substrate 1. Each device shown in the memory formation region of FIG. 1 shows a double-layer gate transistor 201, a MOS transistor 202, a capacitor 203, and a resistor 204. The devices shown in the logic formation region of FIG. 1 are N-channel MOS transistors 205 and 207 and P-channel MOS transistors 206 and 208. Reference numeral 211 denotes a high-voltage CMOS transistor, and reference numeral 212 denotes a low-voltage CMOS transistor. Is shown.
[0020]
In FIG. 1, a double-layer gate transistor 201 in a memory formation region is a memory transistor used for an EPROM, an EEPROM, a flash memory, and the like, and has a double polysilicon layer of a floating gate 201a and a control gate 201b. The capacitive element 203 also includes two polysilicon layers, a lower electrode 203a and an upper electrode 203b. Reference numeral 6 denotes an insulating film, which functions as a separation film between the floating gate 201a and the control gate 201b in the case of the two-layer gate transistor 201, and a dielectric between the lower electrode 203a and the upper electrode 203b in the capacitor 203. Functioning as On the other hand, the MOS transistor 202 and the resistance element 204 each have a gate electrode 202a and a polysilicon resistor 204a formed of a single polysilicon layer. Further, the MOS transistors 205 to 208 in the logic formation region also have gate electrodes 205b to 208b formed of a single polysilicon layer.
[0021]
Note that an interlayer insulating film (BPSG), wiring, a protective film, and the like are actually formed on the semiconductor device 100, but these are not shown for simplicity.
[0022]
Next, using the semiconductor device 100 shown in FIG. 1 as an example, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2A to 2E and FIGS. 3A and 3B. This will be described with reference to FIG.
[0023]
First, as shown in FIG. 2A, a p-type silicon (Si) substrate 1 having a predetermined impurity concentration is prepared, and a thermal oxide film 2 is formed on the Si substrate 1. Thereafter, ion implantation is performed using a resist having a predetermined opening as a mask to form a well region. In FIG. 2A, three well regions 31, 32, and 33 are shown in the logic formation region. Reference numerals 31 and 33 are n-type well regions, and reference numeral 32 is a p-type well region. For forming the n-type well regions 31 and 33, for example, phosphorus (P) is ion-implanted at a rate of 1 × 10 ¹³ / cm ² . To form the p-type well region 32, for example, boron (B) is ion-implanted at a rate of 3.4 × 10 ¹³ / cm ² . By performing a high-temperature heat treatment (drive-in) at 1170 ° C. after the ion implantation, the formation of the well regions 31, 32, and 33 is completed. Although not shown for simplicity, a similar well region may be appropriately formed in the memory formation region.
[0024]
Next, as shown in FIG. 2B, a channel stopper 41 and a LOCOS 42 are formed as follows.
[0025]
A nitride film (Si ₃ N ₄ ) 40 (not shown) is formed on the entire surface of the Si substrate 1 by the low pressure CVD method. Next, after opening the LOCOS formation site of the nitride film 40 by photoetching, for example, boron (B) is ion-implanted into a predetermined opening at a rate of 7 × 10 ¹³ / cm ² to form the channel stopper 41. I do. Thereafter, the LOCOS 42 is formed by thermally oxidizing the Si substrate 1 exposed at the opening of the nitride film 40.
[0026]
Next, as shown in FIG. 2C, a gate oxide film 50 and a first polysilicon layer 5 are formed as follows.
[0027]
The nitride film 40 and the previously formed oxide film 2 are removed, and a new thermal oxidation is performed to form a gate oxide film 50. Further, a predetermined portion of the gate oxide film 50 (a region where the floating gate 201a of the two-layer gate transistor 201 is to be formed) is etched and thermally oxidized again to form a thin tunnel oxide film 51. The tunnel oxide film 51 is subjected to a nitridation and reoxidation process to improve the life. Next, a polysilicon film 5 is deposited and patterned into a predetermined shape by photoetching. Thus, the floating gate 201a of the two-layer gate transistor 201, the gate electrode 202a of the MOS transistor 202, the lower electrode 203a of the capacitor 203, and the polysilicon resistor 204a of the resistor 204 shown in FIG. 1 are formed.
[0028]
Next, as shown in FIG. 2D, after forming the source 201s and the drain 201d of the two-layer gate transistor 201 and the source 202s and the drain 202d of the MOS transistor 202, the insulating film 6 is formed.
[0029]
The insulating film 6 is a three-layer film including a silicon oxide film / a silicon nitride film / a silicon oxide film. The insulating film 6 is a component functioning as a separation film between the floating gate 201a and the control gate 201b in the two-layer gate transistor 201 shown in FIG. 1, and a lower electrode 203a in the capacitor 203. It is a component that functions as a dielectric between the upper electrodes 203b. In addition, the insulating film 6 plays a role of protecting the already completed MOS transistor 202 and the resistive element 204 in the subsequent steps. The insulating film 6 having these two roles may be a two-layer film composed of a silicon oxide film / a silicon nitride film. Further, the insulating film 6 may be formed by any of thermal oxidation and CVD.
[0030]
When the double-layer gate transistor 201 is a memory transistor of an EEPROM and the MOS transistor 202 is a selection and transistor of the EEPROM, the drain 201d of the double-layer gate transistor 201 and the source 202s of the MOS transistor 202 are connected. The formation of the source 201s and the drain 201d of the double-layer gate transistor 201 and the formation of the source 202s and the drain 202d of the MOS transistor 202 are performed simultaneously with the formation of the source and the drain of the MOS transistors 205, 206, 207, and 208 in the logic formation region described later. Is also good.
[0031]
Next, as shown in FIG. 2E, the insulating film 6 in the logic formation region and the previously formed gate oxide film 50 are removed by photoetching to form a gate oxide film 52 and a gate oxide film 53. In forming the gate oxide films 52 and 53, the semiconductor substrate 1 is thermally oxidized. At this time, the MOS transistor 202, the resistor element 204, the floating gate 201a, and the lower electrode 203a in the memory formation region are formed of an insulating film 6 is not oxidized. In FIG. 2E, the insulating film 6 around the lower electrode 203a is also removed. This is because, since the area of the lower electrode 203a is large, even if the surrounding insulating film 6 is removed, it is hardly affected by the subsequent steps. Of course, the insulating film 6 around the lower electrode 203a may be left.
[0032]
Next, as shown in FIG. 3A, a second-layer polysilicon film 7 is deposited and patterned into a predetermined shape by photoetching.
[0033]
Thus, the control gate 201b of the two-layer gate transistor 201 and the upper electrode 203b of the capacitor 203 shown in FIG. The gate electrodes 205b, 206b, 207b, 208b of the MOS transistors 205, 206, 207, 208 shown in FIG. 1 are formed in the logic formation region. In this photo-etching, the MOS transistor 202, the resistor element 204, the floating gate 201a, and the lower electrode 203a which have already been completed in the memory formation region are not etched because the insulating film 6 serves as an etching stopper.
[0034]
When patterning the second-layer polysilicon film 7, the second-layer polysilicon film 7 can be over-etched to remove the etching residue of the polysilicon around the previously formed first device. .
[0035]
For example, as shown in FIG. 4, after the gate electrode 202a of the MOS transistor 202 shown in FIG. 1 is formed with the first polysilicon 5 and the second polysilicon film 7 is normally etched, the two An etching residue 71 of the polysilicon film 7 of the eye is generated. This is because the second-layer polysilicon film 7 is thick at the step due to the step of the gate electrode 202a.
[0036]
In the manufacturing method according to the present invention, when the second polysilicon film 7 is etched, the MOS transistor 202 is protected by the insulating film 6. Thus, the second polysilicon film 7 can be excessively etched using the etching condition (preferably dry etching) in which the etching speed of the polysilicon film is higher than the etching speed of the insulating film 6. The remaining 71 can be removed. Therefore, a special process (mask, additional etching) for removing the etching residue 71 is not required, so that the number of processes and the manufacturing cost can be reduced.
[0037]
Finally, as shown in FIG. 3B, the sources 205s, 206s, 207s, 208s and the drains 205d, 206d, 207d, 208d of the MOS transistors 205, 206, 207, 208 are formed, and are shown in FIG. The semiconductor device 100 is completed.
[0038]
In the above-described method for manufacturing the semiconductor device 100, the insulating film 6 formed in the step shown in FIG. 2D serves as a component of the two-layer gate transistor 201 and the capacitor 203, and the MOS transistor formed earlier. It acts as a protective film of the resistive element 202 and the resistive element 204 in subsequent steps. Therefore, since a new protective film is not required in the present invention, the number of steps increases even when a plurality of devices 201 to 208 having different structures and functions are formed on one semiconductor substrate 1 as shown in FIG. Therefore, the manufacturing cost can be reduced.
[0039]
Further, different functions such as a memory and a logic can be exhibited by one semiconductor device 100.
[0040]
Actually, after the step of FIG. 3B, formation of an interlayer insulating film (BPSG) by CVD, reflow of the interlayer insulating film, formation of contacts and wirings, and formation of a protective film, Finally completed. In the method of manufacturing a semiconductor device according to the present invention, when a contact and a wiring are formed on the MOS transistor 202 formed earlier via an interlayer insulating film, a preferred method is as follows.
[0041]
As shown in FIG. 5A, when the previously formed insulating film 6 and gate insulating film 50 are etched simultaneously with the interlayer insulating film 8 to form a contact hole, the etching speed of the insulating film 6 is reduced. Since the etching rate is lower than 50, the cavity 80 is easily formed. When such a cavity 80 is formed, when the barrier metal 91 for the Al wiring 92 is formed, the coverage is reduced at the cavity 80, and finally, the Al of the wiring 92 diffuses into the Si substrate 1, It is possible that the alloy spike 94 occurs.
[0042]
Therefore, as shown in FIG. 5B, the insulating film 6 and the gate insulating film 50 adjacent to the formation site of the contact 90 are removed by dry etching before the formation of the interlayer insulating film 8. Thereby, a contact hole can be formed in the interlayer insulating film 8 by wet etching without contacting the insulating film 6, and the cavity 80 is not formed. Therefore, the formation of the barrier metal 91 does not lower the coverage, and the generation of the alloy spike 94 can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a semiconductor device formed according to the present invention.
FIGS. 2A to 2E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention;
FIGS. 3A and 3B are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to the present invention.
FIG. 4 is a diagram for explaining generation of an etching residue and a method for preventing the same;
FIG. 5A is a diagram for explaining the occurrence of an alloy spike, and FIG. 5B is a diagram for explaining a method for preventing the spike.
[Explanation of symbols]
1 Silicon (Si) substrate 100 Semiconductor device 201 Double layer gate transistor 201a Floating gate 201b Control gate 202 MOS transistor 203 Capacitance element 203a Lower electrode 203b Upper electrode 204 Resistance element 204a Polysilicon resistor 205 High voltage N-channel MOS transistor 206 High voltage P-channel MOS transistor 207 Low-voltage N-channel MOS transistor 208 Low-voltage P-channel MOS transistor 211 High-voltage CMOS transistor 212 Low-voltage CMOS transistor 202a, 205b, 206b, 207b, 208b Gate electrode 5th polysilicon (film)
6 Insulating film 7 Second polysilicon (film)

Claims (9)

A method for manufacturing a semiconductor device, wherein first and second devices having one polysilicon electrode and a third device having two layers of first polysilicon electrode and second polysilicon electrode are formed on one semiconductor substrate. hand,
Forming a first-layer polysilicon film on the entire surface of the semiconductor substrate, patterning the first-layer polysilicon film, and forming a first device polysilicon electrode and a third device A first step of forming one polysilicon electrode;
A second step of forming an insulating film serving as a protective film on the entire surface of the semiconductor substrate on which the polysilicon electrode of the first device and the first polysilicon electrode of the third device are formed;
A third step of removing the insulating film other than the first device and third device formation regions on the semiconductor substrate to expose the semiconductor substrate;
After forming a silicon oxide film on the semiconductor substrate from which the insulating film other than the first and third device formation regions has been removed, a second polysilicon film is formed on the entire surface of the semiconductor substrate. Patterning a polysilicon film to form a second polysilicon electrode of the third device made of a second-layer polysilicon film and a polysilicon electrode of the second device on the semiconductor substrate from which the insulating film has been removed; A method for manufacturing a semiconductor device, comprising four steps. 2. The method according to claim 1, wherein the insulating film serving as the protective film is a two-layer film of a silicon oxide film / a silicon nitride film. 2. The method according to claim 1, wherein the insulating film serving as the protective film is a three-layer film of a silicon oxide film / a silicon nitride film / a silicon oxide film. 2. The method according to claim 1, wherein the insulating film serving as the protection film is formed by thermal oxidation or CVD. In patterning the second-layer polysilicon film in the fourth step, the second-layer polysilicon film is etched using the insulating film formed in the second step as an etching stopper to form the second-layer polysilicon film formed in the first step. 5. The method of manufacturing a semiconductor device according to claim 1, wherein an etching residue of polysilicon around one device is removed. A fifth step of forming an oxide film on the semiconductor substrate before performing the first step;
A sixth step of forming an interlayer insulating film on the semiconductor substrate after performing the fourth step;
A seventh step of forming a contact hole in the interlayer insulating film by etching for wiring to the first device and the third device;
An eighth step of exposing the semiconductor substrate by removing the oxide film formed in the fifth step and the insulating film formed in the second step around the contact hole forming portion before forming the interlayer insulating film; The method of manufacturing a semiconductor device according to claim 1, further comprising: 7. The semiconductor device according to claim 1, wherein the first device and the second device are one of a MOS transistor having a polysilicon gate electrode and a polysilicon resistor. Method. The first device and the second device are either a MOS transistor having a polysilicon gate electrode or a polysilicon resistor, and an insulating film serving as the protection film is disposed on the device. Item 4. The method for manufacturing a semiconductor device according to item 2 or 3. The third device is one of a double-layer gate transistor having a double-layer polysilicon gate electrode and a capacitor having a double-layer polysilicon electrode, and is formed on the third device in the second step. 9. The method according to claim 1, wherein an insulating film is formed on the first device and the second device.

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