JP2004039864A - Circuit board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent imperfect insulation due to crack generated in the peripheral part of a metal via in the vicinity of the surface of a circuit board, regarding the circuit board which is composed of silicon and has a plurality of penetrating holes into which the metal vias are embedded. <P>SOLUTION: The circuit board has a structure wherein a region which is positioned in the vicinity of the surface of the circuit board 1 composed of silicon and in which cracks are generated or a region in which cracks has been generated actually is eliminated, and a protective layer 6 composed of a material for relieving thermal stress between the circuit board 1 and the metal via 3 is embedded in a recess 5 which is formed by the elimination. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
[Industrial applications]
The present invention relates to a circuit board interposed between a semiconductor integrated circuit chip and a printed circuit board for mounting the semiconductor integrated circuit chip, and more particularly to a circuit board having metal vias embedded in a plurality of through holes. .
[0002]
[Prior art]
As the density and functionality of semiconductor devices increase, the number of external connection terminals in a semiconductor integrated circuit chip increases, and the external connection terminals themselves and the arrangement pitch thereof are becoming finer. In order to cope with such a situation, a method has been introduced in which external connection terminals are two-dimensionally arranged over the entire area corresponding to one main surface of a semiconductor integrated circuit chip, such as a BGA (Ball Grid Array). . In this case, it is not easy to form such a two-dimensionally arranged external terminal on the semiconductor integrated circuit chip itself with a size and a pitch that can be directly connected to the printed circuit board. It may cause deterioration. For this reason, a circuit board for converting the arrangement of the external connection terminals on the semiconductor integrated circuit chip into the arrangement of the external connection terminals on the printed circuit board has been used. The circuit board for this is called an interposer. Such a circuit board is generally connected to and integrated with a semiconductor integrated circuit chip, and is formed into a product as required, for example, in the form of a resin package. There is.
[0003]
As the above-mentioned circuit board, a board made of a resin board and a board made of a ceramic board have been conventionally used. However, a board using a silicon board has been developed. This is because the thermal expansion characteristics of the semiconductor integrated circuit chip are the same, the stress breakdown at the electrical junction is unlikely to occur, and the surface is flat like a mirror surface. This is because a terminal equivalent to the terminal can be formed.
[0004]
A circuit board made of a resin is manufactured by alternately laminating a patterned copper foil inner layer plate and a pre-leg (a sheet in which a thermosetting resin is impregnated in carbon fiber), and joining them by heating under pressure. You. Thereafter, a through hole is formed at a predetermined position by a drill, and copper plating is performed on the surface and in the through hole, and this is patterned to form a wiring circuit.
[0005]
A circuit board made of ceramic is made by punching holes in predetermined positions of a green sheet made of alumina ceramics or glass ceramics and an organic binder by punching, and copper plating is applied to the surface and the inner wall surface of the holes to form a pattern. After that, it is manufactured by laminating a plurality of green sheets under pressure and firing at a high temperature.
[0006]
The circuit board made of resin has a larger coefficient of thermal expansion than a semiconductor integrated circuit chip made of silicon. For this reason, thermal stress is applied to the joints between the semiconductor integrated circuit chip and the circuit board, usually solder bumps, due to high-temperature heat treatment in the process or heat generated during operation of the semiconductor integrated circuit, and in particular, fatigue due to repeated operation and stoppage. Therefore, the joint may be broken. The finer the joint, the more likely it is to break.
[0007]
A circuit board made of ceramics generates little thermal stress, but has variations in dimensions due to shrinkage during high-temperature firing during manufacturing, and voids remain inside. These become more remarkable as the terminals become finer, and affect the production yield and reliability.
As described above, it is difficult to miniaturize the terminals on the circuit board and increase the density of their arrangement. However, the limitation is that both the circuit board made of resin and the circuit board made of ceramic are required to form through holes. It depends on the mechanical feed pitch in drilling and punching. That is, it is impossible to form a through hole with a pitch smaller than the feed pitch amount in such machining. The mechanical feed pitch at such a limit is about 5 μm. In the case of drilling, a thin drill is easily broken, and the higher the aspect ratio of the through hole, the more serious the problem.
[0008]
In recent years, it has become possible to form grooves or holes having a high aspect ratio in a silicon substrate by Deep-RIE (Reactive Ion Etching) technology. This is RIE for applying a bias to the electrode on the substrate to be processed.
[0009]
[Problems to be solved by the invention]
Using the technique, the present inventors formed through holes having an aspect ratio of 2 and a diameter of 50 μm at a pitch of 200 μm on a silicon substrate, and formed an insulating layer on the inner wall surface of the through holes. An attempt was made to manufacture a circuit board in which a via made of copper was embedded in a through hole by plating.
[0010]
It has been observed that when the temperature of the circuit board rises as described above, electric leakage, that is, insulation failure occurs mainly between the metal via embedded in the through hole and the silicon substrate. When this was examined in detail, it was found that a concave crack had occurred inside the silicon substrate around the through hole. FIG. 6 is a sectional view of a main part of a conventional circuit board showing this state.
[0011]
As shown in FIG. 6, a metal via 103 made of, for example, copper is buried in a through hole 104 provided in a circuit board 101 made of silicon. In such a circuit board 101, cracks 105 which are deeper from the surface of the circuit board 101 as approaching the through hole 104, that is, concave in the surface, are generated in the circuit board 101 around the through hole 104. That is, it is considered that the crack 105 extends to the insulating layer 102 interposed between the metal via 103 and the circuit board 101 made of silicon, and causes insulation failure.
[0012]
In FIG. 6, the insulating layer 102 is made of, for example, SiO ₂ , is interposed between the metal via 103 and the circuit board 101 and extends to cover the surface of the circuit board 101. Further, the metal via 103 is released from the stress by the generation of the crack 105, and its length at the time of returning to room temperature becomes larger than its initial length. For example, as shown in the drawing, the metal via 103 protrudes from the surface of the circuit board 101. It becomes.
[0013]
[Means for Solving the Problems]
As a result of investigation by the inventors, it was found that the cause of the crack 105 was caused by the difference in the coefficient of thermal expansion between the circuit board 101 made of silicon and the metal via 103. That is, if the temperature of the entire circuit board 101 including the metal vias 103 rises to a certain high temperature in some process, cracks 105 are generated on both surface sides of the circuit board 101, and only one surface of the circuit board 101 is exposed. It was found that when heating was performed to increase the temperature, cracks 105 were generated only on the surface side.
[0014]
Therefore, the process temperature should be as low as possible, but there is a limit. Also, if a material having a small difference in thermal expansion coefficient from a substrate made of silicon, such as tungsten, can be buried as the metal via 103, it is highly possible that the crack 105 can be prevented from being generated. However, when the diameter of the through hole 104 is as large as about 50 μm and the aspect ratio is high, a sufficient growth rate cannot be obtained by a normal tungsten growth method such as CVD (chemical vapor deposition) or sputtering, and the filling cannot be performed.
[0015]
The present invention has been made in view of the above circumstances, and is formed of silicon and embedded in each of two opposing main surfaces and a plurality of through holes provided to penetrate the two main surfaces. Metal vias, having an insulating layer interposed between each through-hole and the corresponding metal via, and at least on the one principal surface, around each metal via, extending over a predetermined range from the metal via A circuit board is provided, in which a concave portion is provided in a region, and a protective layer is embedded in the concave portion.
[0016]
That is, according to the present invention, as shown in FIG. 1, a portion where a crack is expected to occur or a portion where a crack actually occurs is removed around a metal via 3 near the surface of a circuit board 1 made of silicon. The protective layer 6 is buried in the concave portion 5 formed thereby. As the protective layer 6, a material, such as a resin, for example, which relieves thermal stress generated between the circuit board 1 and the metal via 3 is used.
[0017]
In FIG. 1, reference numeral 2 denotes an insulating layer provided between the circuit board 1 made of silicon and the metal via 3. In FIG. 1, a recess 5 is provided around metal vias 3 on both main surfaces of a circuit board 1 made of silicon, and a protective layer 6 is embedded. Further, in FIG. 1, the protective layer 6 formed on each main surface of the circuit board 1 extends over the entire corresponding main surface. However, in the present invention, recesses are formed on both main surfaces of a circuit board made of silicon, and protective layers are embedded in each of them, or the protective layer extends over the entire corresponding main surface. , Both are not required.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 is a sectional view of a main part for explaining one embodiment of a process of manufacturing a circuit board according to the present invention. First, a thermal oxide film is formed on the surface of a silicon substrate having a thickness of 625 μm, and an opening is formed in the thermal oxide film on one main surface by using a usual photolithography technique. Then, as shown in FIG. 2A, a hole 21 having a diameter of 50 μm and a depth of 150 μm was formed in the silicon substrate 20 exposed from the opening, as shown in FIG. The holes 21 are arranged in a matrix at a pitch of 223 μm, each of 60 holes vertically and horizontally.
[0019]
Next, for example, about 2 μm thick SiO ₂ covering the surface of the hole 21 is deposited by well-known plasma CVD (chemical vapor deposition), and then chromium (Cr) and copper (Cu) are respectively deposited by sputtering. 0.5 μm and 1.5 μm are sequentially deposited. The Cr and Cu serve as a seed layer when a via made of Cu described later is formed by plating. In FIG. 2B, the deposits of SiO ₂ , Cr, and Cu are collectively shown as one layer 22.
[0020]
Next, for example, a dry film (not shown) is attached to the surface of the silicon substrate 20 and is patterned to form an opening that exposes the hole 21. At this time, an opening for forming a Cu wiring is formed on the surface of the silicon substrate 20 as necessary. Using the patterned dry film as a mask, Cu is grown in the entire inside of the hole 21 by electrolytic plating using the seed layer made of Cr and Cu as an electrode. In this way, as shown in FIG. 2C, the via 23 made of Cu is buried inside the hole 21. 2 (c) to 2 (f), the layer 22 made of the SiO ₂ , Cr, Cu deposit existing inside the hole 21 is not shown.
[0021]
Then, after removing the mask made of the dry film, as shown in FIG. 2D, the other main surface of the silicon substrate 20 where the holes 21 are not formed is covered with, for example, a back grinder by the thickness of the silicon substrate 20. Is polished to about 170 μm. This polishing may be stopped before the via 23 made of Cu embedded in the hole 21 is exposed, and it is desirable that the polishing be stopped as soon as possible within a range that can be controlled in consideration of the overall uniformity.
[0022]
Next, the polished main surface of the silicon substrate 20 is selectively etched by using a well-known dry etching technique to expose a via 23 made of Cu as shown in FIG. By this etching, the thickness of the silicon substrate 20 was reduced to about 120 μm. In this dry etching, a concave portion 25 is formed on the main surface of the silicon substrate 20 around the via 23 made of Cu due to a difference in thermal expansion coefficient between the via 23 made of Cu and the silicon substrate 20.
[0023]
Next, for example, polyimide is applied to the entire main surface of the silicon substrate 20 where the vias 23 made of Cu are exposed, and this is cured. As a result, as shown in FIG. 2F, the protection layer 26 made of polyimide is embedded in the recess 25. After that, a mask (not shown) having an opening exposing a region on the via 23 is formed, and the protective layer 26 on the via 23 is selectively removed by using the RIE technique. Alternatively, the protective layer 26 may be etched back using the well-known RIE technique until the via 23 is exposed. Normally, the via 23 is stable in a state where it is protruded from the main surface of the silicon substrate 20 because the stress is released by a crack occurring in the surrounding silicon substrate 20. Therefore, the thickness of the protective layer 26 on the via 23 is smaller than the surrounding area, and if the etch back is stopped when the via 23 is just exposed, the protective layer 26 still remains on the main surface of the silicon substrate 20. .
[0024]
In the process described with reference to FIG. 2E, the following mechanism is considered to form the recess 25 around the via 23 made of Cu by dry etching of the silicon substrate 20.
First, the temperature of the silicon substrate and the metal via increases due to the dry etching, and a crack occurs in the silicon substrate around the metal via. Due to this crack, the region that becomes the concave portion is thermally separated from other portions, and becomes higher in temperature. As a result, this region is etched faster and becomes a recess.
[0025]
FIG. 3 is a schematic plan view (a) showing a plurality of vias 33 formed on one main surface of the silicon substrate 30 by the steps described with reference to FIGS. 2 (a) to 2 (e). FIG. 4B is a schematic enlarged perspective view of FIG. The dimensions and arrangement pitch of each via 33 are as described above. FIG. 3B shows a concave portion 35 generated around the via 33 due to the chipping of the silicon substrate 20.
[0026]
FIG. 4 shows a profile of the surface of the silicon substrate 30 in which the vias 33 made of Cu are buried as shown in FIG. 3B. Measured. The via 33 projects about 5 μm from the surrounding substrate surface. The recess 35 around the via 33 has a width of about several μm near the surface and reaches a depth of about 3 μm from the substrate surface.
[0027]
In the above embodiment, the concave portion is formed in the substrate around the via by utilizing the manufacturing process of the circuit substrate made of silicon. That is, in the dry etching of the polished main surface of the silicon substrate 20, the temperature of the etched main surface of the silicon substrate 20 locally rises. Therefore, on the main surface side, the expansion of the via 23 made of Cu becomes relatively large due to the difference in the coefficient of thermal expansion between the via 23 made of Cu and the silicon substrate 20, and the thermal expansion between the via 23 made of Cu and the silicon substrate 20 becomes large. Stress occurs. As a result, cracks occur in the region around the via 23 in the vicinity of the surface of the silicon substrate 20, and as shown in FIG. 2D or 3B, the recess 25 is formed around the via 23 or 33 made of Cu. Or 35 is formed.
[0028]
FIG. 5 shows a circuit board of the present invention manufactured as described above, and an electrode pad, a thin film wiring, a thin film capacitor, etc. connected to a metal via formed on the circuit board, and a semiconductor integrated circuit is formed via a solder ball. FIG. 4 is a schematic diagram showing a state where a chip is connected and mounted on a printed circuit board.
That is, as shown in FIG. 5A, a metal via 53 having a diameter of 50 .mu.m penetrating through a circuit board 50 of 20 mm square made of silicon and having a thickness of about 120 .mu.m is formed. Each is formed in a matrix at a pitch of 223 μm.
[0029]
As shown in FIG. 5B, the circuit board 50 has, on one main surface, a thin film comprising an upper electrode 58A, for example, a metal oxide high dielectric film 58B such as BST (BaSrTiO ₃ ) and a lower electrode 58C. A capacitor 58 is formed. The thin film capacitor 58 is connected to a predetermined metal via 53, usually between a ground power supply and a metal via for supplying high-voltage power.
Pads 57 connected to both ends of each via are formed on both main surfaces of the circuit board 50, and the semiconductor integrated circuit chip 200 is connected to one main surface via the pads 57 by the solder balls 59, and the other. Are connected to the printed circuit board 300 by the solder balls 59 through the pads 57 on the main surface of the printed circuit board.
[0030]
In the above embodiment, the case where the concave portion is formed in the area around the metal via on one main surface of the circuit board made of silicon and the protective layer is buried is shown, but the same applies to the other main surface of the same circuit board. It is also effective to form the concave portion and bury the protective layer.
In the case of using a method of filling a metal via having a coefficient of thermal expansion from a circuit board made of silicon to form the concave portion, one main surface of the circuit board was dry-etched as in the above embodiment. Thereafter, by performing dry etching on the other main surface, concave portions can be formed on both main surfaces.
[0031]
In the above embodiment, the concave portion was formed in the circuit board around the metal via due to the temperature rise when dry etching was performed on one main surface of the circuit board made of silicon in which the metal via was embedded. If the entire circuit board is heated in a non-oxidizing atmosphere after embedding the metal vias in the circuit board, it is needless to say that a concave portion can be formed using the difference in thermal expansion coefficient between the two. In this case, recesses are formed around the metal vias on both main surfaces of the circuit board.
[0032]
In any of the above cases, the material constituting the metal via may be a metal having a difference in coefficient of thermal expansion from a circuit board made of silicon, high conductivity, and at least heat resistance to the reflow temperature of the solder. In addition, nickel (Ni) or an alloy thereof is preferable.
As described above, when formed using the difference in the coefficient of thermal expansion between the circuit board made of silicon and the metal via embedded therein, the bottom surface of the concave portion is formed at an angle with respect to the center axis of the metal via, that is, the through hole in which the via is embedded. θ (see FIG. 1) is funnel-shaped with 0 ° <θ <90 °. The value of θ differs depending on the dimensions of the circuit board and the metal via, the physical properties including the thermal expansion characteristics of both, the heating temperature, and the like.
[0033]
The recess may be formed by another method. For example, a mask is formed on one or both main surfaces of a circuit board made of silicon to expose a region where a recess is to be formed, and wet etching, laser milling (laser beam processing), or the like is performed. In the case of isotropic etching or milling, a concave portion having a bottom surface parallel to the main surface is formed. In the case of anisotropic wet etching using a KOH solution, a concave portion having a bottom surface inclined with respect to the main surface is formed. In the above, the same effect can be obtained by using a circuit board made of glass or glass ceramic instead of the circuit board made of silicon. In this case, the insulating layer interposed between the metal via and the circuit board can be omitted.
[0034]
The present invention includes the following aspects.
(Supplementary Note 1) A substrate formed of silicon, comprising two opposing main surfaces, metal vias embedded in each of a plurality of through holes provided to penetrate the two main surfaces, An insulating layer interposed between the through-hole and the corresponding metal via, a recess provided to surround the metal via around each of the metal vias on at least one of the main surfaces, and A circuit board comprising a buried protective layer.
(Supplementary Note 2) The circuit board according to Supplementary Note 1, wherein the protective layer is made of a material that reduces thermal stress generated between the circuit board and the metal via at least in the vicinity of at least one of the main surfaces. .
(Supplementary Note 3) The supplementary note 1, wherein the protective layer extends so as to cover the entire main surface on which the concave portion is provided, and is formed so as to expose the metal via from the protective layer. The described circuit board.
(Supplementary note 4) The circuit board according to supplementary note 1, wherein the metal via is made of a metal having a coefficient of thermal expansion larger than a coefficient of thermal expansion of the circuit board in a direction perpendicular to the main surface.
(Supplementary Note 5) The circuit according to Supplementary Note 4, wherein the recess is formed using a difference between a coefficient of thermal expansion of the metal via and a coefficient of thermal expansion of the circuit board in a direction perpendicular to the main surface. Substrate manufacturing method.
(Supplementary Note 6) The circuit board according to supplementary note 1, wherein the silicon is replaced with glass, and the metal via is embedded in the through hole without the interposition of the insulating layer.
[0035]
(Supplementary note 7) The circuit board according to supplementary note 2, wherein a material of the protective layer is made of a resin.
(Supplementary Note 8) The circuit board according to supplementary note 3, wherein a thin film capacitor made of a high dielectric substance and connected between at least two of the metal vias is formed on the at least one main surface.
[0036]
(Supplementary Note 9) The circuit board according to supplementary note 4 or 1, wherein the metal via is made of copper, nickel, or an alloy thereof.
(Supplementary Note 10) The method for manufacturing a circuit board according to supplementary note 1, wherein the concave portion is formed by dry etching the at least one main surface. (Supplementary Note 11) The method for manufacturing a circuit board according to supplementary note 1, wherein the recess is formed by wet etching the at least one main surface.
[0037]
(Supplementary Note 12) The method for manufacturing a circuit board according to supplementary note 1, wherein the concave portion is formed by laser beam processing on the at least one main surface. (Supplementary Note 13) The method for manufacturing a circuit board according to supplementary note 5, wherein a polishing step is performed on the at least one main surface prior to the dry etching.
[0038]
【The invention's effect】
As is apparent from the above description, according to the present invention, it is possible to avoid an electric leak caused by a crack generated in a region around a metal via in a circuit board in which a metal via is buried in a through hole, and to achieve a fine and high A highly reliable circuit board having a dense metal via is provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a circuit board manufactured according to the present invention; FIG. 2 is a cross-sectional view of a main part in an embodiment of a circuit board manufacturing process according to the present invention; FIG. FIG. 4 is a schematic plan view showing one example, and one schematic enlarged perspective view thereof. FIG. 4 is a profile of a surface of a silicon substrate in which metal vias are embedded. FIG. 5 is an external view of a circuit substrate and a printed circuit board connecting semiconductor integrated circuit chips. FIG. 6 is a schematic view showing a state of being mounted on a circuit board. FIG. 6 is a sectional view of a main part for explaining a problem in a conventional circuit board.
1, 50, 101 circuit board,
2, 102 Insulating layer 3, 23, 33, 53, 103 Via 4, 104 Through hole 5, 25, 35 Recess 6, 26 Protective layer 20, 30 Silicon substrate 21 Hole 22 Layer 57 Pad 58 Thin film capacitor 58A Upper electrode 58B Metal Oxide high dielectric film 58C lower electrode 59 solder ball 105 crack 200 semiconductor integrated circuit chip 300 printed circuit board

Claims (5)

A substrate formed of silicon, two opposed main surfaces, a metal via embedded in each of a plurality of through holes provided to penetrate the two main surfaces, and a corresponding one of the through holes. An insulating layer interposed between the metal vias, a recess provided around the metal via on at least one of the main surfaces, and a protection embedded in the recess. A circuit board comprising: 2. The circuit board according to claim 1, wherein the protection layer is made of a material that reduces thermal stress generated between the circuit board and the metal via at least in the vicinity of the at least one main surface. 2. The circuit according to claim 1, wherein the protective layer extends so as to cover the entire main surface on which the concave portion is provided, and is formed so as to expose the metal via from the protective layer. substrate. 2. The circuit board according to claim 1, wherein the metal via is made of a metal having a coefficient of thermal expansion larger than a coefficient of thermal expansion of the circuit board in a direction perpendicular to the main surface. 5. The circuit board according to claim 4, wherein the recess is formed by utilizing a difference between a coefficient of thermal expansion of the metal via and a coefficient of thermal expansion of the circuit board in a direction perpendicular to the main surface. Method.

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